| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.03 | 95.26 | 93.87 | 98.31 | 92.52 | 97.21 | 96.89 | 98.18 |
| T1270 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.1209333280 | Feb 09 03:52:21 AM UTC 25 | Feb 09 03:52:49 AM UTC 25 | 15355500 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1413308827 | Feb 09 03:52:25 AM UTC 25 | Feb 09 03:52:51 AM UTC 25 | 23804400 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2479055344 | Feb 09 03:52:29 AM UTC 25 | Feb 09 03:52:54 AM UTC 25 | 14274000 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.2826927459 | Feb 09 03:52:35 AM UTC 25 | Feb 09 03:52:58 AM UTC 25 | 55544000 ps | ||
| T248 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1410409519 | Feb 09 03:45:01 AM UTC 25 | Feb 09 03:55:29 AM UTC 25 | 721826800 ps | ||
| T249 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.648653373 | Feb 09 03:45:46 AM UTC 25 | Feb 09 03:55:37 AM UTC 25 | 355078800 ps | ||
| T365 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.427572070 | Feb 09 03:45:31 AM UTC 25 | Feb 09 03:55:40 AM UTC 25 | 687127900 ps | ||
| T367 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1679541471 | Feb 09 03:46:44 AM UTC 25 | Feb 09 03:55:41 AM UTC 25 | 189705900 ps | ||
| T366 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3115068288 | Feb 09 03:46:07 AM UTC 25 | Feb 09 03:56:20 AM UTC 25 | 673692900 ps | ||
| T368 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1608606593 | Feb 09 03:43:59 AM UTC 25 | Feb 09 03:56:24 AM UTC 25 | 629658700 ps | ||
| T369 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2990239670 | Feb 09 03:43:20 AM UTC 25 | Feb 09 03:56:35 AM UTC 25 | 679928800 ps | ||
| T371 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2359956472 | Feb 09 03:47:07 AM UTC 25 | Feb 09 03:56:47 AM UTC 25 | 826644700 ps | ||
| T370 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.671916304 | Feb 09 03:47:31 AM UTC 25 | Feb 09 03:57:27 AM UTC 25 | 182464400 ps | ||
| T375 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2324803008 | Feb 09 03:46:29 AM UTC 25 | Feb 09 03:57:42 AM UTC 25 | 241772900 ps | ||
| T372 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.486171854 | Feb 09 03:47:52 AM UTC 25 | Feb 09 03:58:44 AM UTC 25 | 1406335800 ps | ||
| T379 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.463858380 | Feb 09 03:48:37 AM UTC 25 | Feb 09 04:00:11 AM UTC 25 | 352304800 ps | ||
| T373 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3405217196 | Feb 09 03:49:08 AM UTC 25 | Feb 09 04:02:29 AM UTC 25 | 180034000 ps | ||
| T376 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.978818875 | Feb 09 03:41:41 AM UTC 25 | Feb 09 04:04:02 AM UTC 25 | 1690387900 ps | ||
| T374 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1394596477 | Feb 09 03:44:33 AM UTC 25 | Feb 09 04:04:22 AM UTC 25 | 665111300 ps | ||
| T377 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3650117208 | Feb 09 03:48:10 AM UTC 25 | Feb 09 04:05:37 AM UTC 25 | 3237744700 ps | ||
| T363 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1324406373 | Feb 09 03:49:37 AM UTC 25 | Feb 09 04:11:24 AM UTC 25 | 2164567400 ps | ||
| T378 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.430881858 | Feb 09 03:50:43 AM UTC 25 | Feb 09 04:14:15 AM UTC 25 | 3511122400 ps | ||
| T364 | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3099637362 | Feb 09 03:50:10 AM UTC 25 | Feb 09 04:17:40 AM UTC 25 | 968745100 ps |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.248630074 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2009719300 ps |
| CPU time | 74.59 seconds |
| Started | Feb 09 04:58:40 AM UTC 25 |
| Finished | Feb 09 04:59:56 AM UTC 25 |
| Peak memory | 271260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248630074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.248630074 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2245637254 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 424907100 ps |
| CPU time | 31.59 seconds |
| Started | Feb 09 03:42:20 AM UTC 25 |
| Finished | Feb 09 03:42:53 AM UTC 25 |
| Peak memory | 284276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2245637254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.2245637254 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.1699080481 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 34649900 ps |
| CPU time | 137.31 seconds |
| Started | Feb 09 04:58:30 AM UTC 25 |
| Finished | Feb 09 05:00:50 AM UTC 25 |
| Peak memory | 271120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699080481 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.1699080481 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.108944421 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10464581100 ps |
| CPU time | 584.82 seconds |
| Started | Feb 09 04:58:32 AM UTC 25 |
| Finished | Feb 09 05:08:24 AM UTC 25 |
| Peak memory | 283424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=108944421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_mp_regions.108944421 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3801232108 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1228550300 ps |
| CPU time | 181.33 seconds |
| Started | Feb 09 04:59:17 AM UTC 25 |
| Finished | Feb 09 05:02:22 AM UTC 25 |
| Peak memory | 306048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3801232108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3801232108 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.4197907027 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 996341700 ps |
| CPU time | 86.81 seconds |
| Started | Feb 09 04:58:46 AM UTC 25 |
| Finished | Feb 09 05:00:15 AM UTC 25 |
| Peak memory | 271168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197907027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.4197907027 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.689762488 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 190222662500 ps |
| CPU time | 1091.76 seconds |
| Started | Feb 09 05:03:53 AM UTC 25 |
| Finished | Feb 09 05:22:17 AM UTC 25 |
| Peak memory | 275076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689762488 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.689762488 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.267237677 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1514418900 ps |
| CPU time | 6661.43 seconds |
| Started | Feb 09 05:16:09 AM UTC 25 |
| Finished | Feb 09 07:08:16 AM UTC 25 |
| Peak memory | 312196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267237677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.267237677 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1472068857 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1561238200 ps |
| CPU time | 222.62 seconds |
| Started | Feb 09 04:59:17 AM UTC 25 |
| Finished | Feb 09 05:03:03 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147206885 7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.1472068857 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2918500367 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 13702294600 ps |
| CPU time | 144.15 seconds |
| Started | Feb 09 03:42:14 AM UTC 25 |
| Finished | Feb 09 03:44:41 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918500367 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.2918500367 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.4181251224 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 477053600 ps |
| CPU time | 28.93 seconds |
| Started | Feb 09 04:58:32 AM UTC 25 |
| Finished | Feb 09 04:59:02 AM UTC 25 |
| Peak memory | 275172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181251224 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.4181251224 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.797387616 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2701079300 ps |
| CPU time | 587.18 seconds |
| Started | Feb 09 04:58:29 AM UTC 25 |
| Finished | Feb 09 05:08:23 AM UTC 25 |
| Peak memory | 275120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797387616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.797387616 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2254425767 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 160592000 ps |
| CPU time | 25.2 seconds |
| Started | Feb 09 05:09:56 AM UTC 25 |
| Finished | Feb 09 05:10:23 AM UTC 25 |
| Peak memory | 271216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_r d_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2254425767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_i ntg.2254425767 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.2920946901 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 757393600 ps |
| CPU time | 174.78 seconds |
| Started | Feb 09 05:00:23 AM UTC 25 |
| Finished | Feb 09 05:03:21 AM UTC 25 |
| Peak memory | 306080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920946901 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.2920946901 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.4157671718 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 48273400 ps |
| CPU time | 177.42 seconds |
| Started | Feb 09 05:04:07 AM UTC 25 |
| Finished | Feb 09 05:07:07 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157671718 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.4157671718 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2075968971 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 62553184200 ps |
| CPU time | 1221.92 seconds |
| Started | Feb 09 05:10:31 AM UTC 25 |
| Finished | Feb 09 05:31:07 AM UTC 25 |
| Peak memory | 346776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_0 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2075968971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2075968971 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2855482651 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 58820600 ps |
| CPU time | 27.16 seconds |
| Started | Feb 09 03:45:04 AM UTC 25 |
| Finished | Feb 09 03:45:33 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855482651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2855482651 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3342952342 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 77528500 ps |
| CPU time | 167.21 seconds |
| Started | Feb 09 05:42:55 AM UTC 25 |
| Finished | Feb 09 05:45:46 AM UTC 25 |
| Peak memory | 271228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342952342 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.3342952342 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.2216698862 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 77777600 ps |
| CPU time | 191.81 seconds |
| Started | Feb 09 06:15:05 AM UTC 25 |
| Finished | Feb 09 06:18:21 AM UTC 25 |
| Peak memory | 271228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216698862 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.2216698862 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.791063809 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 50606800 ps |
| CPU time | 37.56 seconds |
| Started | Feb 09 03:43:05 AM UTC 25 |
| Finished | Feb 09 03:43:44 AM UTC 25 |
| Peak memory | 284404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=791063809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_csr_mem_rw_with_rand_reset.791063809 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2359956472 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 826644700 ps |
| CPU time | 572.66 seconds |
| Started | Feb 09 03:47:07 AM UTC 25 |
| Finished | Feb 09 03:56:47 AM UTC 25 |
| Peak memory | 273988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359956472 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.2359956472 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1237130030 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 10031493700 ps |
| CPU time | 133.89 seconds |
| Started | Feb 09 05:30:49 AM UTC 25 |
| Finished | Feb 09 05:33:05 AM UTC 25 |
| Peak memory | 275272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1237130030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.flash_ctrl_hw_prog_rma_wipe_err.1237130030 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.872116680 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 673287700 ps |
| CPU time | 74.73 seconds |
| Started | Feb 09 05:09:28 AM UTC 25 |
| Finished | Feb 09 05:10:45 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872116680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.872116680 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.330798051 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 7297146500 ps |
| CPU time | 222.21 seconds |
| Started | Feb 09 04:59:55 AM UTC 25 |
| Finished | Feb 09 05:03:40 AM UTC 25 |
| Peak memory | 300284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=330798051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_rw_derr.330798051 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1012339677 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 33709700 ps |
| CPU time | 23.74 seconds |
| Started | Feb 09 05:30:22 AM UTC 25 |
| Finished | Feb 09 05:30:47 AM UTC 25 |
| Peak memory | 273384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1012339677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1012339677 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.4191121428 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 164380800 ps |
| CPU time | 17.7 seconds |
| Started | Feb 09 05:34:08 AM UTC 25 |
| Finished | Feb 09 05:34:27 AM UTC 25 |
| Peak memory | 271112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191121428 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.4191121428 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.440812069 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3426110100 ps |
| CPU time | 112.02 seconds |
| Started | Feb 09 05:05:32 AM UTC 25 |
| Finished | Feb 09 05:07:27 AM UTC 25 |
| Peak memory | 271172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440812069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.440812069 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3526338371 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 88342900 ps |
| CPU time | 35.68 seconds |
| Started | Feb 09 03:46:07 AM UTC 25 |
| Finished | Feb 09 03:46:45 AM UTC 25 |
| Peak memory | 274100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526338371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3526338371 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3457156379 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5437033200 ps |
| CPU time | 149.85 seconds |
| Started | Feb 09 05:52:13 AM UTC 25 |
| Finished | Feb 09 05:54:46 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457156379 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.3457156379 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.386718765 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 384426966500 ps |
| CPU time | 2555.97 seconds |
| Started | Feb 09 05:17:59 AM UTC 25 |
| Finished | Feb 09 06:01:00 AM UTC 25 |
| Peak memory | 275232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386718765 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.386718765 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1556897437 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 10834739100 ps |
| CPU time | 113.9 seconds |
| Started | Feb 09 04:58:26 AM UTC 25 |
| Finished | Feb 09 05:00:23 AM UTC 25 |
| Peak memory | 270952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556897437 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.1556897437 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1436393860 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 649345700 ps |
| CPU time | 139.1 seconds |
| Started | Feb 09 05:19:06 AM UTC 25 |
| Finished | Feb 09 05:21:27 AM UTC 25 |
| Peak memory | 271232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436393860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1436393860 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.3178253090 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 15534000 ps |
| CPU time | 19.11 seconds |
| Started | Feb 09 05:03:18 AM UTC 25 |
| Finished | Feb 09 05:03:38 AM UTC 25 |
| Peak memory | 275284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 78253090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3178253090 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.656461573 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3401833100 ps |
| CPU time | 525.21 seconds |
| Started | Feb 09 04:59:12 AM UTC 25 |
| Finished | Feb 09 05:08:04 AM UTC 25 |
| Peak memory | 330584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656461573 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.656461573 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2360204167 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 478427600 ps |
| CPU time | 54.8 seconds |
| Started | Feb 09 05:16:40 AM UTC 25 |
| Finished | Feb 09 05:17:37 AM UTC 25 |
| Peak memory | 273188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360204167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fs_sup.2360204167 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.71585175 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 151351100 ps |
| CPU time | 16.02 seconds |
| Started | Feb 09 03:42:53 AM UTC 25 |
| Finished | Feb 09 03:43:10 AM UTC 25 |
| Peak memory | 273920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71585175 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.71585175 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1256307612 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 32800100 ps |
| CPU time | 58.43 seconds |
| Started | Feb 09 05:01:26 AM UTC 25 |
| Finished | Feb 09 05:02:26 AM UTC 25 |
| Peak memory | 285588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256 307612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1256307612 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3325037192 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 248504100 ps |
| CPU time | 551.48 seconds |
| Started | Feb 09 03:42:30 AM UTC 25 |
| Finished | Feb 09 03:51:47 AM UTC 25 |
| Peak memory | 274112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325037192 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.3325037192 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3723644206 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 10025909000 ps |
| CPU time | 96.31 seconds |
| Started | Feb 09 05:42:31 AM UTC 25 |
| Finished | Feb 09 05:44:10 AM UTC 25 |
| Peak memory | 316148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3723644206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.flash_ctrl_hw_prog_rma_wipe_err.3723644206 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.2272323933 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 147710100 ps |
| CPU time | 35.9 seconds |
| Started | Feb 09 06:00:33 AM UTC 25 |
| Finished | Feb 09 06:01:11 AM UTC 25 |
| Peak memory | 285624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272323933 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.2272323933 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.812447745 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 16754000 ps |
| CPU time | 22.42 seconds |
| Started | Feb 09 05:02:46 AM UTC 25 |
| Finished | Feb 09 05:03:10 AM UTC 25 |
| Peak memory | 275480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=812447745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.812447745 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2689479230 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 25134500 ps |
| CPU time | 27.17 seconds |
| Started | Feb 09 03:41:41 AM UTC 25 |
| Finished | Feb 09 03:42:10 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689479230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2689479230 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3933399986 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 25924338900 ps |
| CPU time | 616.03 seconds |
| Started | Feb 09 05:04:14 AM UTC 25 |
| Finished | Feb 09 05:14:37 AM UTC 25 |
| Peak memory | 283696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3933399986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.f lash_ctrl_mp_regions.3933399986 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2475777974 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1388265600 ps |
| CPU time | 169.05 seconds |
| Started | Feb 09 05:50:39 AM UTC 25 |
| Finished | Feb 09 05:53:31 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475777974 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.2475777974 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.2692808740 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 158675700 ps |
| CPU time | 35.27 seconds |
| Started | Feb 09 06:20:25 AM UTC 25 |
| Finished | Feb 09 06:21:02 AM UTC 25 |
| Peak memory | 285508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 92808740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.2692808740 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.340288678 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 884689800 ps |
| CPU time | 34.63 seconds |
| Started | Feb 09 05:30:17 AM UTC 25 |
| Finished | Feb 09 05:30:53 AM UTC 25 |
| Peak memory | 275412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=340288678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 4.flash_ctrl_phy_arb_redun.340288678 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1473931660 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1194287500 ps |
| CPU time | 1018 seconds |
| Started | Feb 09 04:58:35 AM UTC 25 |
| Finished | Feb 09 05:15:44 AM UTC 25 |
| Peak memory | 285416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473931660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1473931660 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.577137171 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 84206000 ps |
| CPU time | 47.53 seconds |
| Started | Feb 09 05:01:43 AM UTC 25 |
| Finished | Feb 09 05:02:32 AM UTC 25 |
| Peak memory | 285628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577137171 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.577137171 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.80288581 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4655068100 ps |
| CPU time | 188.98 seconds |
| Started | Feb 09 05:10:58 AM UTC 25 |
| Finished | Feb 09 05:14:09 AM UTC 25 |
| Peak memory | 273172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80288581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.80288581 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.2482452915 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2937936100 ps |
| CPU time | 127.85 seconds |
| Started | Feb 09 05:28:02 AM UTC 25 |
| Finished | Feb 09 05:30:12 AM UTC 25 |
| Peak memory | 302240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482452915 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.2482452915 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.978818875 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1690387900 ps |
| CPU time | 1325.98 seconds |
| Started | Feb 09 03:41:41 AM UTC 25 |
| Finished | Feb 09 04:04:02 AM UTC 25 |
| Peak memory | 273920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978818875 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.978818875 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.4109986376 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 42500000 ps |
| CPU time | 24.27 seconds |
| Started | Feb 09 05:10:29 AM UTC 25 |
| Finished | Feb 09 05:10:55 AM UTC 25 |
| Peak memory | 293312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct =4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109986376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ph y_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.4109986376 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.4184603584 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1724439100 ps |
| CPU time | 6587.66 seconds |
| Started | Feb 09 05:22:57 AM UTC 25 |
| Finished | Feb 09 07:13:51 AM UTC 25 |
| Peak memory | 316276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184603584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4184603584 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4094782536 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 58209600 ps |
| CPU time | 36.13 seconds |
| Started | Feb 09 03:45:29 AM UTC 25 |
| Finished | Feb 09 03:46:07 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094782536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.4094782536 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.3473243812 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 38351200 ps |
| CPU time | 42.13 seconds |
| Started | Feb 09 05:48:51 AM UTC 25 |
| Finished | Feb 09 05:49:35 AM UTC 25 |
| Peak memory | 289692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473243812 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.3473243812 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.839956596 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 9537961700 ps |
| CPU time | 412.84 seconds |
| Started | Feb 09 06:04:03 AM UTC 25 |
| Finished | Feb 09 06:11:01 AM UTC 25 |
| Peak memory | 320344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839956596 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.839956596 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.3084614404 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 402138500 ps |
| CPU time | 40.2 seconds |
| Started | Feb 09 05:11:24 AM UTC 25 |
| Finished | Feb 09 05:12:06 AM UTC 25 |
| Peak memory | 273064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084614404 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3084614404 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2495098142 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 68178540900 ps |
| CPU time | 192.67 seconds |
| Started | Feb 09 05:00:50 AM UTC 25 |
| Finished | Feb 09 05:04:06 AM UTC 25 |
| Peak memory | 271176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2495098142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_intr_wr_slow_flash.2495098142 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.3026631879 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 525241200 ps |
| CPU time | 131.98 seconds |
| Started | Feb 09 04:59:11 AM UTC 25 |
| Finished | Feb 09 05:01:25 AM UTC 25 |
| Peak memory | 291664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026631 879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.3026631879 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3750663345 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 16209600 ps |
| CPU time | 28.9 seconds |
| Started | Feb 09 05:34:01 AM UTC 25 |
| Finished | Feb 09 05:34:31 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 50663345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_s eed_err.3750663345 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1324406373 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2164567400 ps |
| CPU time | 1292.6 seconds |
| Started | Feb 09 03:49:37 AM UTC 25 |
| Finished | Feb 09 04:11:24 AM UTC 25 |
| Peak memory | 274052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324406373 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.1324406373 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1428949006 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 10012172300 ps |
| CPU time | 127.85 seconds |
| Started | Feb 09 05:03:22 AM UTC 25 |
| Finished | Feb 09 05:05:32 AM UTC 25 |
| Peak memory | 330736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1428949006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_prog_rma_wipe_err.1428949006 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3031848214 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 25102200 ps |
| CPU time | 16.4 seconds |
| Started | Feb 09 05:10:33 AM UTC 25 |
| Finished | Feb 09 05:10:51 AM UTC 25 |
| Peak memory | 275676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 31848214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_s eed_err.3031848214 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.4044741798 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 98488400 ps |
| CPU time | 26.25 seconds |
| Started | Feb 09 05:02:27 AM UTC 25 |
| Finished | Feb 09 05:02:55 AM UTC 25 |
| Peak memory | 295100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044741798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.4044741798 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.2840284000 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 15391826200 ps |
| CPU time | 235.02 seconds |
| Started | Feb 09 05:14:49 AM UTC 25 |
| Finished | Feb 09 05:18:48 AM UTC 25 |
| Peak memory | 304056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2840284000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ ctrl_rw_derr.2840284000 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.2877579874 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 919321700 ps |
| CPU time | 3356.73 seconds |
| Started | Feb 09 04:58:33 AM UTC 25 |
| Finished | Feb 09 05:55:04 AM UTC 25 |
| Peak memory | 273184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877579874 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2877579874 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.436356995 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 21602464100 ps |
| CPU time | 234.31 seconds |
| Started | Feb 09 05:21:39 AM UTC 25 |
| Finished | Feb 09 05:25:37 AM UTC 25 |
| Peak memory | 304296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436356995 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.436356995 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1761337516 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 16617200 ps |
| CPU time | 23.38 seconds |
| Started | Feb 09 05:16:32 AM UTC 25 |
| Finished | Feb 09 05:16:57 AM UTC 25 |
| Peak memory | 275640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1761337516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1761337516 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.890625994 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3950336400 ps |
| CPU time | 120.6 seconds |
| Started | Feb 09 05:34:19 AM UTC 25 |
| Finished | Feb 09 05:36:22 AM UTC 25 |
| Peak memory | 274964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890625994 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.890625994 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3581432333 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 439003600 ps |
| CPU time | 93.84 seconds |
| Started | Feb 09 05:02:16 AM UTC 25 |
| Finished | Feb 09 05:03:52 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581432333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3581432333 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1287680740 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 25638600 ps |
| CPU time | 16.77 seconds |
| Started | Feb 09 03:48:01 AM UTC 25 |
| Finished | Feb 09 03:48:20 AM UTC 25 |
| Peak memory | 271928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287680740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1287680740 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.3944648374 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1837395000 ps |
| CPU time | 80.58 seconds |
| Started | Feb 09 06:18:14 AM UTC 25 |
| Finished | Feb 09 06:19:36 AM UTC 25 |
| Peak memory | 275368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944648374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3944648374 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.1192597242 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1470528700 ps |
| CPU time | 100.15 seconds |
| Started | Feb 09 06:18:41 AM UTC 25 |
| Finished | Feb 09 06:20:24 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192597242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1192597242 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.526786404 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3488252500 ps |
| CPU time | 111.06 seconds |
| Started | Feb 09 06:19:09 AM UTC 25 |
| Finished | Feb 09 06:21:03 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526786404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.526786404 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.606088588 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2516956700 ps |
| CPU time | 105.38 seconds |
| Started | Feb 09 06:15:33 AM UTC 25 |
| Finished | Feb 09 06:17:21 AM UTC 25 |
| Peak memory | 275244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606088588 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.606088588 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.1359043710 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 61029400 ps |
| CPU time | 19.94 seconds |
| Started | Feb 09 05:03:09 AM UTC 25 |
| Finished | Feb 09 05:03:30 AM UTC 25 |
| Peak memory | 275148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359043710 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.1359043710 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.376042371 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 636439400 ps |
| CPU time | 28.54 seconds |
| Started | Feb 09 05:02:55 AM UTC 25 |
| Finished | Feb 09 05:03:25 AM UTC 25 |
| Peak memory | 275400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=376042371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.flash_ctrl_phy_arb_redun.376042371 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.3332025778 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 413999314400 ps |
| CPU time | 2924.22 seconds |
| Started | Feb 09 04:58:32 AM UTC 25 |
| Finished | Feb 09 05:47:45 AM UTC 25 |
| Peak memory | 275228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332025778 -assert nopostproc +U VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.3332025778 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.726343189 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 270228591600 ps |
| CPU time | 867.19 seconds |
| Started | Feb 09 05:49:53 AM UTC 25 |
| Finished | Feb 09 06:04:31 AM UTC 25 |
| Peak memory | 275144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726343189 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_reset.726343189 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4058677391 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 720935779000 ps |
| CPU time | 2881.96 seconds |
| Started | Feb 09 04:58:32 AM UTC 25 |
| Finished | Feb 09 05:47:05 AM UTC 25 |
| Peak memory | 273028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058677391 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.4058677391 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1898911441 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 6971242200 ps |
| CPU time | 457.53 seconds |
| Started | Feb 09 05:31:34 AM UTC 25 |
| Finished | Feb 09 05:39:17 AM UTC 25 |
| Peak memory | 324776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898911441 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.1898911441 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2970881249 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 126338200 ps |
| CPU time | 76.7 seconds |
| Started | Feb 09 03:42:09 AM UTC 25 |
| Finished | Feb 09 03:43:28 AM UTC 25 |
| Peak memory | 271864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970881249 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.2970881249 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.3406491810 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 825467900 ps |
| CPU time | 38.82 seconds |
| Started | Feb 09 05:16:50 AM UTC 25 |
| Finished | Feb 09 05:17:31 AM UTC 25 |
| Peak memory | 275456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3406491810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_phy_arb_redun.3406491810 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2327150278 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 835406800 ps |
| CPU time | 29.24 seconds |
| Started | Feb 09 05:23:35 AM UTC 25 |
| Finished | Feb 09 05:24:05 AM UTC 25 |
| Peak memory | 275408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2327150278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_phy_arb_redun.2327150278 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3031604988 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 15646500 ps |
| CPU time | 21.06 seconds |
| Started | Feb 09 05:10:33 AM UTC 25 |
| Finished | Feb 09 05:10:55 AM UTC 25 |
| Peak memory | 275320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 31604988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3031604988 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3405217196 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 180034000 ps |
| CPU time | 791.59 seconds |
| Started | Feb 09 03:49:08 AM UTC 25 |
| Finished | Feb 09 04:02:29 AM UTC 25 |
| Peak memory | 273988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405217196 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.3405217196 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.1928898809 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 74520700 ps |
| CPU time | 40.33 seconds |
| Started | Feb 09 05:02:04 AM UTC 25 |
| Finished | Feb 09 05:02:46 AM UTC 25 |
| Peak memory | 285508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 28898809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.1928898809 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.1696295379 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 16204300 ps |
| CPU time | 39.66 seconds |
| Started | Feb 09 05:51:31 AM UTC 25 |
| Finished | Feb 09 05:52:12 AM UTC 25 |
| Peak memory | 285504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 96295379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.1696295379 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.3198868869 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 35798000 ps |
| CPU time | 36.74 seconds |
| Started | Feb 09 05:54:00 AM UTC 25 |
| Finished | Feb 09 05:54:38 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 98868869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.3198868869 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.2931613896 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 11246400 ps |
| CPU time | 43.11 seconds |
| Started | Feb 09 06:02:50 AM UTC 25 |
| Finished | Feb 09 06:03:34 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 31613896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.2931613896 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1478009153 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 11152800 ps |
| CPU time | 37.14 seconds |
| Started | Feb 09 06:06:42 AM UTC 25 |
| Finished | Feb 09 06:07:21 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14 78009153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.1478009153 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.749946460 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 39676200 ps |
| CPU time | 38.13 seconds |
| Started | Feb 09 06:08:39 AM UTC 25 |
| Finished | Feb 09 06:09:19 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74 9946460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.749946460 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.3863207568 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 359231300 ps |
| CPU time | 74.17 seconds |
| Started | Feb 09 06:10:10 AM UTC 25 |
| Finished | Feb 09 06:11:26 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863207568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3863207568 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.2189222317 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 33643600 ps |
| CPU time | 41.61 seconds |
| Started | Feb 09 06:13:36 AM UTC 25 |
| Finished | Feb 09 06:14:19 AM UTC 25 |
| Peak memory | 285544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 89222317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.2189222317 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.3233867261 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3197758800 ps |
| CPU time | 107.82 seconds |
| Started | Feb 09 06:15:31 AM UTC 25 |
| Finished | Feb 09 06:17:21 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233867261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3233867261 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.2169019393 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 23170600 ps |
| CPU time | 28.07 seconds |
| Started | Feb 09 06:20:14 AM UTC 25 |
| Finished | Feb 09 06:20:44 AM UTC 25 |
| Peak memory | 285504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 69019393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.2169019393 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2443407915 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 15773100 ps |
| CPU time | 39.06 seconds |
| Started | Feb 09 05:29:40 AM UTC 25 |
| Finished | Feb 09 05:30:20 AM UTC 25 |
| Peak memory | 285516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 43407915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.2443407915 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.15016788 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 115328900 ps |
| CPU time | 155.33 seconds |
| Started | Feb 09 06:21:31 AM UTC 25 |
| Finished | Feb 09 06:24:09 AM UTC 25 |
| Peak memory | 271316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15016788 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.15016788 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.2847472598 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2843976700 ps |
| CPU time | 223.31 seconds |
| Started | Feb 09 06:12:51 AM UTC 25 |
| Finished | Feb 09 06:16:38 AM UTC 25 |
| Peak memory | 304004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847472598 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.2847472598 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1962779331 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 60571900 ps |
| CPU time | 36.26 seconds |
| Started | Feb 09 03:41:41 AM UTC 25 |
| Finished | Feb 09 03:42:19 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962779331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1962779331 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2547400136 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 44517000 ps |
| CPU time | 21.71 seconds |
| Started | Feb 09 05:03:06 AM UTC 25 |
| Finished | Feb 09 05:03:29 AM UTC 25 |
| Peak memory | 271340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct =4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547400136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ph y_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2547400136 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3796927530 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2493057300 ps |
| CPU time | 3149.49 seconds |
| Started | Feb 09 04:58:40 AM UTC 25 |
| Finished | Feb 09 05:51:42 AM UTC 25 |
| Peak memory | 275216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796927530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.3796927530 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.1344527995 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 11828895100 ps |
| CPU time | 466.61 seconds |
| Started | Feb 09 05:00:15 AM UTC 25 |
| Finished | Feb 09 05:08:08 AM UTC 25 |
| Peak memory | 337032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344527 995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integrity.1344527995 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.83138875 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 570928844000 ps |
| CPU time | 2691.46 seconds |
| Started | Feb 09 05:25:09 AM UTC 25 |
| Finished | Feb 09 06:10:29 AM UTC 25 |
| Peak memory | 275224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83138875 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.83138875 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.476291703 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 755582100 ps |
| CPU time | 26.53 seconds |
| Started | Feb 09 05:38:30 AM UTC 25 |
| Finished | Feb 09 05:38:58 AM UTC 25 |
| Peak memory | 273116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476291703 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.476291703 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.974041673 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2175569100 ps |
| CPU time | 189.19 seconds |
| Started | Feb 09 05:47:26 AM UTC 25 |
| Finished | Feb 09 05:50:38 AM UTC 25 |
| Peak memory | 306084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974041673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.974041673 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1385178592 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 309285900 ps |
| CPU time | 38.01 seconds |
| Started | Feb 09 03:42:15 AM UTC 25 |
| Finished | Feb 09 03:42:54 AM UTC 25 |
| Peak memory | 271996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385178592 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.1385178592 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4056820414 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 44500200 ps |
| CPU time | 18.93 seconds |
| Started | Feb 09 03:42:11 AM UTC 25 |
| Finished | Feb 09 03:42:31 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056820414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.4056820414 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2625856794 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 63751300 ps |
| CPU time | 26.53 seconds |
| Started | Feb 09 03:42:04 AM UTC 25 |
| Finished | Feb 09 03:42:32 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625856794 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.2625856794 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2613952565 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 15519200 ps |
| CPU time | 23.95 seconds |
| Started | Feb 09 03:41:44 AM UTC 25 |
| Finished | Feb 09 03:42:09 AM UTC 25 |
| Peak memory | 272128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613952565 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/f lash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.2613952565 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.724929976 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 279484700 ps |
| CPU time | 33.56 seconds |
| Started | Feb 09 03:42:17 AM UTC 25 |
| Finished | Feb 09 03:42:52 AM UTC 25 |
| Peak memory | 273908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724929976 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.724929976 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.131957067 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 17726200 ps |
| CPU time | 30.82 seconds |
| Started | Feb 09 03:41:41 AM UTC 25 |
| Finished | Feb 09 03:42:13 AM UTC 25 |
| Peak memory | 261460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131957067 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.131957067 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.88033769 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 78946400 ps |
| CPU time | 30.87 seconds |
| Started | Feb 09 03:41:41 AM UTC 25 |
| Finished | Feb 09 03:42:13 AM UTC 25 |
| Peak memory | 261552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88 033769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_erro rs_with_csr_rw.88033769 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2551457393 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1836365200 ps |
| CPU time | 69.83 seconds |
| Started | Feb 09 03:43:00 AM UTC 25 |
| Finished | Feb 09 03:44:12 AM UTC 25 |
| Peak memory | 271864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551457393 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.2551457393 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1032647234 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3016477000 ps |
| CPU time | 108.87 seconds |
| Started | Feb 09 03:42:55 AM UTC 25 |
| Finished | Feb 09 03:44:46 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032647234 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.1032647234 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.559342401 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 42847300 ps |
| CPU time | 48.67 seconds |
| Started | Feb 09 03:42:53 AM UTC 25 |
| Finished | Feb 09 03:43:43 AM UTC 25 |
| Peak memory | 272064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559342401 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.559342401 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2825413670 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 24385900 ps |
| CPU time | 29.72 seconds |
| Started | Feb 09 03:42:54 AM UTC 25 |
| Finished | Feb 09 03:43:25 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825413670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.2825413670 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.670396155 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 14871500 ps |
| CPU time | 16.09 seconds |
| Started | Feb 09 03:42:47 AM UTC 25 |
| Finished | Feb 09 03:43:05 AM UTC 25 |
| Peak memory | 271724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670396155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.670396155 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1037268422 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 14303400 ps |
| CPU time | 26.82 seconds |
| Started | Feb 09 03:42:52 AM UTC 25 |
| Finished | Feb 09 03:43:20 AM UTC 25 |
| Peak memory | 271872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037268422 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/f lash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.1037268422 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4229529570 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 436437800 ps |
| CPU time | 32.12 seconds |
| Started | Feb 09 03:43:00 AM UTC 25 |
| Finished | Feb 09 03:43:34 AM UTC 25 |
| Peak memory | 274108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229529570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.4229529570 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1920645075 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 20679600 ps |
| CPU time | 18.66 seconds |
| Started | Feb 09 03:42:32 AM UTC 25 |
| Finished | Feb 09 03:42:52 AM UTC 25 |
| Peak memory | 261688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920645075 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.1920645075 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.211909984 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 72710200 ps |
| CPU time | 24.5 seconds |
| Started | Feb 09 03:42:33 AM UTC 25 |
| Finished | Feb 09 03:42:59 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 1909984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_err ors_with_csr_rw.211909984 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3959638459 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 711206100 ps |
| CPU time | 30.84 seconds |
| Started | Feb 09 03:42:27 AM UTC 25 |
| Finished | Feb 09 03:42:59 AM UTC 25 |
| Peak memory | 274104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959638459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3959638459 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4157691600 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 82440300 ps |
| CPU time | 33.52 seconds |
| Started | Feb 09 03:47:02 AM UTC 25 |
| Finished | Feb 09 03:47:37 AM UTC 25 |
| Peak memory | 290552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4157691600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.4157691600 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2046021717 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 138257700 ps |
| CPU time | 31.4 seconds |
| Started | Feb 09 03:46:57 AM UTC 25 |
| Finished | Feb 09 03:47:30 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046021717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.2046021717 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.276028422 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 26852100 ps |
| CPU time | 26.08 seconds |
| Started | Feb 09 03:46:52 AM UTC 25 |
| Finished | Feb 09 03:47:19 AM UTC 25 |
| Peak memory | 271988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276028422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.276028422 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3300687161 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 227147900 ps |
| CPU time | 62.39 seconds |
| Started | Feb 09 03:46:59 AM UTC 25 |
| Finished | Feb 09 03:48:03 AM UTC 25 |
| Peak memory | 271992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300687161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3300687161 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.628867382 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 14266400 ps |
| CPU time | 21.58 seconds |
| Started | Feb 09 03:46:46 AM UTC 25 |
| Finished | Feb 09 03:47:09 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628867382 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.628867382 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3034271713 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 31514100 ps |
| CPU time | 22.62 seconds |
| Started | Feb 09 03:46:50 AM UTC 25 |
| Finished | Feb 09 03:47:14 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 34271713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_e rrors_with_csr_rw.3034271713 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1205586164 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 35720100 ps |
| CPU time | 29.47 seconds |
| Started | Feb 09 03:46:43 AM UTC 25 |
| Finished | Feb 09 03:47:13 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205586164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.1205586164 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1679541471 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 189705900 ps |
| CPU time | 531.04 seconds |
| Started | Feb 09 03:46:44 AM UTC 25 |
| Finished | Feb 09 03:55:41 AM UTC 25 |
| Peak memory | 273980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679541471 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.1679541471 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.167068217 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 224227300 ps |
| CPU time | 32.1 seconds |
| Started | Feb 09 03:47:17 AM UTC 25 |
| Finished | Feb 09 03:47:51 AM UTC 25 |
| Peak memory | 284408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=167068217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 1.flash_ctrl_csr_mem_rw_with_rand_reset.167068217 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1516405883 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 27614700 ps |
| CPU time | 29.51 seconds |
| Started | Feb 09 03:47:14 AM UTC 25 |
| Finished | Feb 09 03:47:45 AM UTC 25 |
| Peak memory | 273740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516405883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.1516405883 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.242962897 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 17153700 ps |
| CPU time | 17.3 seconds |
| Started | Feb 09 03:47:12 AM UTC 25 |
| Finished | Feb 09 03:47:31 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242962897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.242962897 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2710043205 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 115971600 ps |
| CPU time | 31.2 seconds |
| Started | Feb 09 03:47:14 AM UTC 25 |
| Finished | Feb 09 03:47:47 AM UTC 25 |
| Peak memory | 273776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710043205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2710043205 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3473033786 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 25191600 ps |
| CPU time | 25.86 seconds |
| Started | Feb 09 03:47:09 AM UTC 25 |
| Finished | Feb 09 03:47:36 AM UTC 25 |
| Peak memory | 261624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473033786 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3473033786 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2633912921 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 52324000 ps |
| CPU time | 27.19 seconds |
| Started | Feb 09 03:47:11 AM UTC 25 |
| Finished | Feb 09 03:47:40 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 33912921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_e rrors_with_csr_rw.2633912921 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2561298566 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 45378500 ps |
| CPU time | 32.6 seconds |
| Started | Feb 09 03:47:03 AM UTC 25 |
| Finished | Feb 09 03:47:37 AM UTC 25 |
| Peak memory | 274104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561298566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.2561298566 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2867228649 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 61644400 ps |
| CPU time | 33.3 seconds |
| Started | Feb 09 03:47:46 AM UTC 25 |
| Finished | Feb 09 03:48:21 AM UTC 25 |
| Peak memory | 284272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2867228649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2867228649 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.406860110 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 18470300 ps |
| CPU time | 24.17 seconds |
| Started | Feb 09 03:47:38 AM UTC 25 |
| Finished | Feb 09 03:48:03 AM UTC 25 |
| Peak memory | 274040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406860110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.406860110 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.93160473 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 33628300 ps |
| CPU time | 25.06 seconds |
| Started | Feb 09 03:47:38 AM UTC 25 |
| Finished | Feb 09 03:48:04 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93160473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.93160473 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3593643372 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 118486900 ps |
| CPU time | 51.17 seconds |
| Started | Feb 09 03:47:41 AM UTC 25 |
| Finished | Feb 09 03:48:34 AM UTC 25 |
| Peak memory | 271864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593643372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3593643372 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.949095689 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 20894000 ps |
| CPU time | 29.98 seconds |
| Started | Feb 09 03:47:32 AM UTC 25 |
| Finished | Feb 09 03:48:03 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949095689 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.949095689 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.84878018 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 13075800 ps |
| CPU time | 30.57 seconds |
| Started | Feb 09 03:47:37 AM UTC 25 |
| Finished | Feb 09 03:48:09 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84 878018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_err ors_with_csr_rw.84878018 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.958445434 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 97444700 ps |
| CPU time | 34.19 seconds |
| Started | Feb 09 03:47:21 AM UTC 25 |
| Finished | Feb 09 03:47:56 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958445434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.958445434 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.671916304 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 182464400 ps |
| CPU time | 589.05 seconds |
| Started | Feb 09 03:47:31 AM UTC 25 |
| Finished | Feb 09 03:57:27 AM UTC 25 |
| Peak memory | 273984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671916304 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.671916304 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2147107179 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 843984600 ps |
| CPU time | 30.46 seconds |
| Started | Feb 09 03:48:05 AM UTC 25 |
| Finished | Feb 09 03:48:37 AM UTC 25 |
| Peak memory | 274032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2147107179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2147107179 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1457250074 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 31991900 ps |
| CPU time | 33.03 seconds |
| Started | Feb 09 03:48:04 AM UTC 25 |
| Finished | Feb 09 03:48:38 AM UTC 25 |
| Peak memory | 274108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457250074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.1457250074 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1599897608 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1111570300 ps |
| CPU time | 27.39 seconds |
| Started | Feb 09 03:48:04 AM UTC 25 |
| Finished | Feb 09 03:48:32 AM UTC 25 |
| Peak memory | 271928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599897608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1599897608 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3292382412 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 12572500 ps |
| CPU time | 30.46 seconds |
| Started | Feb 09 03:47:57 AM UTC 25 |
| Finished | Feb 09 03:48:29 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292382412 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3292382412 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.693961008 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 12807200 ps |
| CPU time | 25.1 seconds |
| Started | Feb 09 03:48:00 AM UTC 25 |
| Finished | Feb 09 03:48:26 AM UTC 25 |
| Peak memory | 261760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69 3961008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_er rors_with_csr_rw.693961008 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.122864893 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 87034000 ps |
| CPU time | 32.18 seconds |
| Started | Feb 09 03:47:48 AM UTC 25 |
| Finished | Feb 09 03:48:22 AM UTC 25 |
| Peak memory | 274036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122864893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.122864893 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.486171854 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1406335800 ps |
| CPU time | 643.96 seconds |
| Started | Feb 09 03:47:52 AM UTC 25 |
| Finished | Feb 09 03:58:44 AM UTC 25 |
| Peak memory | 274172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486171854 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.486171854 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2907285585 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 39855900 ps |
| CPU time | 31.51 seconds |
| Started | Feb 09 03:48:33 AM UTC 25 |
| Finished | Feb 09 03:49:06 AM UTC 25 |
| Peak memory | 284280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2907285585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2907285585 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3092750309 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 123188500 ps |
| CPU time | 27.97 seconds |
| Started | Feb 09 03:48:27 AM UTC 25 |
| Finished | Feb 09 03:48:56 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092750309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.3092750309 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2978700943 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 17797300 ps |
| CPU time | 24.68 seconds |
| Started | Feb 09 03:48:22 AM UTC 25 |
| Finished | Feb 09 03:48:48 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978700943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.2978700943 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1165265706 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 389649400 ps |
| CPU time | 67.57 seconds |
| Started | Feb 09 03:48:30 AM UTC 25 |
| Finished | Feb 09 03:49:40 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165265706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1165265706 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1550291489 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 13338800 ps |
| CPU time | 29.2 seconds |
| Started | Feb 09 03:48:21 AM UTC 25 |
| Finished | Feb 09 03:48:52 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550291489 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1550291489 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3247556685 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 33745400 ps |
| CPU time | 31.02 seconds |
| Started | Feb 09 03:48:22 AM UTC 25 |
| Finished | Feb 09 03:48:54 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 47556685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_e rrors_with_csr_rw.3247556685 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.385753896 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 87392500 ps |
| CPU time | 31.51 seconds |
| Started | Feb 09 03:48:05 AM UTC 25 |
| Finished | Feb 09 03:48:38 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385753896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.385753896 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3650117208 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3237744700 ps |
| CPU time | 1036.37 seconds |
| Started | Feb 09 03:48:10 AM UTC 25 |
| Finished | Feb 09 04:05:37 AM UTC 25 |
| Peak memory | 273988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650117208 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.3650117208 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.546364491 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 390941800 ps |
| CPU time | 35.06 seconds |
| Started | Feb 09 03:48:57 AM UTC 25 |
| Finished | Feb 09 03:49:33 AM UTC 25 |
| Peak memory | 284276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=546364491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 5.flash_ctrl_csr_mem_rw_with_rand_reset.546364491 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3339948720 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 34558700 ps |
| CPU time | 25.94 seconds |
| Started | Feb 09 03:48:53 AM UTC 25 |
| Finished | Feb 09 03:49:20 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339948720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.3339948720 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.906238080 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 48720600 ps |
| CPU time | 25.02 seconds |
| Started | Feb 09 03:48:49 AM UTC 25 |
| Finished | Feb 09 03:49:15 AM UTC 25 |
| Peak memory | 271924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906238080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.906238080 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1931760819 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 126418900 ps |
| CPU time | 34.9 seconds |
| Started | Feb 09 03:48:56 AM UTC 25 |
| Finished | Feb 09 03:49:32 AM UTC 25 |
| Peak memory | 273976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931760819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.1931760819 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3911197517 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 34194600 ps |
| CPU time | 28.54 seconds |
| Started | Feb 09 03:48:38 AM UTC 25 |
| Finished | Feb 09 03:49:08 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911197517 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3911197517 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3168984836 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 12639100 ps |
| CPU time | 27.29 seconds |
| Started | Feb 09 03:48:38 AM UTC 25 |
| Finished | Feb 09 03:49:07 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 68984836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_e rrors_with_csr_rw.3168984836 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3643246008 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 143988600 ps |
| CPU time | 31.86 seconds |
| Started | Feb 09 03:48:34 AM UTC 25 |
| Finished | Feb 09 03:49:08 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643246008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.3643246008 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.463858380 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 352304800 ps |
| CPU time | 685.8 seconds |
| Started | Feb 09 03:48:37 AM UTC 25 |
| Finished | Feb 09 04:00:11 AM UTC 25 |
| Peak memory | 271932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463858380 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.463858380 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4024819397 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 241711800 ps |
| CPU time | 29.6 seconds |
| Started | Feb 09 03:49:32 AM UTC 25 |
| Finished | Feb 09 03:50:03 AM UTC 25 |
| Peak memory | 284408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4024819397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.4024819397 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1516293605 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 71994100 ps |
| CPU time | 31.64 seconds |
| Started | Feb 09 03:49:21 AM UTC 25 |
| Finished | Feb 09 03:49:54 AM UTC 25 |
| Peak memory | 273980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516293605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.1516293605 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.4231038753 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 29021000 ps |
| CPU time | 22.61 seconds |
| Started | Feb 09 03:49:16 AM UTC 25 |
| Finished | Feb 09 03:49:40 AM UTC 25 |
| Peak memory | 271924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231038753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.4231038753 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2917730749 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 844807900 ps |
| CPU time | 67.8 seconds |
| Started | Feb 09 03:49:29 AM UTC 25 |
| Finished | Feb 09 03:50:39 AM UTC 25 |
| Peak memory | 271928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917730749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2917730749 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3004150338 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 45962400 ps |
| CPU time | 26.42 seconds |
| Started | Feb 09 03:49:09 AM UTC 25 |
| Finished | Feb 09 03:49:37 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004150338 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3004150338 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1651803209 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 41510000 ps |
| CPU time | 30.44 seconds |
| Started | Feb 09 03:49:09 AM UTC 25 |
| Finished | Feb 09 03:49:41 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 51803209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_e rrors_with_csr_rw.1651803209 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1488522733 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 39715400 ps |
| CPU time | 20.11 seconds |
| Started | Feb 09 03:49:07 AM UTC 25 |
| Finished | Feb 09 03:49:28 AM UTC 25 |
| Peak memory | 273968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488522733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.1488522733 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3025279260 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 102348200 ps |
| CPU time | 30.98 seconds |
| Started | Feb 09 03:50:09 AM UTC 25 |
| Finished | Feb 09 03:50:41 AM UTC 25 |
| Peak memory | 284408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3025279260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3025279260 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3187690736 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 27167100 ps |
| CPU time | 33.04 seconds |
| Started | Feb 09 03:49:55 AM UTC 25 |
| Finished | Feb 09 03:50:30 AM UTC 25 |
| Peak memory | 274044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187690736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.3187690736 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2414607508 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 25474700 ps |
| CPU time | 27.95 seconds |
| Started | Feb 09 03:49:42 AM UTC 25 |
| Finished | Feb 09 03:50:11 AM UTC 25 |
| Peak memory | 271928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414607508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.2414607508 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1636032999 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 392324200 ps |
| CPU time | 31.25 seconds |
| Started | Feb 09 03:50:05 AM UTC 25 |
| Finished | Feb 09 03:50:37 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636032999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1636032999 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2894579979 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 12585700 ps |
| CPU time | 27.05 seconds |
| Started | Feb 09 03:49:41 AM UTC 25 |
| Finished | Feb 09 03:50:09 AM UTC 25 |
| Peak memory | 261512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894579979 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2894579979 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1438664424 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 41113000 ps |
| CPU time | 25.85 seconds |
| Started | Feb 09 03:49:41 AM UTC 25 |
| Finished | Feb 09 03:50:08 AM UTC 25 |
| Peak memory | 261508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14 38664424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_e rrors_with_csr_rw.1438664424 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3521211935 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 74933900 ps |
| CPU time | 31.84 seconds |
| Started | Feb 09 03:49:34 AM UTC 25 |
| Finished | Feb 09 03:50:08 AM UTC 25 |
| Peak memory | 273976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521211935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.3521211935 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1325372497 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 49019800 ps |
| CPU time | 30.46 seconds |
| Started | Feb 09 03:50:41 AM UTC 25 |
| Finished | Feb 09 03:51:12 AM UTC 25 |
| Peak memory | 284272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1325372497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1325372497 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1399900735 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 35009800 ps |
| CPU time | 31.99 seconds |
| Started | Feb 09 03:50:38 AM UTC 25 |
| Finished | Feb 09 03:51:12 AM UTC 25 |
| Peak memory | 271864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399900735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.1399900735 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3184110125 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 15258800 ps |
| CPU time | 26.16 seconds |
| Started | Feb 09 03:50:34 AM UTC 25 |
| Finished | Feb 09 03:51:02 AM UTC 25 |
| Peak memory | 271924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184110125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.3184110125 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.120588215 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 163495000 ps |
| CPU time | 23 seconds |
| Started | Feb 09 03:50:40 AM UTC 25 |
| Finished | Feb 09 03:51:04 AM UTC 25 |
| Peak memory | 273916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120588215 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.120588215 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.658234105 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 13507700 ps |
| CPU time | 25.91 seconds |
| Started | Feb 09 03:50:12 AM UTC 25 |
| Finished | Feb 09 03:50:39 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658234105 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.658234105 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4050051777 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 87046200 ps |
| CPU time | 30.95 seconds |
| Started | Feb 09 03:50:30 AM UTC 25 |
| Finished | Feb 09 03:51:03 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 50051777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_e rrors_with_csr_rw.4050051777 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3095449501 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 45852800 ps |
| CPU time | 31.42 seconds |
| Started | Feb 09 03:50:09 AM UTC 25 |
| Finished | Feb 09 03:50:42 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095449501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.3095449501 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3099637362 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 968745100 ps |
| CPU time | 1630.19 seconds |
| Started | Feb 09 03:50:10 AM UTC 25 |
| Finished | Feb 09 04:17:40 AM UTC 25 |
| Peak memory | 274112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099637362 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.3099637362 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1235812973 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 66770500 ps |
| CPU time | 34.3 seconds |
| Started | Feb 09 03:51:13 AM UTC 25 |
| Finished | Feb 09 03:51:49 AM UTC 25 |
| Peak memory | 284280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1235812973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1235812973 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.783233826 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 113701700 ps |
| CPU time | 19.9 seconds |
| Started | Feb 09 03:51:10 AM UTC 25 |
| Finished | Feb 09 03:51:31 AM UTC 25 |
| Peak memory | 273908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783233826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.783233826 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.1123389174 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 17521000 ps |
| CPU time | 22.54 seconds |
| Started | Feb 09 03:51:05 AM UTC 25 |
| Finished | Feb 09 03:51:29 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123389174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.1123389174 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.820982797 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 198705700 ps |
| CPU time | 53.31 seconds |
| Started | Feb 09 03:51:13 AM UTC 25 |
| Finished | Feb 09 03:52:08 AM UTC 25 |
| Peak memory | 273916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820982797 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.820982797 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.252895949 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 24885600 ps |
| CPU time | 19.11 seconds |
| Started | Feb 09 03:51:03 AM UTC 25 |
| Finished | Feb 09 03:51:23 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252895949 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.252895949 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.801518781 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 14510900 ps |
| CPU time | 21.62 seconds |
| Started | Feb 09 03:51:04 AM UTC 25 |
| Finished | Feb 09 03:51:27 AM UTC 25 |
| Peak memory | 261760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80 1518781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_er rors_with_csr_rw.801518781 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.690822367 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 930420600 ps |
| CPU time | 29.25 seconds |
| Started | Feb 09 03:50:42 AM UTC 25 |
| Finished | Feb 09 03:51:12 AM UTC 25 |
| Peak memory | 274164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690822367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.690822367 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.430881858 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3511122400 ps |
| CPU time | 1397.09 seconds |
| Started | Feb 09 03:50:43 AM UTC 25 |
| Finished | Feb 09 04:14:15 AM UTC 25 |
| Peak memory | 273984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430881858 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.430881858 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3742346976 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 362070600 ps |
| CPU time | 41.23 seconds |
| Started | Feb 09 03:43:45 AM UTC 25 |
| Finished | Feb 09 03:44:27 AM UTC 25 |
| Peak memory | 273916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742346976 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.3742346976 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3441962624 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2908456700 ps |
| CPU time | 63.27 seconds |
| Started | Feb 09 03:43:44 AM UTC 25 |
| Finished | Feb 09 03:44:49 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441962624 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.3441962624 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3422105805 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 31574500 ps |
| CPU time | 51.54 seconds |
| Started | Feb 09 03:43:41 AM UTC 25 |
| Finished | Feb 09 03:44:34 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422105805 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.3422105805 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2791680183 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 47005200 ps |
| CPU time | 33.03 seconds |
| Started | Feb 09 03:43:58 AM UTC 25 |
| Finished | Feb 09 03:44:32 AM UTC 25 |
| Peak memory | 284280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2791680183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2791680183 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1424545291 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 406491500 ps |
| CPU time | 25.7 seconds |
| Started | Feb 09 03:43:41 AM UTC 25 |
| Finished | Feb 09 03:44:08 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424545291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.1424545291 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.4190801762 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 29524500 ps |
| CPU time | 27.29 seconds |
| Started | Feb 09 03:43:29 AM UTC 25 |
| Finished | Feb 09 03:43:58 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190801762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.4190801762 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1417738262 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 30837800 ps |
| CPU time | 15.82 seconds |
| Started | Feb 09 03:43:39 AM UTC 25 |
| Finished | Feb 09 03:43:56 AM UTC 25 |
| Peak memory | 274044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417738262 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.1417738262 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3343484272 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 28171300 ps |
| CPU time | 22.58 seconds |
| Started | Feb 09 03:43:34 AM UTC 25 |
| Finished | Feb 09 03:43:58 AM UTC 25 |
| Peak memory | 271872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343484272 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/f lash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.3343484272 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1949923003 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 181848000 ps |
| CPU time | 33 seconds |
| Started | Feb 09 03:43:58 AM UTC 25 |
| Finished | Feb 09 03:44:32 AM UTC 25 |
| Peak memory | 273980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949923003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1949923003 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2591922682 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 27077900 ps |
| CPU time | 30.51 seconds |
| Started | Feb 09 03:43:25 AM UTC 25 |
| Finished | Feb 09 03:43:57 AM UTC 25 |
| Peak memory | 261628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591922682 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2591922682 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2370841237 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 13580700 ps |
| CPU time | 31.59 seconds |
| Started | Feb 09 03:43:26 AM UTC 25 |
| Finished | Feb 09 03:43:59 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 70841237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_er rors_with_csr_rw.2370841237 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.196404392 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 59830900 ps |
| CPU time | 26.76 seconds |
| Started | Feb 09 03:43:11 AM UTC 25 |
| Finished | Feb 09 03:43:39 AM UTC 25 |
| Peak memory | 273964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196404392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.196404392 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2990239670 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 679928800 ps |
| CPU time | 785.27 seconds |
| Started | Feb 09 03:43:20 AM UTC 25 |
| Finished | Feb 09 03:56:35 AM UTC 25 |
| Peak memory | 273976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990239670 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.2990239670 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.2577849374 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 15309300 ps |
| CPU time | 24.66 seconds |
| Started | Feb 09 03:51:13 AM UTC 25 |
| Finished | Feb 09 03:51:39 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577849374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.2577849374 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.253844367 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 52639800 ps |
| CPU time | 22.77 seconds |
| Started | Feb 09 03:51:16 AM UTC 25 |
| Finished | Feb 09 03:51:40 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253844367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.253844367 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.815277440 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 188825500 ps |
| CPU time | 24.97 seconds |
| Started | Feb 09 03:51:24 AM UTC 25 |
| Finished | Feb 09 03:51:50 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815277440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.815277440 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2537807360 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 40596400 ps |
| CPU time | 20.36 seconds |
| Started | Feb 09 03:51:28 AM UTC 25 |
| Finished | Feb 09 03:51:49 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537807360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.2537807360 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3341098313 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 27347700 ps |
| CPU time | 24.34 seconds |
| Started | Feb 09 03:51:30 AM UTC 25 |
| Finished | Feb 09 03:51:55 AM UTC 25 |
| Peak memory | 271800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341098313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.3341098313 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.713769462 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 39806000 ps |
| CPU time | 23.68 seconds |
| Started | Feb 09 03:51:32 AM UTC 25 |
| Finished | Feb 09 03:51:57 AM UTC 25 |
| Peak memory | 271988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713769462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.713769462 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2912975438 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 27456500 ps |
| CPU time | 19.18 seconds |
| Started | Feb 09 03:51:40 AM UTC 25 |
| Finished | Feb 09 03:52:00 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912975438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.2912975438 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3501483485 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 19792900 ps |
| CPU time | 22.7 seconds |
| Started | Feb 09 03:51:41 AM UTC 25 |
| Finished | Feb 09 03:52:05 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501483485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.3501483485 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.2065879019 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 30520400 ps |
| CPU time | 23.08 seconds |
| Started | Feb 09 03:51:48 AM UTC 25 |
| Finished | Feb 09 03:52:13 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065879019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.2065879019 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2089871324 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 14934500 ps |
| CPU time | 28.09 seconds |
| Started | Feb 09 03:51:48 AM UTC 25 |
| Finished | Feb 09 03:52:18 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089871324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.2089871324 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.857524621 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 448909400 ps |
| CPU time | 74.84 seconds |
| Started | Feb 09 03:44:29 AM UTC 25 |
| Finished | Feb 09 03:45:46 AM UTC 25 |
| Peak memory | 271872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857524621 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.857524621 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3121107553 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6450552200 ps |
| CPU time | 76.26 seconds |
| Started | Feb 09 03:44:27 AM UTC 25 |
| Finished | Feb 09 03:45:45 AM UTC 25 |
| Peak memory | 271996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121107553 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.3121107553 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2348121275 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 105426000 ps |
| CPU time | 44.91 seconds |
| Started | Feb 09 03:44:16 AM UTC 25 |
| Finished | Feb 09 03:45:03 AM UTC 25 |
| Peak memory | 271996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348121275 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.2348121275 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2289496508 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 23525000 ps |
| CPU time | 25.83 seconds |
| Started | Feb 09 03:44:32 AM UTC 25 |
| Finished | Feb 09 03:44:59 AM UTC 25 |
| Peak memory | 284012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2289496508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2289496508 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1066102826 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 62656700 ps |
| CPU time | 22.87 seconds |
| Started | Feb 09 03:44:18 AM UTC 25 |
| Finished | Feb 09 03:44:42 AM UTC 25 |
| Peak memory | 271932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066102826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.1066102826 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3075588198 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 16164600 ps |
| CPU time | 24.35 seconds |
| Started | Feb 09 03:44:09 AM UTC 25 |
| Finished | Feb 09 03:44:35 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075588198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3075588198 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4240909349 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 17577400 ps |
| CPU time | 15.95 seconds |
| Started | Feb 09 03:44:13 AM UTC 25 |
| Finished | Feb 09 03:44:31 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240909349 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.4240909349 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1106707952 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 52781200 ps |
| CPU time | 25.97 seconds |
| Started | Feb 09 03:44:12 AM UTC 25 |
| Finished | Feb 09 03:44:40 AM UTC 25 |
| Peak memory | 271936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106707952 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/f lash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.1106707952 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2740975650 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 65413700 ps |
| CPU time | 64.37 seconds |
| Started | Feb 09 03:44:32 AM UTC 25 |
| Finished | Feb 09 03:45:38 AM UTC 25 |
| Peak memory | 273748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740975650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2740975650 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.424520544 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 32670600 ps |
| CPU time | 25.75 seconds |
| Started | Feb 09 03:43:59 AM UTC 25 |
| Finished | Feb 09 03:44:26 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424520544 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.424520544 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.607184300 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 24999700 ps |
| CPU time | 29.36 seconds |
| Started | Feb 09 03:44:00 AM UTC 25 |
| Finished | Feb 09 03:44:31 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60 7184300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_err ors_with_csr_rw.607184300 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1913952970 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 52335500 ps |
| CPU time | 33.27 seconds |
| Started | Feb 09 03:43:58 AM UTC 25 |
| Finished | Feb 09 03:44:32 AM UTC 25 |
| Peak memory | 274036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913952970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1913952970 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1608606593 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 629658700 ps |
| CPU time | 736.53 seconds |
| Started | Feb 09 03:43:59 AM UTC 25 |
| Finished | Feb 09 03:56:24 AM UTC 25 |
| Peak memory | 273980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608606593 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.1608606593 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1583739924 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 15300200 ps |
| CPU time | 24.78 seconds |
| Started | Feb 09 03:51:50 AM UTC 25 |
| Finished | Feb 09 03:52:16 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583739924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1583739924 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.986083515 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 18139500 ps |
| CPU time | 19.1 seconds |
| Started | Feb 09 03:51:50 AM UTC 25 |
| Finished | Feb 09 03:52:11 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986083515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.986083515 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.3262808952 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 19236200 ps |
| CPU time | 20.73 seconds |
| Started | Feb 09 03:51:50 AM UTC 25 |
| Finished | Feb 09 03:52:12 AM UTC 25 |
| Peak memory | 271924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262808952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.3262808952 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2671831539 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 47610300 ps |
| CPU time | 21.56 seconds |
| Started | Feb 09 03:51:56 AM UTC 25 |
| Finished | Feb 09 03:52:19 AM UTC 25 |
| Peak memory | 271728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671831539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.2671831539 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1513843811 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 65955100 ps |
| CPU time | 21.01 seconds |
| Started | Feb 09 03:51:57 AM UTC 25 |
| Finished | Feb 09 03:52:20 AM UTC 25 |
| Peak memory | 271728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513843811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.1513843811 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.1751563650 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 36338200 ps |
| CPU time | 21.29 seconds |
| Started | Feb 09 03:52:02 AM UTC 25 |
| Finished | Feb 09 03:52:24 AM UTC 25 |
| Peak memory | 271924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751563650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.1751563650 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.3632874433 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 17580800 ps |
| CPU time | 20.79 seconds |
| Started | Feb 09 03:52:07 AM UTC 25 |
| Finished | Feb 09 03:52:29 AM UTC 25 |
| Peak memory | 271728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632874433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.3632874433 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.3751301665 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 30572200 ps |
| CPU time | 26.46 seconds |
| Started | Feb 09 03:52:07 AM UTC 25 |
| Finished | Feb 09 03:52:35 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751301665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.3751301665 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2844290030 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 14655600 ps |
| CPU time | 19.99 seconds |
| Started | Feb 09 03:52:09 AM UTC 25 |
| Finished | Feb 09 03:52:30 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844290030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.2844290030 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.353861533 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 14677300 ps |
| CPU time | 26.47 seconds |
| Started | Feb 09 03:52:11 AM UTC 25 |
| Finished | Feb 09 03:52:39 AM UTC 25 |
| Peak memory | 271732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353861533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.353861533 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3095993923 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 873882700 ps |
| CPU time | 74.95 seconds |
| Started | Feb 09 03:44:50 AM UTC 25 |
| Finished | Feb 09 03:46:07 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095993923 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.3095993923 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2485865055 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6406427400 ps |
| CPU time | 85.31 seconds |
| Started | Feb 09 03:44:47 AM UTC 25 |
| Finished | Feb 09 03:46:14 AM UTC 25 |
| Peak memory | 271996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485865055 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.2485865055 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3498566119 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 45579600 ps |
| CPU time | 73.87 seconds |
| Started | Feb 09 03:44:42 AM UTC 25 |
| Finished | Feb 09 03:45:57 AM UTC 25 |
| Peak memory | 271864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498566119 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.3498566119 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.310897054 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 158485300 ps |
| CPU time | 30.01 seconds |
| Started | Feb 09 03:44:59 AM UTC 25 |
| Finished | Feb 09 03:45:31 AM UTC 25 |
| Peak memory | 284404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=310897054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_csr_mem_rw_with_rand_reset.310897054 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.741892208 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 26854400 ps |
| CPU time | 28.89 seconds |
| Started | Feb 09 03:44:43 AM UTC 25 |
| Finished | Feb 09 03:45:13 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741892208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.741892208 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2511005751 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 55795400 ps |
| CPU time | 17.9 seconds |
| Started | Feb 09 03:44:35 AM UTC 25 |
| Finished | Feb 09 03:44:54 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511005751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2511005751 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1211645073 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 16208200 ps |
| CPU time | 26.61 seconds |
| Started | Feb 09 03:44:41 AM UTC 25 |
| Finished | Feb 09 03:45:08 AM UTC 25 |
| Peak memory | 273920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211645073 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.1211645073 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2545648531 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 28358800 ps |
| CPU time | 21.81 seconds |
| Started | Feb 09 03:44:37 AM UTC 25 |
| Finished | Feb 09 03:45:01 AM UTC 25 |
| Peak memory | 271868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545648531 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/f lash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.2545648531 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.320711462 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 901118800 ps |
| CPU time | 44.13 seconds |
| Started | Feb 09 03:44:55 AM UTC 25 |
| Finished | Feb 09 03:45:41 AM UTC 25 |
| Peak memory | 274104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320711462 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.320711462 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2095843597 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 55271400 ps |
| CPU time | 27.15 seconds |
| Started | Feb 09 03:44:33 AM UTC 25 |
| Finished | Feb 09 03:45:02 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095843597 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.2095843597 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.808038668 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 84487200 ps |
| CPU time | 22.11 seconds |
| Started | Feb 09 03:44:35 AM UTC 25 |
| Finished | Feb 09 03:44:58 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80 8038668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_err ors_with_csr_rw.808038668 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.976402337 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 62599600 ps |
| CPU time | 34.94 seconds |
| Started | Feb 09 03:44:33 AM UTC 25 |
| Finished | Feb 09 03:45:10 AM UTC 25 |
| Peak memory | 273960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976402337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.976402337 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1394596477 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 665111300 ps |
| CPU time | 1176.62 seconds |
| Started | Feb 09 03:44:33 AM UTC 25 |
| Finished | Feb 09 04:04:22 AM UTC 25 |
| Peak memory | 273984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394596477 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.1394596477 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2258762873 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 14696300 ps |
| CPU time | 24.55 seconds |
| Started | Feb 09 03:52:13 AM UTC 25 |
| Finished | Feb 09 03:52:39 AM UTC 25 |
| Peak memory | 271728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258762873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.2258762873 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1573075004 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 14808700 ps |
| CPU time | 19.71 seconds |
| Started | Feb 09 03:52:13 AM UTC 25 |
| Finished | Feb 09 03:52:34 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573075004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.1573075004 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.758179273 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 15396300 ps |
| CPU time | 19.9 seconds |
| Started | Feb 09 03:52:17 AM UTC 25 |
| Finished | Feb 09 03:52:38 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758179273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.758179273 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2111954324 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 28588900 ps |
| CPU time | 24.02 seconds |
| Started | Feb 09 03:52:18 AM UTC 25 |
| Finished | Feb 09 03:52:44 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111954324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.2111954324 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.156034059 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 29185500 ps |
| CPU time | 26.22 seconds |
| Started | Feb 09 03:52:20 AM UTC 25 |
| Finished | Feb 09 03:52:48 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156034059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.156034059 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.1209333280 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 15355500 ps |
| CPU time | 25.86 seconds |
| Started | Feb 09 03:52:21 AM UTC 25 |
| Finished | Feb 09 03:52:49 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209333280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.1209333280 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1413308827 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 23804400 ps |
| CPU time | 23.93 seconds |
| Started | Feb 09 03:52:25 AM UTC 25 |
| Finished | Feb 09 03:52:51 AM UTC 25 |
| Peak memory | 271992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413308827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.1413308827 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2479055344 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 14274000 ps |
| CPU time | 22.9 seconds |
| Started | Feb 09 03:52:29 AM UTC 25 |
| Finished | Feb 09 03:52:54 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479055344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.2479055344 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.819442650 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 53854500 ps |
| CPU time | 16.04 seconds |
| Started | Feb 09 03:52:31 AM UTC 25 |
| Finished | Feb 09 03:52:48 AM UTC 25 |
| Peak memory | 271728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819442650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.819442650 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.2826927459 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 55544000 ps |
| CPU time | 22.42 seconds |
| Started | Feb 09 03:52:35 AM UTC 25 |
| Finished | Feb 09 03:52:58 AM UTC 25 |
| Peak memory | 271928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826927459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.2826927459 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3625643594 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 160578400 ps |
| CPU time | 29.68 seconds |
| Started | Feb 09 03:45:14 AM UTC 25 |
| Finished | Feb 09 03:45:45 AM UTC 25 |
| Peak memory | 284344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3625643594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3625643594 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3689978728 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 130923100 ps |
| CPU time | 25.97 seconds |
| Started | Feb 09 03:45:09 AM UTC 25 |
| Finished | Feb 09 03:45:36 AM UTC 25 |
| Peak memory | 271932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689978728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.3689978728 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.428165121 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 613061200 ps |
| CPU time | 65.34 seconds |
| Started | Feb 09 03:45:10 AM UTC 25 |
| Finished | Feb 09 03:46:17 AM UTC 25 |
| Peak memory | 273976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428165121 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.428165121 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.427007304 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 35667600 ps |
| CPU time | 25.78 seconds |
| Started | Feb 09 03:45:01 AM UTC 25 |
| Finished | Feb 09 03:45:28 AM UTC 25 |
| Peak memory | 261688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427007304 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.427007304 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2852990906 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 12418700 ps |
| CPU time | 28.07 seconds |
| Started | Feb 09 03:45:02 AM UTC 25 |
| Finished | Feb 09 03:45:31 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28 52990906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_er rors_with_csr_rw.2852990906 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2879607710 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 57086500 ps |
| CPU time | 35.2 seconds |
| Started | Feb 09 03:45:01 AM UTC 25 |
| Finished | Feb 09 03:45:38 AM UTC 25 |
| Peak memory | 273964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879607710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2879607710 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1410409519 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 721826800 ps |
| CPU time | 621.32 seconds |
| Started | Feb 09 03:45:01 AM UTC 25 |
| Finished | Feb 09 03:55:29 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410409519 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.1410409519 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3132625380 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 157699100 ps |
| CPU time | 34.75 seconds |
| Started | Feb 09 03:45:42 AM UTC 25 |
| Finished | Feb 09 03:46:18 AM UTC 25 |
| Peak memory | 284280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3132625380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3132625380 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3690355978 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 58877700 ps |
| CPU time | 23.53 seconds |
| Started | Feb 09 03:45:39 AM UTC 25 |
| Finished | Feb 09 03:46:04 AM UTC 25 |
| Peak memory | 274108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690355978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.3690355978 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2904060593 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 16358100 ps |
| CPU time | 23.2 seconds |
| Started | Feb 09 03:45:38 AM UTC 25 |
| Finished | Feb 09 03:46:02 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904060593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2904060593 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1933506380 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 202274000 ps |
| CPU time | 54.29 seconds |
| Started | Feb 09 03:45:39 AM UTC 25 |
| Finished | Feb 09 03:46:35 AM UTC 25 |
| Peak memory | 273916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933506380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1933506380 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.67295030 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 46399500 ps |
| CPU time | 21.43 seconds |
| Started | Feb 09 03:45:32 AM UTC 25 |
| Finished | Feb 09 03:45:55 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67295030 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.67295030 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1139549533 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 16855400 ps |
| CPU time | 28.68 seconds |
| Started | Feb 09 03:45:34 AM UTC 25 |
| Finished | Feb 09 03:46:04 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 39549533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_er rors_with_csr_rw.1139549533 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.427572070 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 687127900 ps |
| CPU time | 602.22 seconds |
| Started | Feb 09 03:45:31 AM UTC 25 |
| Finished | Feb 09 03:55:40 AM UTC 25 |
| Peak memory | 273980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427572070 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.427572070 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3424213181 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 101294100 ps |
| CPU time | 35.14 seconds |
| Started | Feb 09 03:46:04 AM UTC 25 |
| Finished | Feb 09 03:46:41 AM UTC 25 |
| Peak memory | 288376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3424213181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3424213181 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1662794092 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 128108900 ps |
| CPU time | 28.33 seconds |
| Started | Feb 09 03:46:03 AM UTC 25 |
| Finished | Feb 09 03:46:33 AM UTC 25 |
| Peak memory | 273916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662794092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.1662794092 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2444425682 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 51313800 ps |
| CPU time | 19 seconds |
| Started | Feb 09 03:45:58 AM UTC 25 |
| Finished | Feb 09 03:46:18 AM UTC 25 |
| Peak memory | 271796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444425682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2444425682 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1393672133 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 333152400 ps |
| CPU time | 32.58 seconds |
| Started | Feb 09 03:46:04 AM UTC 25 |
| Finished | Feb 09 03:46:38 AM UTC 25 |
| Peak memory | 271996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393672133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1393672133 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2443331738 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 62766100 ps |
| CPU time | 27.95 seconds |
| Started | Feb 09 03:45:47 AM UTC 25 |
| Finished | Feb 09 03:46:16 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443331738 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2443331738 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.264781558 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 23066800 ps |
| CPU time | 30.15 seconds |
| Started | Feb 09 03:45:56 AM UTC 25 |
| Finished | Feb 09 03:46:28 AM UTC 25 |
| Peak memory | 261556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 4781558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_err ors_with_csr_rw.264781558 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1515641207 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 54839200 ps |
| CPU time | 25.99 seconds |
| Started | Feb 09 03:45:46 AM UTC 25 |
| Finished | Feb 09 03:46:13 AM UTC 25 |
| Peak memory | 273972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515641207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1515641207 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.648653373 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 355078800 ps |
| CPU time | 584.3 seconds |
| Started | Feb 09 03:45:46 AM UTC 25 |
| Finished | Feb 09 03:55:37 AM UTC 25 |
| Peak memory | 273976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648653373 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.648653373 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3444753937 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 228929100 ps |
| CPU time | 37.89 seconds |
| Started | Feb 09 03:46:19 AM UTC 25 |
| Finished | Feb 09 03:46:58 AM UTC 25 |
| Peak memory | 284408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3444753937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3444753937 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.665385032 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 77421200 ps |
| CPU time | 31.91 seconds |
| Started | Feb 09 03:46:18 AM UTC 25 |
| Finished | Feb 09 03:46:51 AM UTC 25 |
| Peak memory | 271860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665385032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.665385032 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.4088405037 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 18320400 ps |
| CPU time | 23.42 seconds |
| Started | Feb 09 03:46:17 AM UTC 25 |
| Finished | Feb 09 03:46:42 AM UTC 25 |
| Peak memory | 271988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088405037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.4088405037 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1048052102 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 98250000 ps |
| CPU time | 28.4 seconds |
| Started | Feb 09 03:46:19 AM UTC 25 |
| Finished | Feb 09 03:46:49 AM UTC 25 |
| Peak memory | 273908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048052102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.1048052102 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3161100911 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 170728000 ps |
| CPU time | 26.85 seconds |
| Started | Feb 09 03:46:15 AM UTC 25 |
| Finished | Feb 09 03:46:43 AM UTC 25 |
| Peak memory | 261692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161100911 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3161100911 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1512905700 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 16234200 ps |
| CPU time | 19.62 seconds |
| Started | Feb 09 03:46:15 AM UTC 25 |
| Finished | Feb 09 03:46:36 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 12905700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_er rors_with_csr_rw.1512905700 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3115068288 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 673692900 ps |
| CPU time | 605.41 seconds |
| Started | Feb 09 03:46:07 AM UTC 25 |
| Finished | Feb 09 03:56:20 AM UTC 25 |
| Peak memory | 273984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115068288 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.3115068288 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.911763603 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 190421800 ps |
| CPU time | 28.65 seconds |
| Started | Feb 09 03:46:42 AM UTC 25 |
| Finished | Feb 09 03:47:12 AM UTC 25 |
| Peak memory | 284404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mo de=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=911763603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9 .flash_ctrl_csr_mem_rw_with_rand_reset.911763603 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4248001956 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 93357200 ps |
| CPU time | 31.53 seconds |
| Started | Feb 09 03:46:37 AM UTC 25 |
| Finished | Feb 09 03:47:11 AM UTC 25 |
| Peak memory | 273912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248001956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.4248001956 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1286963961 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 16233000 ps |
| CPU time | 24.66 seconds |
| Started | Feb 09 03:46:36 AM UTC 25 |
| Finished | Feb 09 03:47:02 AM UTC 25 |
| Peak memory | 271792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286963961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1286963961 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1295851945 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 227908300 ps |
| CPU time | 35.84 seconds |
| Started | Feb 09 03:46:39 AM UTC 25 |
| Finished | Feb 09 03:47:17 AM UTC 25 |
| Peak memory | 271996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295851945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.1295851945 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2847006682 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 20797700 ps |
| CPU time | 20.61 seconds |
| Started | Feb 09 03:46:34 AM UTC 25 |
| Finished | Feb 09 03:46:56 AM UTC 25 |
| Peak memory | 261564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847006682 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2847006682 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3124486073 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 40308800 ps |
| CPU time | 29.08 seconds |
| Started | Feb 09 03:46:36 AM UTC 25 |
| Finished | Feb 09 03:47:06 AM UTC 25 |
| Peak memory | 261560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 24486073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_er rors_with_csr_rw.3124486073 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.873630896 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 92239300 ps |
| CPU time | 32.42 seconds |
| Started | Feb 09 03:46:28 AM UTC 25 |
| Finished | Feb 09 03:47:01 AM UTC 25 |
| Peak memory | 274100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873630896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.873630896 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2324803008 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 241772900 ps |
| CPU time | 665.36 seconds |
| Started | Feb 09 03:46:29 AM UTC 25 |
| Finished | Feb 09 03:57:42 AM UTC 25 |
| Peak memory | 273984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324803008 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.2324803008 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.3212216522 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 81712100 ps |
| CPU time | 18.43 seconds |
| Started | Feb 09 05:03:31 AM UTC 25 |
| Finished | Feb 09 05:03:51 AM UTC 25 |
| Peak memory | 275224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212216522 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3212216522 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.688095893 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1244587800 ps |
| CPU time | 215.91 seconds |
| Started | Feb 09 04:59:58 AM UTC 25 |
| Finished | Feb 09 05:03:37 AM UTC 25 |
| Peak memory | 287624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 + otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=688095893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_d err_detect.688095893 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.295145587 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 305559000 ps |
| CPU time | 51.33 seconds |
| Started | Feb 09 05:02:54 AM UTC 25 |
| Finished | Feb 09 05:03:47 AM UTC 25 |
| Peak memory | 275456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295145587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fs_sup.295145587 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1596039472 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 27930500 ps |
| CPU time | 35.31 seconds |
| Started | Feb 09 05:03:29 AM UTC 25 |
| Finished | Feb 09 05:04:06 AM UTC 25 |
| Peak memory | 277332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596039472 -assert n opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_addr_infection.1596039472 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.1311364145 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 38763000 ps |
| CPU time | 45.16 seconds |
| Started | Feb 09 04:58:24 AM UTC 25 |
| Finished | Feb 09 04:59:11 AM UTC 25 |
| Peak memory | 275420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311364145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1311364145 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.463032662 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 38519200 ps |
| CPU time | 22.36 seconds |
| Started | Feb 09 05:03:22 AM UTC 25 |
| Finished | Feb 09 05:03:46 AM UTC 25 |
| Peak memory | 269152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46 3032662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_se ed_err.463032662 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.4270482365 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 83818420400 ps |
| CPU time | 1927.11 seconds |
| Started | Feb 09 04:58:29 AM UTC 25 |
| Finished | Feb 09 05:30:57 AM UTC 25 |
| Peak memory | 271172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270482365 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.4270482365 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.2811725260 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 120167610000 ps |
| CPU time | 980.85 seconds |
| Started | Feb 09 04:58:30 AM UTC 25 |
| Finished | Feb 09 05:15:02 AM UTC 25 |
| Peak memory | 275008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811725260 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.2811725260 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1948855663 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5934575200 ps |
| CPU time | 177.75 seconds |
| Started | Feb 09 05:00:34 AM UTC 25 |
| Finished | Feb 09 05:03:35 AM UTC 25 |
| Peak memory | 303868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1948855663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_int r_rd_slow_flash.1948855663 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.105506076 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5174169900 ps |
| CPU time | 93.96 seconds |
| Started | Feb 09 05:00:27 AM UTC 25 |
| Finished | Feb 09 05:02:03 AM UTC 25 |
| Peak memory | 275248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105506076 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.105506076 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.1812311203 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1368248300 ps |
| CPU time | 216.2 seconds |
| Started | Feb 09 05:00:12 AM UTC 25 |
| Finished | Feb 09 05:03:51 AM UTC 25 |
| Peak memory | 291740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_ pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1812311203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.f lash_ctrl_oversize_error.1812311203 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.3628986263 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5794470300 ps |
| CPU time | 689.66 seconds |
| Started | Feb 09 04:58:26 AM UTC 25 |
| Finished | Feb 09 05:10:04 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628986263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3628986263 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.1068561708 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 45004600 ps |
| CPU time | 28.64 seconds |
| Started | Feb 09 05:03:05 AM UTC 25 |
| Finished | Feb 09 05:03:35 AM UTC 25 |
| Peak memory | 273380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1068561708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1068561708 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1430276058 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 21237200 ps |
| CPU time | 20.96 seconds |
| Started | Feb 09 05:00:51 AM UTC 25 |
| Finished | Feb 09 05:01:14 AM UTC 25 |
| Peak memory | 271384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430276058 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.1430276058 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4251082768 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 85972700 ps |
| CPU time | 1053.04 seconds |
| Started | Feb 09 04:58:23 AM UTC 25 |
| Finished | Feb 09 05:16:08 AM UTC 25 |
| Peak memory | 291548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251082768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.4251082768 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.563058148 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 210208600 ps |
| CPU time | 125.84 seconds |
| Started | Feb 09 04:58:25 AM UTC 25 |
| Finished | Feb 09 05:00:34 AM UTC 25 |
| Peak memory | 273172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563058148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.563058148 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3360249938 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 255432500 ps |
| CPU time | 43.58 seconds |
| Started | Feb 09 05:02:32 AM UTC 25 |
| Finished | Feb 09 05:03:17 AM UTC 25 |
| Peak memory | 285560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360249938 -assert n opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.3360249938 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.542229841 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 38105700 ps |
| CPU time | 73.41 seconds |
| Started | Feb 09 05:03:26 AM UTC 25 |
| Finished | Feb 09 05:04:41 AM UTC 25 |
| Peak memory | 285592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542229841 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.542229841 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1156626716 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 22555000 ps |
| CPU time | 21.83 seconds |
| Started | Feb 09 04:59:03 AM UTC 25 |
| Finished | Feb 09 04:59:26 AM UTC 25 |
| Peak memory | 269040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156626716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.1156626716 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.612477720 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 58866200 ps |
| CPU time | 38.2 seconds |
| Started | Feb 09 04:59:31 AM UTC 25 |
| Finished | Feb 09 05:00:11 AM UTC 25 |
| Peak memory | 275300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6124777 20 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_ derr.612477720 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.3534029997 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 43178400 ps |
| CPU time | 39.87 seconds |
| Started | Feb 09 04:59:12 AM UTC 25 |
| Finished | Feb 09 04:59:53 AM UTC 25 |
| Peak memory | 275268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534029997 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.3534029997 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.206583067 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 41107754800 ps |
| CPU time | 983.37 seconds |
| Started | Feb 09 05:03:11 AM UTC 25 |
| Finished | Feb 09 05:19:45 AM UTC 25 |
| Peak memory | 273016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_0 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=206583067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.206583067 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.2770799740 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 657218800 ps |
| CPU time | 189.36 seconds |
| Started | Feb 09 04:59:41 AM UTC 25 |
| Finished | Feb 09 05:02:54 AM UTC 25 |
| Peak memory | 291708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2770799740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_ro_derr.2770799740 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.896363876 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 30142800 ps |
| CPU time | 53.36 seconds |
| Started | Feb 09 05:01:15 AM UTC 25 |
| Finished | Feb 09 05:02:10 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896363876 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.896363876 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.46213295 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2352644500 ps |
| CPU time | 6750.41 seconds |
| Started | Feb 09 05:02:11 AM UTC 25 |
| Finished | Feb 09 06:55:50 AM UTC 25 |
| Peak memory | 314240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46213295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ba se_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.46213295 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2750116409 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1120594100 ps |
| CPU time | 57.34 seconds |
| Started | Feb 09 04:59:27 AM UTC 25 |
| Finished | Feb 09 05:00:26 AM UTC 25 |
| Peak memory | 275340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750116409 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_serr_address.2750116409 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2069487482 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2041745100 ps |
| CPU time | 89.73 seconds |
| Started | Feb 09 04:59:19 AM UTC 25 |
| Finished | Feb 09 05:00:51 AM UTC 25 |
| Peak memory | 285832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069487482 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_serr_counter.2069487482 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.3205388871 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 26589200 ps |
| CPU time | 66.54 seconds |
| Started | Feb 09 04:58:22 AM UTC 25 |
| Finished | Feb 09 04:59:30 AM UTC 25 |
| Peak memory | 285340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205388871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3205388871 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3134217287 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 47210600 ps |
| CPU time | 32.36 seconds |
| Started | Feb 09 04:58:23 AM UTC 25 |
| Finished | Feb 09 04:58:57 AM UTC 25 |
| Peak memory | 271144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134217287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3134217287 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1583589391 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2079074300 ps |
| CPU time | 1688.93 seconds |
| Started | Feb 09 05:02:23 AM UTC 25 |
| Finished | Feb 09 05:30:49 AM UTC 25 |
| Peak memory | 301996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583589391 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.1583589391 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.3418674565 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 37308700 ps |
| CPU time | 33.1 seconds |
| Started | Feb 09 04:58:24 AM UTC 25 |
| Finished | Feb 09 04:58:59 AM UTC 25 |
| Peak memory | 270884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418674565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.3418674565 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.1365748793 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7351289000 ps |
| CPU time | 161.05 seconds |
| Started | Feb 09 04:58:58 AM UTC 25 |
| Finished | Feb 09 05:01:42 AM UTC 25 |
| Peak memory | 271380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365748793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.1365748793 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.451468289 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 46794100 ps |
| CPU time | 30.4 seconds |
| Started | Feb 09 05:02:33 AM UTC 25 |
| Finished | Feb 09 05:03:05 AM UTC 25 |
| Peak memory | 271216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_r d_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=451468289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.451468289 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.1722129859 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 151747000 ps |
| CPU time | 17.85 seconds |
| Started | Feb 09 04:58:59 AM UTC 25 |
| Finished | Feb 09 04:59:18 AM UTC 25 |
| Peak memory | 269204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722129859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.1722129859 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1754195998 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 42965700 ps |
| CPU time | 28.18 seconds |
| Started | Feb 09 05:09:58 AM UTC 25 |
| Finished | Feb 09 05:10:28 AM UTC 25 |
| Peak memory | 275420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1754195998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1754195998 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.3418108381 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 34053700 ps |
| CPU time | 27.01 seconds |
| Started | Feb 09 05:10:38 AM UTC 25 |
| Finished | Feb 09 05:11:07 AM UTC 25 |
| Peak memory | 269324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418108381 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3418108381 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3156590548 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 39275300 ps |
| CPU time | 25.75 seconds |
| Started | Feb 09 05:10:30 AM UTC 25 |
| Finished | Feb 09 05:10:57 AM UTC 25 |
| Peak memory | 273144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156590548 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.3156590548 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.739886053 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 16863600 ps |
| CPU time | 15.86 seconds |
| Started | Feb 09 05:09:37 AM UTC 25 |
| Finished | Feb 09 05:09:55 AM UTC 25 |
| Peak memory | 295100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739886053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.739886053 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.1859435365 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 790725600 ps |
| CPU time | 328.54 seconds |
| Started | Feb 09 05:07:28 AM UTC 25 |
| Finished | Feb 09 05:13:02 AM UTC 25 |
| Peak memory | 289668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 + otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1859435365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ derr_detect.1859435365 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.858519813 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 18507600 ps |
| CPU time | 36.87 seconds |
| Started | Feb 09 05:08:56 AM UTC 25 |
| Finished | Feb 09 05:09:34 AM UTC 25 |
| Peak memory | 285704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85 8519813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.858519813 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3538824088 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 771008700 ps |
| CPU time | 436.98 seconds |
| Started | Feb 09 05:03:52 AM UTC 25 |
| Finished | Feb 09 05:11:15 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538824088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3538824088 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.2945776420 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 11056858300 ps |
| CPU time | 3161.96 seconds |
| Started | Feb 09 05:05:01 AM UTC 25 |
| Finished | Feb 09 05:58:15 AM UTC 25 |
| Peak memory | 273168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945776420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2945776420 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.3146860809 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 852440500 ps |
| CPU time | 3138.02 seconds |
| Started | Feb 09 05:04:55 AM UTC 25 |
| Finished | Feb 09 05:57:47 AM UTC 25 |
| Peak memory | 273184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146860809 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3146860809 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2580895442 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 957572300 ps |
| CPU time | 1451.56 seconds |
| Started | Feb 09 05:05:00 AM UTC 25 |
| Finished | Feb 09 05:29:27 AM UTC 25 |
| Peak memory | 283364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580895442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2580895442 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.3019636904 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 845656800 ps |
| CPU time | 44.2 seconds |
| Started | Feb 09 05:04:31 AM UTC 25 |
| Finished | Feb 09 05:05:17 AM UTC 25 |
| Peak memory | 273380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019636904 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.3019636904 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2078249321 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 4631732700 ps |
| CPU time | 60.31 seconds |
| Started | Feb 09 05:10:03 AM UTC 25 |
| Finished | Feb 09 05:11:05 AM UTC 25 |
| Peak memory | 275240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078249321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fs_sup.2078249321 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.1353682367 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 62607132100 ps |
| CPU time | 3367.67 seconds |
| Started | Feb 09 05:04:42 AM UTC 25 |
| Finished | Feb 09 06:01:25 AM UTC 25 |
| Peak memory | 275020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353682367 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.1353682367 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.837820594 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 28404500 ps |
| CPU time | 42.19 seconds |
| Started | Feb 09 05:10:36 AM UTC 25 |
| Finished | Feb 09 05:11:20 AM UTC 25 |
| Peak memory | 285460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837820594 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_addr_infection.837820594 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.3708412298 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 251941635900 ps |
| CPU time | 2945.3 seconds |
| Started | Feb 09 05:04:07 AM UTC 25 |
| Finished | Feb 09 05:53:42 AM UTC 25 |
| Peak memory | 275236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708412298 -assert nopostproc +U VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.3708412298 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.2249411640 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 48228800 ps |
| CPU time | 136.42 seconds |
| Started | Feb 09 05:03:40 AM UTC 25 |
| Finished | Feb 09 05:05:59 AM UTC 25 |
| Peak memory | 273116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249411640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2249411640 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1221105412 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 10055748500 ps |
| CPU time | 61.39 seconds |
| Started | Feb 09 05:10:33 AM UTC 25 |
| Finished | Feb 09 05:11:36 AM UTC 25 |
| Peak memory | 287604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1221105412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_prog_rma_wipe_err.1221105412 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.3838490208 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 169178589300 ps |
| CPU time | 2029.55 seconds |
| Started | Feb 09 05:03:52 AM UTC 25 |
| Finished | Feb 09 05:38:03 AM UTC 25 |
| Peak memory | 270916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838490208 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.3838490208 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2661910552 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4105180800 ps |
| CPU time | 112.43 seconds |
| Started | Feb 09 05:03:48 AM UTC 25 |
| Finished | Feb 09 05:05:43 AM UTC 25 |
| Peak memory | 272996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661910552 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.2661910552 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.673582538 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3922406900 ps |
| CPU time | 501.79 seconds |
| Started | Feb 09 05:07:41 AM UTC 25 |
| Finished | Feb 09 05:16:09 AM UTC 25 |
| Peak memory | 336796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6735825 38 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integrity.673582538 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.896727593 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 540501600 ps |
| CPU time | 172.07 seconds |
| Started | Feb 09 05:07:48 AM UTC 25 |
| Finished | Feb 09 05:10:43 AM UTC 25 |
| Peak memory | 306060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896727593 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.896727593 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.214575666 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12774863400 ps |
| CPU time | 453.6 seconds |
| Started | Feb 09 05:08:05 AM UTC 25 |
| Finished | Feb 09 05:15:44 AM UTC 25 |
| Peak memory | 301824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=214575666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr _rd_slow_flash.214575666 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1933746126 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6685355600 ps |
| CPU time | 82.75 seconds |
| Started | Feb 09 05:08:03 AM UTC 25 |
| Finished | Feb 09 05:09:28 AM UTC 25 |
| Peak memory | 275476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933746126 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.1933746126 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4293083601 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 40703145300 ps |
| CPU time | 276.95 seconds |
| Started | Feb 09 05:08:08 AM UTC 25 |
| Finished | Feb 09 05:12:49 AM UTC 25 |
| Peak memory | 271100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=4293083601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_intr_wr_slow_flash.4293083601 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.1033934781 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3071558400 ps |
| CPU time | 89.87 seconds |
| Started | Feb 09 05:05:18 AM UTC 25 |
| Finished | Feb 09 05:06:50 AM UTC 25 |
| Peak memory | 273308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033934781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1033934781 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2968131070 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4539832700 ps |
| CPU time | 175.5 seconds |
| Started | Feb 09 05:07:34 AM UTC 25 |
| Finished | Feb 09 05:10:32 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_ pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2968131070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.f lash_ctrl_oversize_error.2968131070 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2336293589 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 157745500 ps |
| CPU time | 102.34 seconds |
| Started | Feb 09 05:03:47 AM UTC 25 |
| Finished | Feb 09 05:05:31 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336293589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2336293589 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2540963936 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1015889900 ps |
| CPU time | 30.92 seconds |
| Started | Feb 09 05:10:05 AM UTC 25 |
| Finished | Feb 09 05:10:37 AM UTC 25 |
| Peak memory | 275412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2540963936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_phy_arb_redun.2540963936 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3076802318 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 15424000 ps |
| CPU time | 19.44 seconds |
| Started | Feb 09 05:10:24 AM UTC 25 |
| Finished | Feb 09 05:10:44 AM UTC 25 |
| Peak memory | 273436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3076802318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3076802318 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.2892493916 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 98637000 ps |
| CPU time | 26.42 seconds |
| Started | Feb 09 05:08:24 AM UTC 25 |
| Finished | Feb 09 05:08:52 AM UTC 25 |
| Peak memory | 275416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892493916 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.2892493916 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.4112486089 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 842785800 ps |
| CPU time | 1125.33 seconds |
| Started | Feb 09 05:03:38 AM UTC 25 |
| Finished | Feb 09 05:22:36 AM UTC 25 |
| Peak memory | 295900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112486089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.4112486089 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.4158742172 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1409190200 ps |
| CPU time | 210.26 seconds |
| Started | Feb 09 05:03:41 AM UTC 25 |
| Finished | Feb 09 05:07:14 AM UTC 25 |
| Peak memory | 273436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158742172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.4158742172 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.3347846680 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 64808300 ps |
| CPU time | 40.11 seconds |
| Started | Feb 09 05:09:53 AM UTC 25 |
| Finished | Feb 09 05:10:35 AM UTC 25 |
| Peak memory | 287568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347846680 -assert n opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.3347846680 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.3805200604 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 191718100 ps |
| CPU time | 62.99 seconds |
| Started | Feb 09 05:08:53 AM UTC 25 |
| Finished | Feb 09 05:09:58 AM UTC 25 |
| Peak memory | 287644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805200604 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.3805200604 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.2178485136 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 59890200 ps |
| CPU time | 30.48 seconds |
| Started | Feb 09 05:07:15 AM UTC 25 |
| Finished | Feb 09 05:07:46 AM UTC 25 |
| Peak memory | 275588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178485 136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep _derr.2178485136 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.1776662335 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 48979900 ps |
| CPU time | 44.84 seconds |
| Started | Feb 09 05:06:41 AM UTC 25 |
| Finished | Feb 09 05:07:27 AM UTC 25 |
| Peak memory | 275268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776662335 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.1776662335 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.1660313271 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 498211200 ps |
| CPU time | 113.95 seconds |
| Started | Feb 09 05:05:44 AM UTC 25 |
| Finished | Feb 09 05:07:40 AM UTC 25 |
| Peak memory | 291700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660313 271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.1660313271 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.2950595697 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2464723000 ps |
| CPU time | 185.01 seconds |
| Started | Feb 09 05:07:22 AM UTC 25 |
| Finished | Feb 09 05:10:31 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2950595697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_ro_derr.2950595697 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.2437675791 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1268100300 ps |
| CPU time | 178.12 seconds |
| Started | Feb 09 05:06:51 AM UTC 25 |
| Finished | Feb 09 05:09:53 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2437675791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2437675791 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.2239586241 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 15734353900 ps |
| CPU time | 556.87 seconds |
| Started | Feb 09 05:06:00 AM UTC 25 |
| Finished | Feb 09 05:15:23 AM UTC 25 |
| Peak memory | 320364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239586241 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.2239586241 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.3606952474 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2813593900 ps |
| CPU time | 182.26 seconds |
| Started | Feb 09 05:07:27 AM UTC 25 |
| Finished | Feb 09 05:10:32 AM UTC 25 |
| Peak memory | 295840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3606952474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ ctrl_rw_derr.3606952474 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2671111330 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 77331800 ps |
| CPU time | 57.35 seconds |
| Started | Feb 09 05:08:26 AM UTC 25 |
| Finished | Feb 09 05:09:25 AM UTC 25 |
| Peak memory | 287676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671111330 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.2671111330 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2414963001 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 70380500 ps |
| CPU time | 60.59 seconds |
| Started | Feb 09 05:08:34 AM UTC 25 |
| Finished | Feb 09 05:09:36 AM UTC 25 |
| Peak memory | 281492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414 963001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2414963001 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1222649158 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1306274000 ps |
| CPU time | 225.42 seconds |
| Started | Feb 09 05:06:55 AM UTC 25 |
| Finished | Feb 09 05:10:44 AM UTC 25 |
| Peak memory | 291748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122264915 8 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.1222649158 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.314910774 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1338164300 ps |
| CPU time | 5953.12 seconds |
| Started | Feb 09 05:09:26 AM UTC 25 |
| Finished | Feb 09 06:49:38 AM UTC 25 |
| Peak memory | 314248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314910774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.314910774 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.3230873727 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1024361300 ps |
| CPU time | 105.73 seconds |
| Started | Feb 09 05:07:08 AM UTC 25 |
| Finished | Feb 09 05:08:55 AM UTC 25 |
| Peak memory | 285712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230873727 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_serr_address.3230873727 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3327469861 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 497831600 ps |
| CPU time | 86.16 seconds |
| Started | Feb 09 05:07:05 AM UTC 25 |
| Finished | Feb 09 05:08:33 AM UTC 25 |
| Peak memory | 287648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327469861 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_serr_counter.3327469861 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1596763234 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 336367300 ps |
| CPU time | 234.01 seconds |
| Started | Feb 09 05:03:35 AM UTC 25 |
| Finished | Feb 09 05:07:33 AM UTC 25 |
| Peak memory | 289488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596763234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1596763234 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.2667657673 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 16566000 ps |
| CPU time | 35.42 seconds |
| Started | Feb 09 05:03:36 AM UTC 25 |
| Finished | Feb 09 05:04:13 AM UTC 25 |
| Peak memory | 271208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667657673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2667657673 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.1349853457 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 143761000 ps |
| CPU time | 55.39 seconds |
| Started | Feb 09 05:09:35 AM UTC 25 |
| Finished | Feb 09 05:10:32 AM UTC 25 |
| Peak memory | 271148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349853457 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.1349853457 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3748050342 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 112543300 ps |
| CPU time | 49.54 seconds |
| Started | Feb 09 05:03:38 AM UTC 25 |
| Finished | Feb 09 05:04:30 AM UTC 25 |
| Peak memory | 272932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748050342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3748050342 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.3521190893 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 16625817600 ps |
| CPU time | 264.94 seconds |
| Started | Feb 09 05:05:33 AM UTC 25 |
| Finished | Feb 09 05:10:02 AM UTC 25 |
| Peak memory | 271148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521190893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.3521190893 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.1659292679 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 31439500 ps |
| CPU time | 17.67 seconds |
| Started | Feb 09 05:51:59 AM UTC 25 |
| Finished | Feb 09 05:52:18 AM UTC 25 |
| Peak memory | 269080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659292679 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.1659292679 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.4205791303 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 13817700 ps |
| CPU time | 27.16 seconds |
| Started | Feb 09 05:51:36 AM UTC 25 |
| Finished | Feb 09 05:52:04 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205791303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.4205791303 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.963158411 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 10012191400 ps |
| CPU time | 182.05 seconds |
| Started | Feb 09 05:51:58 AM UTC 25 |
| Finished | Feb 09 05:55:03 AM UTC 25 |
| Peak memory | 394316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=963158411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_hw_prog_rma_wipe_err.963158411 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.203619237 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 15497200 ps |
| CPU time | 24.94 seconds |
| Started | Feb 09 05:51:51 AM UTC 25 |
| Finished | Feb 09 05:52:17 AM UTC 25 |
| Peak memory | 269300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 3619237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_s eed_err.203619237 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3754549284 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1375353300 ps |
| CPU time | 76.76 seconds |
| Started | Feb 09 05:49:50 AM UTC 25 |
| Finished | Feb 09 05:51:09 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754549284 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.3754549284 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4153713364 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 163418704700 ps |
| CPU time | 417.18 seconds |
| Started | Feb 09 05:50:45 AM UTC 25 |
| Finished | Feb 09 05:57:47 AM UTC 25 |
| Peak memory | 301824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4153713364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_in tr_rd_slow_flash.4153713364 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1079915156 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1594285500 ps |
| CPU time | 87.37 seconds |
| Started | Feb 09 05:50:02 AM UTC 25 |
| Finished | Feb 09 05:51:32 AM UTC 25 |
| Peak memory | 271256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079915156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1079915156 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.13114609 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 45244700 ps |
| CPU time | 24.03 seconds |
| Started | Feb 09 05:51:44 AM UTC 25 |
| Finished | Feb 09 05:52:09 AM UTC 25 |
| Peak memory | 275320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 114609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.13114609 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2038954325 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 9241330600 ps |
| CPU time | 166.15 seconds |
| Started | Feb 09 05:50:01 AM UTC 25 |
| Finished | Feb 09 05:52:50 AM UTC 25 |
| Peak memory | 275228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2038954325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. flash_ctrl_mp_regions.2038954325 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.1008186482 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 162295100 ps |
| CPU time | 172.92 seconds |
| Started | Feb 09 05:49:55 AM UTC 25 |
| Finished | Feb 09 05:52:51 AM UTC 25 |
| Peak memory | 271508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008186482 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.1008186482 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.1228175857 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 144359400 ps |
| CPU time | 471.56 seconds |
| Started | Feb 09 05:49:48 AM UTC 25 |
| Finished | Feb 09 05:57:45 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228175857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.1228175857 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.528083027 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 10045235300 ps |
| CPU time | 234.11 seconds |
| Started | Feb 09 05:50:51 AM UTC 25 |
| Finished | Feb 09 05:54:48 AM UTC 25 |
| Peak memory | 275552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528083027 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.528083027 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2617149772 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 913276600 ps |
| CPU time | 1265.12 seconds |
| Started | Feb 09 05:49:42 AM UTC 25 |
| Finished | Feb 09 06:11:00 AM UTC 25 |
| Peak memory | 295644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617149772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2617149772 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2583150431 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 199093900 ps |
| CPU time | 57.99 seconds |
| Started | Feb 09 05:51:30 AM UTC 25 |
| Finished | Feb 09 05:52:30 AM UTC 25 |
| Peak memory | 287668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583150431 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.2583150431 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2211717690 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 488774500 ps |
| CPU time | 94.5 seconds |
| Started | Feb 09 05:50:20 AM UTC 25 |
| Finished | Feb 09 05:51:57 AM UTC 25 |
| Peak memory | 291872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211717 690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.2211717690 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3693222420 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 46595100 ps |
| CPU time | 46.14 seconds |
| Started | Feb 09 05:51:10 AM UTC 25 |
| Finished | Feb 09 05:51:58 AM UTC 25 |
| Peak memory | 287964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693222420 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.3693222420 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3855137582 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 55800600 ps |
| CPU time | 35.04 seconds |
| Started | Feb 09 05:51:26 AM UTC 25 |
| Finished | Feb 09 05:52:03 AM UTC 25 |
| Peak memory | 285596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855 137582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3855137582 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.3401847720 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4695851200 ps |
| CPU time | 63.98 seconds |
| Started | Feb 09 05:51:33 AM UTC 25 |
| Finished | Feb 09 05:52:38 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401847720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3401847720 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.4056406965 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 58901200 ps |
| CPU time | 239.07 seconds |
| Started | Feb 09 05:49:39 AM UTC 25 |
| Finished | Feb 09 05:53:41 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056406965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.4056406965 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.560810825 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 9344873000 ps |
| CPU time | 176.21 seconds |
| Started | Feb 09 05:50:18 AM UTC 25 |
| Finished | Feb 09 05:53:18 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560810825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.560810825 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1133629155 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 83264900 ps |
| CPU time | 24.98 seconds |
| Started | Feb 09 05:54:49 AM UTC 25 |
| Finished | Feb 09 05:55:15 AM UTC 25 |
| Peak memory | 269324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133629155 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1133629155 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.135778917 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 21653200 ps |
| CPU time | 24.82 seconds |
| Started | Feb 09 05:54:22 AM UTC 25 |
| Finished | Feb 09 05:54:48 AM UTC 25 |
| Peak memory | 295228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135778917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.135778917 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2492726256 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 10036396100 ps |
| CPU time | 64.03 seconds |
| Started | Feb 09 05:54:47 AM UTC 25 |
| Finished | Feb 09 05:55:53 AM UTC 25 |
| Peak memory | 301968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2492726256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 11.flash_ctrl_hw_prog_rma_wipe_err.2492726256 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.2693471264 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 15620400 ps |
| CPU time | 23.18 seconds |
| Started | Feb 09 05:54:40 AM UTC 25 |
| Finished | Feb 09 05:55:04 AM UTC 25 |
| Peak memory | 271308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 93471264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_ seed_err.2693471264 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.611889346 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 40124488600 ps |
| CPU time | 805.15 seconds |
| Started | Feb 09 05:52:18 AM UTC 25 |
| Finished | Feb 09 06:05:53 AM UTC 25 |
| Peak memory | 274880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611889346 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_reset.611889346 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1169209202 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1681351400 ps |
| CPU time | 255.31 seconds |
| Started | Feb 09 05:53:19 AM UTC 25 |
| Finished | Feb 09 05:57:38 AM UTC 25 |
| Peak memory | 303972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169209202 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.1169209202 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2477914056 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5741939800 ps |
| CPU time | 150.74 seconds |
| Started | Feb 09 05:53:29 AM UTC 25 |
| Finished | Feb 09 05:56:03 AM UTC 25 |
| Peak memory | 303868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2477914056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_in tr_rd_slow_flash.2477914056 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.3760359899 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3008250700 ps |
| CPU time | 79 seconds |
| Started | Feb 09 05:52:39 AM UTC 25 |
| Finished | Feb 09 05:54:00 AM UTC 25 |
| Peak memory | 275100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760359899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3760359899 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.3984899396 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 24762000 ps |
| CPU time | 23.35 seconds |
| Started | Feb 09 05:54:31 AM UTC 25 |
| Finished | Feb 09 05:54:55 AM UTC 25 |
| Peak memory | 275284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 84899396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3984899396 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3592660515 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 6314998600 ps |
| CPU time | 474.24 seconds |
| Started | Feb 09 05:52:31 AM UTC 25 |
| Finished | Feb 09 06:00:31 AM UTC 25 |
| Peak memory | 283440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3592660515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11. flash_ctrl_mp_regions.3592660515 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3419426928 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 77489000 ps |
| CPU time | 173.69 seconds |
| Started | Feb 09 05:52:18 AM UTC 25 |
| Finished | Feb 09 05:55:15 AM UTC 25 |
| Peak memory | 270972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419426928 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.3419426928 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.3514152942 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 727070400 ps |
| CPU time | 375.26 seconds |
| Started | Feb 09 05:52:10 AM UTC 25 |
| Finished | Feb 09 05:58:30 AM UTC 25 |
| Peak memory | 273056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514152942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3514152942 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.189953602 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 9808701300 ps |
| CPU time | 177.75 seconds |
| Started | Feb 09 05:53:32 AM UTC 25 |
| Finished | Feb 09 05:56:33 AM UTC 25 |
| Peak memory | 271452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189953602 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.189953602 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.223137679 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 786304600 ps |
| CPU time | 941.21 seconds |
| Started | Feb 09 05:52:05 AM UTC 25 |
| Finished | Feb 09 06:07:57 AM UTC 25 |
| Peak memory | 293852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223137679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.223137679 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1288618137 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 62003000 ps |
| CPU time | 60.02 seconds |
| Started | Feb 09 05:53:52 AM UTC 25 |
| Finished | Feb 09 05:54:54 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288618137 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.1288618137 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.1526022837 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2234946500 ps |
| CPU time | 150.35 seconds |
| Started | Feb 09 05:52:52 AM UTC 25 |
| Finished | Feb 09 05:55:26 AM UTC 25 |
| Peak memory | 301908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526022 837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.1526022837 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.1805383822 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 8758142000 ps |
| CPU time | 419.98 seconds |
| Started | Feb 09 05:53:11 AM UTC 25 |
| Finished | Feb 09 06:00:16 AM UTC 25 |
| Peak memory | 320400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805383822 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.1805383822 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1108521254 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 137521500 ps |
| CPU time | 36.5 seconds |
| Started | Feb 09 05:53:42 AM UTC 25 |
| Finished | Feb 09 05:54:20 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108521254 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.1108521254 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.667785311 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 120272400 ps |
| CPU time | 36.04 seconds |
| Started | Feb 09 05:53:43 AM UTC 25 |
| Finished | Feb 09 05:54:21 AM UTC 25 |
| Peak memory | 285624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6677 85311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.667785311 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2384766340 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2191792800 ps |
| CPU time | 85.11 seconds |
| Started | Feb 09 05:54:20 AM UTC 25 |
| Finished | Feb 09 05:55:48 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384766340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2384766340 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.3179787877 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 44371400 ps |
| CPU time | 180.83 seconds |
| Started | Feb 09 05:52:03 AM UTC 25 |
| Finished | Feb 09 05:55:07 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179787877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3179787877 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1060768642 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 129405700 ps |
| CPU time | 26.47 seconds |
| Started | Feb 09 05:57:32 AM UTC 25 |
| Finished | Feb 09 05:58:00 AM UTC 25 |
| Peak memory | 275420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060768642 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.1060768642 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.2291272489 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 51426600 ps |
| CPU time | 22.85 seconds |
| Started | Feb 09 05:57:12 AM UTC 25 |
| Finished | Feb 09 05:57:37 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291272489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2291272489 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.1328282660 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 10293900 ps |
| CPU time | 32.23 seconds |
| Started | Feb 09 05:56:43 AM UTC 25 |
| Finished | Feb 09 05:57:17 AM UTC 25 |
| Peak memory | 285800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 28282660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.1328282660 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1892381725 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 10033580400 ps |
| CPU time | 99.83 seconds |
| Started | Feb 09 05:57:31 AM UTC 25 |
| Finished | Feb 09 05:59:13 AM UTC 25 |
| Peak memory | 275272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1892381725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.flash_ctrl_hw_prog_rma_wipe_err.1892381725 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.3660384174 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 24948300 ps |
| CPU time | 19.21 seconds |
| Started | Feb 09 05:57:25 AM UTC 25 |
| Finished | Feb 09 05:57:45 AM UTC 25 |
| Peak memory | 275256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 60384174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_ seed_err.3660384174 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.4232631166 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 40126368700 ps |
| CPU time | 797.76 seconds |
| Started | Feb 09 05:55:04 AM UTC 25 |
| Finished | Feb 09 06:08:31 AM UTC 25 |
| Peak memory | 274840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232631166 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_reset.4232631166 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3970837290 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2017308000 ps |
| CPU time | 144.35 seconds |
| Started | Feb 09 05:55:04 AM UTC 25 |
| Finished | Feb 09 05:57:31 AM UTC 25 |
| Peak memory | 272836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970837290 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.3970837290 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3935472608 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 6137629300 ps |
| CPU time | 196.09 seconds |
| Started | Feb 09 05:55:48 AM UTC 25 |
| Finished | Feb 09 05:59:07 AM UTC 25 |
| Peak memory | 302180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935472608 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.3935472608 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3146968208 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 12245691700 ps |
| CPU time | 143.03 seconds |
| Started | Feb 09 05:55:53 AM UTC 25 |
| Finished | Feb 09 05:58:19 AM UTC 25 |
| Peak memory | 301824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3146968208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_in tr_rd_slow_flash.3146968208 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.553285231 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 923540400 ps |
| CPU time | 84.01 seconds |
| Started | Feb 09 05:55:16 AM UTC 25 |
| Finished | Feb 09 05:56:42 AM UTC 25 |
| Peak memory | 270996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553285231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.553285231 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.3769064473 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 48579100 ps |
| CPU time | 16.6 seconds |
| Started | Feb 09 05:57:18 AM UTC 25 |
| Finished | Feb 09 05:57:36 AM UTC 25 |
| Peak memory | 275548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 69064473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3769064473 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2130340503 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 8077666100 ps |
| CPU time | 467.1 seconds |
| Started | Feb 09 05:55:08 AM UTC 25 |
| Finished | Feb 09 06:03:01 AM UTC 25 |
| Peak memory | 283424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2130340503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12. flash_ctrl_mp_regions.2130340503 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2868211851 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 45673700 ps |
| CPU time | 164.42 seconds |
| Started | Feb 09 05:55:06 AM UTC 25 |
| Finished | Feb 09 05:57:53 AM UTC 25 |
| Peak memory | 271164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868211851 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.2868211851 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.3845398116 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2784759400 ps |
| CPU time | 736.2 seconds |
| Started | Feb 09 05:54:56 AM UTC 25 |
| Finished | Feb 09 06:07:21 AM UTC 25 |
| Peak memory | 275156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845398116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3845398116 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2204799466 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 66504200 ps |
| CPU time | 25.41 seconds |
| Started | Feb 09 05:56:03 AM UTC 25 |
| Finished | Feb 09 05:56:30 AM UTC 25 |
| Peak memory | 275440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204799466 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.2204799466 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.4128452690 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 219303700 ps |
| CPU time | 972.4 seconds |
| Started | Feb 09 05:54:55 AM UTC 25 |
| Finished | Feb 09 06:11:18 AM UTC 25 |
| Peak memory | 293852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128452690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.4128452690 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2785418336 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 75545900 ps |
| CPU time | 60 seconds |
| Started | Feb 09 05:56:37 AM UTC 25 |
| Finished | Feb 09 05:57:39 AM UTC 25 |
| Peak memory | 287708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785418336 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2785418336 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2275697848 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1232370600 ps |
| CPU time | 111.23 seconds |
| Started | Feb 09 05:55:18 AM UTC 25 |
| Finished | Feb 09 05:57:11 AM UTC 25 |
| Peak memory | 302144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275697 848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.2275697848 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.3228976398 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 15620599500 ps |
| CPU time | 416.67 seconds |
| Started | Feb 09 05:55:26 AM UTC 25 |
| Finished | Feb 09 06:02:28 AM UTC 25 |
| Peak memory | 320396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228976398 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.3228976398 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.3280034923 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 29186700 ps |
| CPU time | 50.4 seconds |
| Started | Feb 09 05:56:32 AM UTC 25 |
| Finished | Feb 09 05:57:24 AM UTC 25 |
| Peak memory | 287932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280034923 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.3280034923 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.474515121 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 77699300 ps |
| CPU time | 60.36 seconds |
| Started | Feb 09 05:56:34 AM UTC 25 |
| Finished | Feb 09 05:57:36 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4745 15121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.474515121 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3274742263 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3409417700 ps |
| CPU time | 79.53 seconds |
| Started | Feb 09 05:57:04 AM UTC 25 |
| Finished | Feb 09 05:58:26 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274742263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3274742263 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.232137085 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 68505500 ps |
| CPU time | 218.85 seconds |
| Started | Feb 09 05:54:49 AM UTC 25 |
| Finished | Feb 09 05:58:31 AM UTC 25 |
| Peak memory | 287460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232137085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.232137085 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.3072102217 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1965691400 ps |
| CPU time | 131.44 seconds |
| Started | Feb 09 05:55:16 AM UTC 25 |
| Finished | Feb 09 05:57:30 AM UTC 25 |
| Peak memory | 275496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072102217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.3072102217 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.953262053 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 139144000 ps |
| CPU time | 29.56 seconds |
| Started | Feb 09 05:59:28 AM UTC 25 |
| Finished | Feb 09 06:00:00 AM UTC 25 |
| Peak memory | 269072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953262053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.953262053 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1465274501 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 98072300 ps |
| CPU time | 24.05 seconds |
| Started | Feb 09 05:59:13 AM UTC 25 |
| Finished | Feb 09 05:59:38 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465274501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1465274501 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1767594745 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 10989600 ps |
| CPU time | 25.03 seconds |
| Started | Feb 09 05:58:46 AM UTC 25 |
| Finished | Feb 09 05:59:12 AM UTC 25 |
| Peak memory | 285768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 67594745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.1767594745 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1767906738 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 10035140000 ps |
| CPU time | 51.55 seconds |
| Started | Feb 09 05:59:26 AM UTC 25 |
| Finished | Feb 09 06:00:19 AM UTC 25 |
| Peak memory | 275312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1767906738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 13.flash_ctrl_hw_prog_rma_wipe_err.1767906738 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.955000989 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 42595300 ps |
| CPU time | 23.45 seconds |
| Started | Feb 09 05:59:24 AM UTC 25 |
| Finished | Feb 09 05:59:49 AM UTC 25 |
| Peak memory | 275732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95 5000989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_s eed_err.955000989 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.4271019492 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 260225585900 ps |
| CPU time | 930.86 seconds |
| Started | Feb 09 05:57:39 AM UTC 25 |
| Finished | Feb 09 06:13:20 AM UTC 25 |
| Peak memory | 275072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271019492 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_reset.4271019492 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.3461131941 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2223411100 ps |
| CPU time | 160.29 seconds |
| Started | Feb 09 05:57:39 AM UTC 25 |
| Finished | Feb 09 06:00:22 AM UTC 25 |
| Peak memory | 273320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461131941 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.3461131941 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.2488390098 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 803701700 ps |
| CPU time | 137.67 seconds |
| Started | Feb 09 05:58:16 AM UTC 25 |
| Finished | Feb 09 06:00:36 AM UTC 25 |
| Peak memory | 306244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488390098 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.2488390098 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.4281072970 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 193992871700 ps |
| CPU time | 413.81 seconds |
| Started | Feb 09 05:58:20 AM UTC 25 |
| Finished | Feb 09 06:05:20 AM UTC 25 |
| Peak memory | 301860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4281072970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_in tr_rd_slow_flash.4281072970 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.1393442737 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 9859745200 ps |
| CPU time | 105.95 seconds |
| Started | Feb 09 05:57:48 AM UTC 25 |
| Finished | Feb 09 05:59:36 AM UTC 25 |
| Peak memory | 275356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393442737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1393442737 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.2216163507 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 26978000 ps |
| CPU time | 19.41 seconds |
| Started | Feb 09 05:59:14 AM UTC 25 |
| Finished | Feb 09 05:59:35 AM UTC 25 |
| Peak memory | 275312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 16163507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2216163507 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3131298067 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1429554300 ps |
| CPU time | 153.97 seconds |
| Started | Feb 09 05:57:46 AM UTC 25 |
| Finished | Feb 09 06:00:23 AM UTC 25 |
| Peak memory | 275228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3131298067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. flash_ctrl_mp_regions.3131298067 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.2827924775 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 38848400 ps |
| CPU time | 162.33 seconds |
| Started | Feb 09 05:57:46 AM UTC 25 |
| Finished | Feb 09 06:00:31 AM UTC 25 |
| Peak memory | 275412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827924775 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.2827924775 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.2253215033 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 32104900 ps |
| CPU time | 180.73 seconds |
| Started | Feb 09 05:57:37 AM UTC 25 |
| Finished | Feb 09 06:00:41 AM UTC 25 |
| Peak memory | 275364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253215033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2253215033 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2226906500 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 36440200 ps |
| CPU time | 17.31 seconds |
| Started | Feb 09 05:58:26 AM UTC 25 |
| Finished | Feb 09 05:58:45 AM UTC 25 |
| Peak memory | 269000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226906500 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.2226906500 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.1370839755 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 8652034000 ps |
| CPU time | 1298.3 seconds |
| Started | Feb 09 05:57:37 AM UTC 25 |
| Finished | Feb 09 06:19:30 AM UTC 25 |
| Peak memory | 295900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370839755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1370839755 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.3102102262 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 130199600 ps |
| CPU time | 38.05 seconds |
| Started | Feb 09 05:58:44 AM UTC 25 |
| Finished | Feb 09 05:59:23 AM UTC 25 |
| Peak memory | 283868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102102262 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.3102102262 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1847948596 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 576196100 ps |
| CPU time | 132.19 seconds |
| Started | Feb 09 05:57:54 AM UTC 25 |
| Finished | Feb 09 06:00:09 AM UTC 25 |
| Peak memory | 291936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847948 596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1847948596 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.1159247373 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 49657261100 ps |
| CPU time | 478.4 seconds |
| Started | Feb 09 05:58:01 AM UTC 25 |
| Finished | Feb 09 06:06:05 AM UTC 25 |
| Peak memory | 324544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159247373 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.1159247373 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3472514715 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 47530200 ps |
| CPU time | 54.54 seconds |
| Started | Feb 09 05:58:31 AM UTC 25 |
| Finished | Feb 09 05:59:28 AM UTC 25 |
| Peak memory | 287644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472514715 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.3472514715 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.188417311 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 37320000 ps |
| CPU time | 50.98 seconds |
| Started | Feb 09 05:58:32 AM UTC 25 |
| Finished | Feb 09 05:59:25 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884 17311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.188417311 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.372505930 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1695779500 ps |
| CPU time | 73.91 seconds |
| Started | Feb 09 05:59:08 AM UTC 25 |
| Finished | Feb 09 06:00:24 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372505930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.372505930 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.2922930387 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 109730400 ps |
| CPU time | 183.89 seconds |
| Started | Feb 09 05:57:37 AM UTC 25 |
| Finished | Feb 09 06:00:44 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922930387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2922930387 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.1301228446 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1798121500 ps |
| CPU time | 140.77 seconds |
| Started | Feb 09 05:57:49 AM UTC 25 |
| Finished | Feb 09 06:00:12 AM UTC 25 |
| Peak memory | 271136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301228446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.1301228446 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.869588297 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 92291100 ps |
| CPU time | 23.91 seconds |
| Started | Feb 09 06:01:05 AM UTC 25 |
| Finished | Feb 09 06:01:31 AM UTC 25 |
| Peak memory | 269072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869588297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.869588297 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.403272209 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 16471600 ps |
| CPU time | 24.95 seconds |
| Started | Feb 09 06:00:45 AM UTC 25 |
| Finished | Feb 09 06:01:11 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403272209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.403272209 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.2136379841 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 21940800 ps |
| CPU time | 39.79 seconds |
| Started | Feb 09 06:00:37 AM UTC 25 |
| Finished | Feb 09 06:01:19 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 36379841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.2136379841 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2550580569 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 10032618300 ps |
| CPU time | 66.95 seconds |
| Started | Feb 09 06:01:04 AM UTC 25 |
| Finished | Feb 09 06:02:13 AM UTC 25 |
| Peak memory | 301932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2550580569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 14.flash_ctrl_hw_prog_rma_wipe_err.2550580569 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.924938897 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 25586800 ps |
| CPU time | 24.31 seconds |
| Started | Feb 09 06:01:01 AM UTC 25 |
| Finished | Feb 09 06:01:27 AM UTC 25 |
| Peak memory | 275260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92 4938897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_s eed_err.924938897 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.301163251 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 40122841600 ps |
| CPU time | 763.24 seconds |
| Started | Feb 09 05:59:50 AM UTC 25 |
| Finished | Feb 09 06:12:41 AM UTC 25 |
| Peak memory | 270912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301163251 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_reset.301163251 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.1747432285 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 24406013100 ps |
| CPU time | 130.84 seconds |
| Started | Feb 09 05:59:39 AM UTC 25 |
| Finished | Feb 09 06:01:53 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747432285 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.1747432285 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.936287850 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2395773700 ps |
| CPU time | 262.04 seconds |
| Started | Feb 09 06:00:26 AM UTC 25 |
| Finished | Feb 09 06:04:52 AM UTC 25 |
| Peak memory | 301924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936287850 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.936287850 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.101567423 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 46622642000 ps |
| CPU time | 215.91 seconds |
| Started | Feb 09 06:00:26 AM UTC 25 |
| Finished | Feb 09 06:04:06 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=101567423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_int r_rd_slow_flash.101567423 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.3732484758 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2246846200 ps |
| CPU time | 66.09 seconds |
| Started | Feb 09 06:00:24 AM UTC 25 |
| Finished | Feb 09 06:01:32 AM UTC 25 |
| Peak memory | 275356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732484758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3732484758 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.3419120495 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 27405700 ps |
| CPU time | 26.47 seconds |
| Started | Feb 09 06:00:53 AM UTC 25 |
| Finished | Feb 09 06:01:21 AM UTC 25 |
| Peak memory | 271220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34 19120495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3419120495 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.2669678398 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4875211200 ps |
| CPU time | 196.59 seconds |
| Started | Feb 09 06:00:01 AM UTC 25 |
| Finished | Feb 09 06:03:36 AM UTC 25 |
| Peak memory | 275300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2669678398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14. flash_ctrl_mp_regions.2669678398 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.4225119255 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 75877300 ps |
| CPU time | 171.91 seconds |
| Started | Feb 09 05:59:54 AM UTC 25 |
| Finished | Feb 09 06:02:48 AM UTC 25 |
| Peak memory | 275216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225119255 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.4225119255 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.2488124951 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 171733800 ps |
| CPU time | 702.37 seconds |
| Started | Feb 09 05:59:37 AM UTC 25 |
| Finished | Feb 09 06:11:28 AM UTC 25 |
| Peak memory | 275156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488124951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2488124951 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.1455354401 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 34119100 ps |
| CPU time | 24.72 seconds |
| Started | Feb 09 06:00:26 AM UTC 25 |
| Finished | Feb 09 06:00:52 AM UTC 25 |
| Peak memory | 275352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455354401 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.1455354401 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3965199256 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 131476500 ps |
| CPU time | 261.98 seconds |
| Started | Feb 09 05:59:36 AM UTC 25 |
| Finished | Feb 09 06:04:02 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965199256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3965199256 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.14334 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 5504740600 ps |
| CPU time | 115.67 seconds |
| Started | Feb 09 06:00:24 AM UTC 25 |
| Finished | Feb 09 06:02:22 AM UTC 25 |
| Peak memory | 291676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14334 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.14334 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.1482247625 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 7270533100 ps |
| CPU time | 462.4 seconds |
| Started | Feb 09 06:00:26 AM UTC 25 |
| Finished | Feb 09 06:08:14 AM UTC 25 |
| Peak memory | 324520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482247625 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.1482247625 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.4033774199 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 41474200 ps |
| CPU time | 37.39 seconds |
| Started | Feb 09 06:00:26 AM UTC 25 |
| Finished | Feb 09 06:01:05 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033774199 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.4033774199 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1343901034 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 29041100 ps |
| CPU time | 42.83 seconds |
| Started | Feb 09 06:00:33 AM UTC 25 |
| Finished | Feb 09 06:01:18 AM UTC 25 |
| Peak memory | 277404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343 901034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.1343901034 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.635094684 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 772587400 ps |
| CPU time | 66.08 seconds |
| Started | Feb 09 06:00:42 AM UTC 25 |
| Finished | Feb 09 06:01:50 AM UTC 25 |
| Peak memory | 275108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635094684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.635094684 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.3347598080 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 27632400 ps |
| CPU time | 179.1 seconds |
| Started | Feb 09 05:59:35 AM UTC 25 |
| Finished | Feb 09 06:02:37 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347598080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3347598080 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.1915362348 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 7899689500 ps |
| CPU time | 134.08 seconds |
| Started | Feb 09 06:00:24 AM UTC 25 |
| Finished | Feb 09 06:02:40 AM UTC 25 |
| Peak memory | 271120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915362348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.1915362348 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.1030312871 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 213724900 ps |
| CPU time | 16.94 seconds |
| Started | Feb 09 06:03:27 AM UTC 25 |
| Finished | Feb 09 06:03:45 AM UTC 25 |
| Peak memory | 269064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030312871 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.1030312871 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.79007178 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 46259100 ps |
| CPU time | 22.17 seconds |
| Started | Feb 09 06:03:02 AM UTC 25 |
| Finished | Feb 09 06:03:26 AM UTC 25 |
| Peak memory | 295292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79007178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.79007178 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.986298905 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 10013935800 ps |
| CPU time | 170.12 seconds |
| Started | Feb 09 06:03:23 AM UTC 25 |
| Finished | Feb 09 06:06:16 AM UTC 25 |
| Peak memory | 371564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=986298905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_hw_prog_rma_wipe_err.986298905 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.1378372124 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 15187200 ps |
| CPU time | 19.75 seconds |
| Started | Feb 09 06:03:21 AM UTC 25 |
| Finished | Feb 09 06:03:42 AM UTC 25 |
| Peak memory | 269260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 78372124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_ seed_err.1378372124 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.4151232460 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 50128440600 ps |
| CPU time | 950.46 seconds |
| Started | Feb 09 06:01:22 AM UTC 25 |
| Finished | Feb 09 06:17:24 AM UTC 25 |
| Peak memory | 275084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151232460 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_reset.4151232460 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.3834733680 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 24571265200 ps |
| CPU time | 153.91 seconds |
| Started | Feb 09 06:01:20 AM UTC 25 |
| Finished | Feb 09 06:03:56 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834733680 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.3834733680 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.153965669 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 8368201100 ps |
| CPU time | 271 seconds |
| Started | Feb 09 06:01:54 AM UTC 25 |
| Finished | Feb 09 06:06:29 AM UTC 25 |
| Peak memory | 293956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153965669 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.153965669 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.411469059 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 73265632300 ps |
| CPU time | 353.74 seconds |
| Started | Feb 09 06:02:14 AM UTC 25 |
| Finished | Feb 09 06:08:12 AM UTC 25 |
| Peak memory | 303904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=411469059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_int r_rd_slow_flash.411469059 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.4155007093 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4051671000 ps |
| CPU time | 87.28 seconds |
| Started | Feb 09 06:01:32 AM UTC 25 |
| Finished | Feb 09 06:03:02 AM UTC 25 |
| Peak memory | 274784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155007093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.4155007093 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2026998491 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 31002200 ps |
| CPU time | 21.77 seconds |
| Started | Feb 09 06:03:02 AM UTC 25 |
| Finished | Feb 09 06:03:26 AM UTC 25 |
| Peak memory | 275548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 26998491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.2026998491 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.2295218055 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5697199500 ps |
| CPU time | 135.94 seconds |
| Started | Feb 09 06:01:32 AM UTC 25 |
| Finished | Feb 09 06:03:51 AM UTC 25 |
| Peak memory | 274856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2295218055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. flash_ctrl_mp_regions.2295218055 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.847809432 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 45719600 ps |
| CPU time | 167.99 seconds |
| Started | Feb 09 06:01:30 AM UTC 25 |
| Finished | Feb 09 06:04:21 AM UTC 25 |
| Peak memory | 271320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847809432 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.847809432 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2941691755 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 701503700 ps |
| CPU time | 294.34 seconds |
| Started | Feb 09 06:01:19 AM UTC 25 |
| Finished | Feb 09 06:06:17 AM UTC 25 |
| Peak memory | 275288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941691755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2941691755 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.3154013378 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 34850100 ps |
| CPU time | 26.04 seconds |
| Started | Feb 09 06:02:23 AM UTC 25 |
| Finished | Feb 09 06:02:50 AM UTC 25 |
| Peak memory | 269000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154013378 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.3154013378 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.594344982 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 304908100 ps |
| CPU time | 1490.14 seconds |
| Started | Feb 09 06:01:13 AM UTC 25 |
| Finished | Feb 09 06:26:19 AM UTC 25 |
| Peak memory | 295644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594344982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.594344982 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.2394069279 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 122182100 ps |
| CPU time | 42.92 seconds |
| Started | Feb 09 06:02:41 AM UTC 25 |
| Finished | Feb 09 06:03:26 AM UTC 25 |
| Peak memory | 287672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394069279 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.2394069279 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.1892078531 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4881691300 ps |
| CPU time | 115.55 seconds |
| Started | Feb 09 06:01:33 AM UTC 25 |
| Finished | Feb 09 06:03:32 AM UTC 25 |
| Peak memory | 291604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892078 531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.1892078531 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.769118437 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3296673300 ps |
| CPU time | 408.68 seconds |
| Started | Feb 09 06:01:51 AM UTC 25 |
| Finished | Feb 09 06:08:44 AM UTC 25 |
| Peak memory | 320420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769118437 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.769118437 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.3479013498 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 29861000 ps |
| CPU time | 39.5 seconds |
| Started | Feb 09 06:02:38 AM UTC 25 |
| Finished | Feb 09 06:03:19 AM UTC 25 |
| Peak memory | 277404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479 013498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.3479013498 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.3390067246 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2446691800 ps |
| CPU time | 77.11 seconds |
| Started | Feb 09 06:02:52 AM UTC 25 |
| Finished | Feb 09 06:04:11 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390067246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3390067246 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2366381322 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 61185600 ps |
| CPU time | 224.68 seconds |
| Started | Feb 09 06:01:11 AM UTC 25 |
| Finished | Feb 09 06:05:00 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366381322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2366381322 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.2664657545 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 8399042500 ps |
| CPU time | 212.87 seconds |
| Started | Feb 09 06:01:32 AM UTC 25 |
| Finished | Feb 09 06:05:09 AM UTC 25 |
| Peak memory | 271116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664657545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.2664657545 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.1031835497 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 99025900 ps |
| CPU time | 22.77 seconds |
| Started | Feb 09 06:05:33 AM UTC 25 |
| Finished | Feb 09 06:05:57 AM UTC 25 |
| Peak memory | 269068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031835497 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.1031835497 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.3231760378 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 47804800 ps |
| CPU time | 23.07 seconds |
| Started | Feb 09 06:05:10 AM UTC 25 |
| Finished | Feb 09 06:05:34 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231760378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3231760378 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.3001551583 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 43104600 ps |
| CPU time | 37.42 seconds |
| Started | Feb 09 06:05:01 AM UTC 25 |
| Finished | Feb 09 06:05:40 AM UTC 25 |
| Peak memory | 285504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 01551583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.3001551583 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1949107857 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 10011639900 ps |
| CPU time | 255.05 seconds |
| Started | Feb 09 06:05:28 AM UTC 25 |
| Finished | Feb 09 06:09:47 AM UTC 25 |
| Peak memory | 412528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1949107857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 16.flash_ctrl_hw_prog_rma_wipe_err.1949107857 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.1810430317 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 25385700 ps |
| CPU time | 21.65 seconds |
| Started | Feb 09 06:05:21 AM UTC 25 |
| Finished | Feb 09 06:05:44 AM UTC 25 |
| Peak memory | 275256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18 10430317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_ seed_err.1810430317 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2801952497 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 40119376700 ps |
| CPU time | 793.78 seconds |
| Started | Feb 09 06:03:37 AM UTC 25 |
| Finished | Feb 09 06:17:00 AM UTC 25 |
| Peak memory | 275268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801952497 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_reset.2801952497 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.295515927 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 13816466100 ps |
| CPU time | 139.14 seconds |
| Started | Feb 09 06:03:35 AM UTC 25 |
| Finished | Feb 09 06:05:57 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295515927 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.295515927 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.1674480627 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 453317000 ps |
| CPU time | 151.39 seconds |
| Started | Feb 09 06:04:07 AM UTC 25 |
| Finished | Feb 09 06:06:41 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674480627 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.1674480627 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.704841197 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 10876568100 ps |
| CPU time | 298.08 seconds |
| Started | Feb 09 06:04:12 AM UTC 25 |
| Finished | Feb 09 06:09:14 AM UTC 25 |
| Peak memory | 301824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=704841197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_int r_rd_slow_flash.704841197 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.3385675473 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3424480400 ps |
| CPU time | 83.97 seconds |
| Started | Feb 09 06:03:46 AM UTC 25 |
| Finished | Feb 09 06:05:12 AM UTC 25 |
| Peak memory | 273052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385675473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3385675473 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.1702288668 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 64593700 ps |
| CPU time | 23.02 seconds |
| Started | Feb 09 06:05:13 AM UTC 25 |
| Finished | Feb 09 06:05:37 AM UTC 25 |
| Peak memory | 271452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 02288668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1702288668 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.2208885526 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 31606199600 ps |
| CPU time | 405.75 seconds |
| Started | Feb 09 06:03:44 AM UTC 25 |
| Finished | Feb 09 06:10:35 AM UTC 25 |
| Peak memory | 283420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2208885526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16. flash_ctrl_mp_regions.2208885526 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.299469327 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 139576000 ps |
| CPU time | 249.51 seconds |
| Started | Feb 09 06:03:43 AM UTC 25 |
| Finished | Feb 09 06:07:56 AM UTC 25 |
| Peak memory | 271384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299469327 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.299469327 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.3246956981 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 392682100 ps |
| CPU time | 302.36 seconds |
| Started | Feb 09 06:03:32 AM UTC 25 |
| Finished | Feb 09 06:08:39 AM UTC 25 |
| Peak memory | 275428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246956981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3246956981 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.823342801 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 32282600 ps |
| CPU time | 22.08 seconds |
| Started | Feb 09 06:04:22 AM UTC 25 |
| Finished | Feb 09 06:04:46 AM UTC 25 |
| Peak memory | 275156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823342801 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.823342801 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.479807901 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 91246100 ps |
| CPU time | 281.68 seconds |
| Started | Feb 09 06:03:27 AM UTC 25 |
| Finished | Feb 09 06:08:13 AM UTC 25 |
| Peak memory | 291804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479807901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.479807901 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.4214426912 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 101889400 ps |
| CPU time | 65.24 seconds |
| Started | Feb 09 06:04:53 AM UTC 25 |
| Finished | Feb 09 06:06:01 AM UTC 25 |
| Peak memory | 287900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214426912 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.4214426912 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.273779618 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2213000200 ps |
| CPU time | 110.4 seconds |
| Started | Feb 09 06:03:58 AM UTC 25 |
| Finished | Feb 09 06:05:51 AM UTC 25 |
| Peak memory | 291600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737796 18 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.273779618 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.3556078384 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 138025900 ps |
| CPU time | 58.2 seconds |
| Started | Feb 09 06:04:32 AM UTC 25 |
| Finished | Feb 09 06:05:32 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556078384 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.3556078384 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.465919880 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 46894700 ps |
| CPU time | 38.96 seconds |
| Started | Feb 09 06:04:46 AM UTC 25 |
| Finished | Feb 09 06:05:27 AM UTC 25 |
| Peak memory | 285592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4659 19880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.465919880 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.2397573073 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2532461000 ps |
| CPU time | 93.64 seconds |
| Started | Feb 09 06:05:03 AM UTC 25 |
| Finished | Feb 09 06:06:38 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397573073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2397573073 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.96433639 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 190100500 ps |
| CPU time | 154.8 seconds |
| Started | Feb 09 06:03:27 AM UTC 25 |
| Finished | Feb 09 06:06:04 AM UTC 25 |
| Peak memory | 287456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96433639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.96433639 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.7218785 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3752440800 ps |
| CPU time | 178.44 seconds |
| Started | Feb 09 06:03:52 AM UTC 25 |
| Finished | Feb 09 06:06:54 AM UTC 25 |
| Peak memory | 271152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7218785 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.7218785 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.4269215113 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 33171800 ps |
| CPU time | 24.52 seconds |
| Started | Feb 09 06:07:26 AM UTC 25 |
| Finished | Feb 09 06:07:52 AM UTC 25 |
| Peak memory | 269064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269215113 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.4269215113 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.451872677 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 17098900 ps |
| CPU time | 26.89 seconds |
| Started | Feb 09 06:06:55 AM UTC 25 |
| Finished | Feb 09 06:07:24 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451872677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.451872677 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1243549115 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 10139162100 ps |
| CPU time | 71.58 seconds |
| Started | Feb 09 06:07:25 AM UTC 25 |
| Finished | Feb 09 06:08:38 AM UTC 25 |
| Peak memory | 275308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1243549115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.flash_ctrl_hw_prog_rma_wipe_err.1243549115 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.3990463085 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 14940600 ps |
| CPU time | 25.51 seconds |
| Started | Feb 09 06:07:22 AM UTC 25 |
| Finished | Feb 09 06:07:49 AM UTC 25 |
| Peak memory | 275256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 90463085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_ seed_err.3990463085 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.40280172 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 160193398000 ps |
| CPU time | 868.02 seconds |
| Started | Feb 09 06:05:51 AM UTC 25 |
| Finished | Feb 09 06:20:29 AM UTC 25 |
| Peak memory | 272964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40280172 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_reset.40280172 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.2788188523 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 13988797500 ps |
| CPU time | 134.42 seconds |
| Started | Feb 09 06:05:45 AM UTC 25 |
| Finished | Feb 09 06:08:02 AM UTC 25 |
| Peak memory | 271208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788188523 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.2788188523 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1210914363 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3394820200 ps |
| CPU time | 243 seconds |
| Started | Feb 09 06:06:06 AM UTC 25 |
| Finished | Feb 09 06:10:13 AM UTC 25 |
| Peak memory | 302180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210914363 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.1210914363 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2931325369 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 23524677400 ps |
| CPU time | 163.47 seconds |
| Started | Feb 09 06:06:17 AM UTC 25 |
| Finished | Feb 09 06:09:03 AM UTC 25 |
| Peak memory | 301820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2931325369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_in tr_rd_slow_flash.2931325369 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.3670511778 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1581539600 ps |
| CPU time | 54.5 seconds |
| Started | Feb 09 06:05:58 AM UTC 25 |
| Finished | Feb 09 06:06:54 AM UTC 25 |
| Peak memory | 271000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670511778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3670511778 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.2676833281 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 15327300 ps |
| CPU time | 26.42 seconds |
| Started | Feb 09 06:07:22 AM UTC 25 |
| Finished | Feb 09 06:07:50 AM UTC 25 |
| Peak memory | 275284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 76833281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2676833281 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.95540244 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 42648147800 ps |
| CPU time | 336.63 seconds |
| Started | Feb 09 06:05:53 AM UTC 25 |
| Finished | Feb 09 06:11:34 AM UTC 25 |
| Peak memory | 283512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=95540244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_mp_regions.95540244 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.3132571977 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 75487600 ps |
| CPU time | 163.4 seconds |
| Started | Feb 09 06:05:52 AM UTC 25 |
| Finished | Feb 09 06:08:38 AM UTC 25 |
| Peak memory | 271308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132571977 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.3132571977 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.3626019063 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1422553500 ps |
| CPU time | 427.04 seconds |
| Started | Feb 09 06:05:41 AM UTC 25 |
| Finished | Feb 09 06:12:53 AM UTC 25 |
| Peak memory | 273368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626019063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3626019063 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1292461959 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2146584900 ps |
| CPU time | 197.61 seconds |
| Started | Feb 09 06:06:18 AM UTC 25 |
| Finished | Feb 09 06:09:39 AM UTC 25 |
| Peak memory | 275376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292461959 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.1292461959 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.4016523138 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 373800600 ps |
| CPU time | 771.13 seconds |
| Started | Feb 09 06:05:38 AM UTC 25 |
| Finished | Feb 09 06:18:38 AM UTC 25 |
| Peak memory | 291548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016523138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.4016523138 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.1357698936 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 66740600 ps |
| CPU time | 53.77 seconds |
| Started | Feb 09 06:06:39 AM UTC 25 |
| Finished | Feb 09 06:07:35 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357698936 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.1357698936 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.4142709138 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 989248900 ps |
| CPU time | 107.07 seconds |
| Started | Feb 09 06:06:01 AM UTC 25 |
| Finished | Feb 09 06:07:51 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142709 138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.4142709138 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.2343361118 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 6928189700 ps |
| CPU time | 441.2 seconds |
| Started | Feb 09 06:06:05 AM UTC 25 |
| Finished | Feb 09 06:13:32 AM UTC 25 |
| Peak memory | 320376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343361118 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.2343361118 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1633875527 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 31773900 ps |
| CPU time | 53.8 seconds |
| Started | Feb 09 06:06:30 AM UTC 25 |
| Finished | Feb 09 06:07:25 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633875527 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.1633875527 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.322110182 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 32152900 ps |
| CPU time | 52.62 seconds |
| Started | Feb 09 06:06:38 AM UTC 25 |
| Finished | Feb 09 06:07:32 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221 10182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.322110182 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.1177234556 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2206723300 ps |
| CPU time | 111.38 seconds |
| Started | Feb 09 06:06:55 AM UTC 25 |
| Finished | Feb 09 06:08:49 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177234556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1177234556 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.15147288 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 127800200 ps |
| CPU time | 305.77 seconds |
| Started | Feb 09 06:05:35 AM UTC 25 |
| Finished | Feb 09 06:10:45 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15147288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.15147288 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.4290650366 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 7720635700 ps |
| CPU time | 134.14 seconds |
| Started | Feb 09 06:05:58 AM UTC 25 |
| Finished | Feb 09 06:08:15 AM UTC 25 |
| Peak memory | 271140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290650366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.4290650366 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.79734363 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 210885100 ps |
| CPU time | 15.78 seconds |
| Started | Feb 09 06:09:08 AM UTC 25 |
| Finished | Feb 09 06:09:25 AM UTC 25 |
| Peak memory | 275468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79734363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.79734363 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.3638391260 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 44439900 ps |
| CPU time | 20.33 seconds |
| Started | Feb 09 06:08:45 AM UTC 25 |
| Finished | Feb 09 06:09:07 AM UTC 25 |
| Peak memory | 284852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638391260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3638391260 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2504599344 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 10048720100 ps |
| CPU time | 86.73 seconds |
| Started | Feb 09 06:09:06 AM UTC 25 |
| Finished | Feb 09 06:10:35 AM UTC 25 |
| Peak memory | 275552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2504599344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.flash_ctrl_hw_prog_rma_wipe_err.2504599344 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.3942707007 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 27936900 ps |
| CPU time | 23.58 seconds |
| Started | Feb 09 06:08:50 AM UTC 25 |
| Finished | Feb 09 06:09:15 AM UTC 25 |
| Peak memory | 275408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 42707007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_ seed_err.3942707007 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.1387108364 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 40124183300 ps |
| CPU time | 889.82 seconds |
| Started | Feb 09 06:07:50 AM UTC 25 |
| Finished | Feb 09 06:22:50 AM UTC 25 |
| Peak memory | 275076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387108364 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_reset.1387108364 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.3143273604 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3115984800 ps |
| CPU time | 120.4 seconds |
| Started | Feb 09 06:07:49 AM UTC 25 |
| Finished | Feb 09 06:09:52 AM UTC 25 |
| Peak memory | 270952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143273604 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.3143273604 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.1890485879 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3850117700 ps |
| CPU time | 222.67 seconds |
| Started | Feb 09 06:08:13 AM UTC 25 |
| Finished | Feb 09 06:11:59 AM UTC 25 |
| Peak memory | 301616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890485879 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.1890485879 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1427670837 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 23856228100 ps |
| CPU time | 215.79 seconds |
| Started | Feb 09 06:08:15 AM UTC 25 |
| Finished | Feb 09 06:11:55 AM UTC 25 |
| Peak memory | 303868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1427670837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_in tr_rd_slow_flash.1427670837 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.845993206 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5937617300 ps |
| CPU time | 81.06 seconds |
| Started | Feb 09 06:07:57 AM UTC 25 |
| Finished | Feb 09 06:09:20 AM UTC 25 |
| Peak memory | 271252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845993206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.845993206 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.384873911 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 80704000 ps |
| CPU time | 25.68 seconds |
| Started | Feb 09 06:08:46 AM UTC 25 |
| Finished | Feb 09 06:09:13 AM UTC 25 |
| Peak memory | 275608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 4873911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.384873911 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.2106991752 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 12095368700 ps |
| CPU time | 266.99 seconds |
| Started | Feb 09 06:07:53 AM UTC 25 |
| Finished | Feb 09 06:12:23 AM UTC 25 |
| Peak memory | 283700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2106991752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18. flash_ctrl_mp_regions.2106991752 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.843144646 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 37436300 ps |
| CPU time | 197.05 seconds |
| Started | Feb 09 06:07:52 AM UTC 25 |
| Finished | Feb 09 06:11:12 AM UTC 25 |
| Peak memory | 270916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843144646 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.843144646 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.1529344768 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 49223500 ps |
| CPU time | 88.01 seconds |
| Started | Feb 09 06:07:40 AM UTC 25 |
| Finished | Feb 09 06:09:10 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529344768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1529344768 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.2831778393 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 45001100 ps |
| CPU time | 28.75 seconds |
| Started | Feb 09 06:08:15 AM UTC 25 |
| Finished | Feb 09 06:08:46 AM UTC 25 |
| Peak memory | 269036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831778393 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.2831778393 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1434733608 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 2845104600 ps |
| CPU time | 1703.99 seconds |
| Started | Feb 09 06:07:35 AM UTC 25 |
| Finished | Feb 09 06:36:18 AM UTC 25 |
| Peak memory | 297948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434733608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1434733608 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.4237428175 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 56262900 ps |
| CPU time | 38.66 seconds |
| Started | Feb 09 06:08:39 AM UTC 25 |
| Finished | Feb 09 06:09:19 AM UTC 25 |
| Peak memory | 287900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237428175 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.4237428175 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.3434129919 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1175402400 ps |
| CPU time | 97.15 seconds |
| Started | Feb 09 06:08:02 AM UTC 25 |
| Finished | Feb 09 06:09:41 AM UTC 25 |
| Peak memory | 302188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434129 919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.3434129919 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3406162805 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 19213330600 ps |
| CPU time | 565.45 seconds |
| Started | Feb 09 06:08:13 AM UTC 25 |
| Finished | Feb 09 06:17:46 AM UTC 25 |
| Peak memory | 320176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406162805 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.3406162805 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.3728959204 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 51778200 ps |
| CPU time | 45.48 seconds |
| Started | Feb 09 06:08:32 AM UTC 25 |
| Finished | Feb 09 06:09:19 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728959204 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.3728959204 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.3387758220 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 31392700 ps |
| CPU time | 52.62 seconds |
| Started | Feb 09 06:08:32 AM UTC 25 |
| Finished | Feb 09 06:09:26 AM UTC 25 |
| Peak memory | 285588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387 758220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.3387758220 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.3912078055 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2175627300 ps |
| CPU time | 79.69 seconds |
| Started | Feb 09 06:08:40 AM UTC 25 |
| Finished | Feb 09 06:10:02 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912078055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3912078055 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.3996940449 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 48838000 ps |
| CPU time | 86.43 seconds |
| Started | Feb 09 06:07:33 AM UTC 25 |
| Finished | Feb 09 06:09:02 AM UTC 25 |
| Peak memory | 285400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996940449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3996940449 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.2330609796 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4559882000 ps |
| CPU time | 182.7 seconds |
| Started | Feb 09 06:07:58 AM UTC 25 |
| Finished | Feb 09 06:11:04 AM UTC 25 |
| Peak memory | 275212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330609796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.2330609796 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.2656572859 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 220489300 ps |
| CPU time | 23.76 seconds |
| Started | Feb 09 06:10:33 AM UTC 25 |
| Finished | Feb 09 06:10:58 AM UTC 25 |
| Peak memory | 269084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656572859 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.2656572859 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.2456148874 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 13672700 ps |
| CPU time | 23.03 seconds |
| Started | Feb 09 06:10:14 AM UTC 25 |
| Finished | Feb 09 06:10:38 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456148874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2456148874 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.1092422740 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 16044300 ps |
| CPU time | 28.09 seconds |
| Started | Feb 09 06:10:02 AM UTC 25 |
| Finished | Feb 09 06:10:32 AM UTC 25 |
| Peak memory | 285764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 92422740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.1092422740 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1975148122 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 10062144400 ps |
| CPU time | 64.56 seconds |
| Started | Feb 09 06:10:30 AM UTC 25 |
| Finished | Feb 09 06:11:36 AM UTC 25 |
| Peak memory | 275288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1975148122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 19.flash_ctrl_hw_prog_rma_wipe_err.1975148122 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.2673345980 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 47004500 ps |
| CPU time | 18.38 seconds |
| Started | Feb 09 06:10:27 AM UTC 25 |
| Finished | Feb 09 06:10:47 AM UTC 25 |
| Peak memory | 275256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 73345980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_ seed_err.2673345980 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3076944268 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 80139927500 ps |
| CPU time | 825.19 seconds |
| Started | Feb 09 06:09:15 AM UTC 25 |
| Finished | Feb 09 06:23:10 AM UTC 25 |
| Peak memory | 275404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076944268 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_reset.3076944268 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.4247399021 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4250195800 ps |
| CPU time | 116 seconds |
| Started | Feb 09 06:09:14 AM UTC 25 |
| Finished | Feb 09 06:11:12 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247399021 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.4247399021 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.4172520632 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1447953800 ps |
| CPU time | 201.32 seconds |
| Started | Feb 09 06:09:26 AM UTC 25 |
| Finished | Feb 09 06:12:50 AM UTC 25 |
| Peak memory | 293700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172520632 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.4172520632 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.397469268 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 24201175500 ps |
| CPU time | 157.29 seconds |
| Started | Feb 09 06:09:27 AM UTC 25 |
| Finished | Feb 09 06:12:07 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=397469268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_int r_rd_slow_flash.397469268 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.1996385963 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 1554110900 ps |
| CPU time | 78.24 seconds |
| Started | Feb 09 06:09:19 AM UTC 25 |
| Finished | Feb 09 06:10:39 AM UTC 25 |
| Peak memory | 275096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996385963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1996385963 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.4161387653 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 29947800 ps |
| CPU time | 23.96 seconds |
| Started | Feb 09 06:10:19 AM UTC 25 |
| Finished | Feb 09 06:10:44 AM UTC 25 |
| Peak memory | 275284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 61387653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.4161387653 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.3429880682 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 115244506200 ps |
| CPU time | 545.36 seconds |
| Started | Feb 09 06:09:17 AM UTC 25 |
| Finished | Feb 09 06:18:29 AM UTC 25 |
| Peak memory | 283420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3429880682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. flash_ctrl_mp_regions.3429880682 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.115415979 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 165105700 ps |
| CPU time | 171.66 seconds |
| Started | Feb 09 06:09:16 AM UTC 25 |
| Finished | Feb 09 06:12:11 AM UTC 25 |
| Peak memory | 271228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115415979 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.115415979 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.1149491319 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 63216200 ps |
| CPU time | 144.61 seconds |
| Started | Feb 09 06:09:11 AM UTC 25 |
| Finished | Feb 09 06:11:38 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149491319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1149491319 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.3256334448 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 101560200 ps |
| CPU time | 27.31 seconds |
| Started | Feb 09 06:09:40 AM UTC 25 |
| Finished | Feb 09 06:10:09 AM UTC 25 |
| Peak memory | 269016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256334448 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.3256334448 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.945470121 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 1004266400 ps |
| CPU time | 720.66 seconds |
| Started | Feb 09 06:09:08 AM UTC 25 |
| Finished | Feb 09 06:21:16 AM UTC 25 |
| Peak memory | 293596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945470121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.945470121 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.892924035 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 74617800 ps |
| CPU time | 38.42 seconds |
| Started | Feb 09 06:09:53 AM UTC 25 |
| Finished | Feb 09 06:10:33 AM UTC 25 |
| Peak memory | 289680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892924035 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.892924035 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.2503754744 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1116715700 ps |
| CPU time | 102.17 seconds |
| Started | Feb 09 06:09:21 AM UTC 25 |
| Finished | Feb 09 06:11:05 AM UTC 25 |
| Peak memory | 291700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503754 744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.2503754744 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.457330005 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 53375815700 ps |
| CPU time | 500.8 seconds |
| Started | Feb 09 06:09:21 AM UTC 25 |
| Finished | Feb 09 06:17:47 AM UTC 25 |
| Peak memory | 324456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457330005 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.457330005 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.1884296316 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 76532400 ps |
| CPU time | 42.11 seconds |
| Started | Feb 09 06:09:42 AM UTC 25 |
| Finished | Feb 09 06:10:26 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884296316 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.1884296316 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1957324212 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 63577900 ps |
| CPU time | 69.02 seconds |
| Started | Feb 09 06:09:08 AM UTC 25 |
| Finished | Feb 09 06:10:18 AM UTC 25 |
| Peak memory | 285392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957324212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1957324212 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.94516282 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 17083577700 ps |
| CPU time | 212.38 seconds |
| Started | Feb 09 06:09:19 AM UTC 25 |
| Finished | Feb 09 06:12:55 AM UTC 25 |
| Peak memory | 271120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94516282 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.94516282 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.3594108278 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 521214800 ps |
| CPU time | 19.86 seconds |
| Started | Feb 09 05:17:20 AM UTC 25 |
| Finished | Feb 09 05:17:41 AM UTC 25 |
| Peak memory | 269060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594108278 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3594108278 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.2215822368 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 81751500 ps |
| CPU time | 24.89 seconds |
| Started | Feb 09 05:17:00 AM UTC 25 |
| Finished | Feb 09 05:17:27 AM UTC 25 |
| Peak memory | 273144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215822368 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.2215822368 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.2924578411 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 116207500 ps |
| CPU time | 24.53 seconds |
| Started | Feb 09 05:16:23 AM UTC 25 |
| Finished | Feb 09 05:16:49 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924578411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2924578411 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.1979806722 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 957031700 ps |
| CPU time | 247.64 seconds |
| Started | Feb 09 05:15:01 AM UTC 25 |
| Finished | Feb 09 05:19:12 AM UTC 25 |
| Peak memory | 289992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 + otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1979806722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ derr_detect.1979806722 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.425047771 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 13313700 ps |
| CPU time | 28.88 seconds |
| Started | Feb 09 05:16:01 AM UTC 25 |
| Finished | Feb 09 05:16:31 AM UTC 25 |
| Peak memory | 285544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 5047771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.425047771 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.2511870029 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 37241514400 ps |
| CPU time | 677.22 seconds |
| Started | Feb 09 05:10:58 AM UTC 25 |
| Finished | Feb 09 05:22:23 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511870029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2511870029 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.4149532105 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 7105261900 ps |
| CPU time | 3161.05 seconds |
| Started | Feb 09 05:11:49 AM UTC 25 |
| Finished | Feb 09 06:05:02 AM UTC 25 |
| Peak memory | 273128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149532105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.4149532105 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3377382530 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 949534600 ps |
| CPU time | 3425.21 seconds |
| Started | Feb 09 05:11:37 AM UTC 25 |
| Finished | Feb 09 06:09:16 AM UTC 25 |
| Peak memory | 275224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377382530 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3377382530 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.4106945402 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1489860200 ps |
| CPU time | 1449 seconds |
| Started | Feb 09 05:11:39 AM UTC 25 |
| Finished | Feb 09 05:36:04 AM UTC 25 |
| Peak memory | 285412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106945402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.4106945402 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.204705169 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 65545372600 ps |
| CPU time | 3789.83 seconds |
| Started | Feb 09 05:11:29 AM UTC 25 |
| Finished | Feb 09 06:15:17 AM UTC 25 |
| Peak memory | 277860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204705169 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.204705169 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.503999539 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 65546200 ps |
| CPU time | 36.96 seconds |
| Started | Feb 09 05:17:17 AM UTC 25 |
| Finished | Feb 09 05:17:55 AM UTC 25 |
| Peak memory | 285556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503999539 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_addr_infection.503999539 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3898967337 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 324258166400 ps |
| CPU time | 2567.13 seconds |
| Started | Feb 09 05:11:15 AM UTC 25 |
| Finished | Feb 09 05:54:30 AM UTC 25 |
| Peak memory | 275440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898967337 -assert nopostproc +U VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.3898967337 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.2292421986 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 92100700 ps |
| CPU time | 54.87 seconds |
| Started | Feb 09 05:10:52 AM UTC 25 |
| Finished | Feb 09 05:11:48 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292421986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.2292421986 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.851568446 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 10019678100 ps |
| CPU time | 92.22 seconds |
| Started | Feb 09 05:17:14 AM UTC 25 |
| Finished | Feb 09 05:18:48 AM UTC 25 |
| Peak memory | 340848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=851568446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_hw_prog_rma_wipe_err.851568446 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.1544842792 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 28566700 ps |
| CPU time | 26.63 seconds |
| Started | Feb 09 05:17:08 AM UTC 25 |
| Finished | Feb 09 05:17:36 AM UTC 25 |
| Peak memory | 269152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 44842792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_s eed_err.1544842792 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2469325845 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 337637611100 ps |
| CPU time | 2127.73 seconds |
| Started | Feb 09 05:11:06 AM UTC 25 |
| Finished | Feb 09 05:46:55 AM UTC 25 |
| Peak memory | 271236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469325845 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.2469325845 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.1901581407 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 40123748400 ps |
| CPU time | 770.51 seconds |
| Started | Feb 09 05:11:08 AM UTC 25 |
| Finished | Feb 09 05:24:07 AM UTC 25 |
| Peak memory | 274860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901581407 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.1901581407 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.2731933579 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3501063500 ps |
| CPU time | 105.41 seconds |
| Started | Feb 09 05:10:58 AM UTC 25 |
| Finished | Feb 09 05:12:45 AM UTC 25 |
| Peak memory | 275040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731933579 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.2731933579 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.539753125 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3610468300 ps |
| CPU time | 563.61 seconds |
| Started | Feb 09 05:15:10 AM UTC 25 |
| Finished | Feb 09 05:24:41 AM UTC 25 |
| Peak memory | 338872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5397531 25 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integrity.539753125 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.193411499 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7422027600 ps |
| CPU time | 168.37 seconds |
| Started | Feb 09 05:15:10 AM UTC 25 |
| Finished | Feb 09 05:18:02 AM UTC 25 |
| Peak memory | 306056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193411499 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.193411499 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2609880141 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 23993929200 ps |
| CPU time | 218.56 seconds |
| Started | Feb 09 05:15:22 AM UTC 25 |
| Finished | Feb 09 05:19:04 AM UTC 25 |
| Peak memory | 303908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2609880141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_int r_rd_slow_flash.2609880141 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.1273470860 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 4641058100 ps |
| CPU time | 105.51 seconds |
| Started | Feb 09 05:15:13 AM UTC 25 |
| Finished | Feb 09 05:17:01 AM UTC 25 |
| Peak memory | 271156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273470860 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.1273470860 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2090383789 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 55085207600 ps |
| CPU time | 244.42 seconds |
| Started | Feb 09 05:15:24 AM UTC 25 |
| Finished | Feb 09 05:19:32 AM UTC 25 |
| Peak memory | 271136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2090383789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_intr_wr_slow_flash.2090383789 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1602366921 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1861102200 ps |
| CPU time | 85.02 seconds |
| Started | Feb 09 05:12:07 AM UTC 25 |
| Finished | Feb 09 05:13:34 AM UTC 25 |
| Peak memory | 273372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602366921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1602366921 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.1382174685 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 46453000 ps |
| CPU time | 19.25 seconds |
| Started | Feb 09 05:17:02 AM UTC 25 |
| Finished | Feb 09 05:17:23 AM UTC 25 |
| Peak memory | 273240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 82174685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1382174685 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.367583990 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3424387000 ps |
| CPU time | 90.42 seconds |
| Started | Feb 09 05:12:15 AM UTC 25 |
| Finished | Feb 09 05:13:47 AM UTC 25 |
| Peak memory | 270912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367583990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.367583990 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1081388579 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 7778370600 ps |
| CPU time | 225.06 seconds |
| Started | Feb 09 05:11:20 AM UTC 25 |
| Finished | Feb 09 05:15:09 AM UTC 25 |
| Peak memory | 283432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1081388579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.f lash_ctrl_mp_regions.1081388579 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.705833800 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 65076500 ps |
| CPU time | 227.79 seconds |
| Started | Feb 09 05:11:08 AM UTC 25 |
| Finished | Feb 09 05:14:59 AM UTC 25 |
| Peak memory | 270708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705833800 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.705833800 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3643948556 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1824987400 ps |
| CPU time | 249.84 seconds |
| Started | Feb 09 05:15:03 AM UTC 25 |
| Finished | Feb 09 05:19:16 AM UTC 25 |
| Peak memory | 291720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_ pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3643948556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.f lash_ctrl_oversize_error.3643948556 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.640374750 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 43722700 ps |
| CPU time | 17.74 seconds |
| Started | Feb 09 05:16:57 AM UTC 25 |
| Finished | Feb 09 05:17:16 AM UTC 25 |
| Peak memory | 275472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct =4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640374750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy _ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.640374750 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.3177455694 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3341221900 ps |
| CPU time | 901.53 seconds |
| Started | Feb 09 05:10:58 AM UTC 25 |
| Finished | Feb 09 05:26:09 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177455694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3177455694 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.3474827566 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 23318300 ps |
| CPU time | 19.34 seconds |
| Started | Feb 09 05:16:52 AM UTC 25 |
| Finished | Feb 09 05:17:13 AM UTC 25 |
| Peak memory | 275688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3474827566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3474827566 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1297592334 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 47766300 ps |
| CPU time | 27.54 seconds |
| Started | Feb 09 05:15:39 AM UTC 25 |
| Finished | Feb 09 05:16:08 AM UTC 25 |
| Peak memory | 271156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297592334 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.1297592334 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1556942501 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1632217500 ps |
| CPU time | 926.41 seconds |
| Started | Feb 09 05:10:45 AM UTC 25 |
| Finished | Feb 09 05:26:21 AM UTC 25 |
| Peak memory | 295644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556942501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1556942501 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3968259019 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 978224300 ps |
| CPU time | 47.66 seconds |
| Started | Feb 09 05:16:30 AM UTC 25 |
| Finished | Feb 09 05:17:19 AM UTC 25 |
| Peak memory | 285560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968259019 -assert n opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.3968259019 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2168970024 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 95955700 ps |
| CPU time | 58.24 seconds |
| Started | Feb 09 05:16:01 AM UTC 25 |
| Finished | Feb 09 05:17:01 AM UTC 25 |
| Peak memory | 287680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168970024 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.2168970024 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.766324308 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 32730200 ps |
| CPU time | 46.75 seconds |
| Started | Feb 09 05:14:21 AM UTC 25 |
| Finished | Feb 09 05:15:09 AM UTC 25 |
| Peak memory | 275296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7663243 08 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_ derr.766324308 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.2149669441 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 24442600 ps |
| CPU time | 37.28 seconds |
| Started | Feb 09 05:13:03 AM UTC 25 |
| Finished | Feb 09 05:13:42 AM UTC 25 |
| Peak memory | 275624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149669441 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.2149669441 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2076511194 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 171144710300 ps |
| CPU time | 928.49 seconds |
| Started | Feb 09 05:17:01 AM UTC 25 |
| Finished | Feb 09 05:32:40 AM UTC 25 |
| Peak memory | 273024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_0 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2076511194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2076511194 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2743928917 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 474400600 ps |
| CPU time | 143.91 seconds |
| Started | Feb 09 05:12:46 AM UTC 25 |
| Finished | Feb 09 05:15:13 AM UTC 25 |
| Peak memory | 304060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743928 917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.2743928917 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2782442811 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1448708000 ps |
| CPU time | 175.66 seconds |
| Started | Feb 09 05:14:39 AM UTC 25 |
| Finished | Feb 09 05:17:37 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2782442811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_ro_derr.2782442811 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.636020281 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 628201500 ps |
| CPU time | 163.61 seconds |
| Started | Feb 09 05:13:36 AM UTC 25 |
| Finished | Feb 09 05:16:22 AM UTC 25 |
| Peak memory | 306048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=636020281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.636020281 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4059954513 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 4178982700 ps |
| CPU time | 549.1 seconds |
| Started | Feb 09 05:12:50 AM UTC 25 |
| Finished | Feb 09 05:22:06 AM UTC 25 |
| Peak memory | 324516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059954513 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.4059954513 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.1594132447 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29517600 ps |
| CPU time | 42.53 seconds |
| Started | Feb 09 05:15:45 AM UTC 25 |
| Finished | Feb 09 05:16:29 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594132447 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.1594132447 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.243863087 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 27698600 ps |
| CPU time | 45.12 seconds |
| Started | Feb 09 05:15:45 AM UTC 25 |
| Finished | Feb 09 05:16:31 AM UTC 25 |
| Peak memory | 285848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438 63087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.243863087 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.2427624274 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3972684200 ps |
| CPU time | 185.27 seconds |
| Started | Feb 09 05:13:43 AM UTC 25 |
| Finished | Feb 09 05:16:51 AM UTC 25 |
| Peak memory | 306048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242762427 4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.2427624274 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3582835441 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2233129900 ps |
| CPU time | 83.09 seconds |
| Started | Feb 09 05:16:09 AM UTC 25 |
| Finished | Feb 09 05:17:34 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582835441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3582835441 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.3988647264 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2179152400 ps |
| CPU time | 85.78 seconds |
| Started | Feb 09 05:14:10 AM UTC 25 |
| Finished | Feb 09 05:15:38 AM UTC 25 |
| Peak memory | 275332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988647264 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr_address.3988647264 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.746840358 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2297486400 ps |
| CPU time | 91.42 seconds |
| Started | Feb 09 05:13:48 AM UTC 25 |
| Finished | Feb 09 05:15:21 AM UTC 25 |
| Peak memory | 285576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746840358 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr_counter.746840358 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.683305801 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 28339700 ps |
| CPU time | 88.15 seconds |
| Started | Feb 09 05:10:43 AM UTC 25 |
| Finished | Feb 09 05:12:13 AM UTC 25 |
| Peak memory | 287712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683305801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.683305801 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.3298480190 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 53754000 ps |
| CPU time | 37.56 seconds |
| Started | Feb 09 05:10:44 AM UTC 25 |
| Finished | Feb 09 05:11:23 AM UTC 25 |
| Peak memory | 270888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298480190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3298480190 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.4069868302 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 305007000 ps |
| CPU time | 911.89 seconds |
| Started | Feb 09 05:16:10 AM UTC 25 |
| Finished | Feb 09 05:31:33 AM UTC 25 |
| Peak memory | 301740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069868302 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.4069868302 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.4064543444 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 23076700 ps |
| CPU time | 40.48 seconds |
| Started | Feb 09 05:10:45 AM UTC 25 |
| Finished | Feb 09 05:11:28 AM UTC 25 |
| Peak memory | 272936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064543444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.4064543444 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.2100012148 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 8048989900 ps |
| CPU time | 220.51 seconds |
| Started | Feb 09 05:12:15 AM UTC 25 |
| Finished | Feb 09 05:15:59 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100012148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.2100012148 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.1042662391 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 213449600 ps |
| CPU time | 26.45 seconds |
| Started | Feb 09 05:16:32 AM UTC 25 |
| Finished | Feb 09 05:17:00 AM UTC 25 |
| Peak memory | 271480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_r d_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1042662391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_i ntg.1042662391 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.3296726261 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 334305500 ps |
| CPU time | 21.15 seconds |
| Started | Feb 09 06:11:01 AM UTC 25 |
| Finished | Feb 09 06:11:24 AM UTC 25 |
| Peak memory | 269064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296726261 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.3296726261 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2149948149 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 14386400 ps |
| CPU time | 28.44 seconds |
| Started | Feb 09 06:10:59 AM UTC 25 |
| Finished | Feb 09 06:11:29 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149948149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2149948149 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.154661620 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 10080400 ps |
| CPU time | 39.16 seconds |
| Started | Feb 09 06:10:47 AM UTC 25 |
| Finished | Feb 09 06:11:27 AM UTC 25 |
| Peak memory | 285516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 4661620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.154661620 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.390261346 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8803805600 ps |
| CPU time | 115.22 seconds |
| Started | Feb 09 06:10:34 AM UTC 25 |
| Finished | Feb 09 06:12:32 AM UTC 25 |
| Peak memory | 271272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390261346 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.390261346 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.2626479352 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2599734300 ps |
| CPU time | 142.15 seconds |
| Started | Feb 09 06:10:37 AM UTC 25 |
| Finished | Feb 09 06:13:02 AM UTC 25 |
| Peak memory | 301988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626479352 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.2626479352 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.628913534 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 46972916400 ps |
| CPU time | 269.65 seconds |
| Started | Feb 09 06:10:39 AM UTC 25 |
| Finished | Feb 09 06:15:12 AM UTC 25 |
| Peak memory | 303904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=628913534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_int r_rd_slow_flash.628913534 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.4249819545 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 143729000 ps |
| CPU time | 141.81 seconds |
| Started | Feb 09 06:10:37 AM UTC 25 |
| Finished | Feb 09 06:13:01 AM UTC 25 |
| Peak memory | 271060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249819545 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.4249819545 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.2269687279 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 21428500 ps |
| CPU time | 24.59 seconds |
| Started | Feb 09 06:10:40 AM UTC 25 |
| Finished | Feb 09 06:11:06 AM UTC 25 |
| Peak memory | 275208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269687279 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.2269687279 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.164821938 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 30051800 ps |
| CPU time | 35.5 seconds |
| Started | Feb 09 06:10:41 AM UTC 25 |
| Finished | Feb 09 06:11:18 AM UTC 25 |
| Peak memory | 287676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164821938 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.164821938 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3612243533 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 54043400 ps |
| CPU time | 52.37 seconds |
| Started | Feb 09 06:10:45 AM UTC 25 |
| Finished | Feb 09 06:11:39 AM UTC 25 |
| Peak memory | 287644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612 243533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3612243533 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2763656999 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 566794600 ps |
| CPU time | 60.88 seconds |
| Started | Feb 09 06:10:48 AM UTC 25 |
| Finished | Feb 09 06:11:50 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763656999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2763656999 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.3429976732 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1595853400 ps |
| CPU time | 189.09 seconds |
| Started | Feb 09 06:10:33 AM UTC 25 |
| Finished | Feb 09 06:13:45 AM UTC 25 |
| Peak memory | 291536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429976732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3429976732 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.368943772 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 48086300 ps |
| CPU time | 25.8 seconds |
| Started | Feb 09 06:11:29 AM UTC 25 |
| Finished | Feb 09 06:11:57 AM UTC 25 |
| Peak memory | 268816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368943772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.368943772 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.3047095300 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 50718500 ps |
| CPU time | 26.79 seconds |
| Started | Feb 09 06:11:28 AM UTC 25 |
| Finished | Feb 09 06:11:57 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047095300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3047095300 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.2983129652 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 19258600 ps |
| CPU time | 38.05 seconds |
| Started | Feb 09 06:11:24 AM UTC 25 |
| Finished | Feb 09 06:12:03 AM UTC 25 |
| Peak memory | 285832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 83129652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.2983129652 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.2049815296 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1547273600 ps |
| CPU time | 75.9 seconds |
| Started | Feb 09 06:11:05 AM UTC 25 |
| Finished | Feb 09 06:12:23 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049815296 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.2049815296 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.2491112075 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 16068451600 ps |
| CPU time | 213.28 seconds |
| Started | Feb 09 06:11:07 AM UTC 25 |
| Finished | Feb 09 06:14:44 AM UTC 25 |
| Peak memory | 293700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491112075 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.2491112075 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.4102606284 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 23345886100 ps |
| CPU time | 202.04 seconds |
| Started | Feb 09 06:11:13 AM UTC 25 |
| Finished | Feb 09 06:14:38 AM UTC 25 |
| Peak memory | 303908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4102606284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_in tr_rd_slow_flash.4102606284 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.2817324920 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 81980200 ps |
| CPU time | 217.39 seconds |
| Started | Feb 09 06:11:06 AM UTC 25 |
| Finished | Feb 09 06:14:47 AM UTC 25 |
| Peak memory | 271056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817324920 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.2817324920 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.1250276689 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 119560900 ps |
| CPU time | 23.89 seconds |
| Started | Feb 09 06:11:13 AM UTC 25 |
| Finished | Feb 09 06:11:38 AM UTC 25 |
| Peak memory | 275156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250276689 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.1250276689 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.2925925183 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 39902400 ps |
| CPU time | 41.64 seconds |
| Started | Feb 09 06:11:19 AM UTC 25 |
| Finished | Feb 09 06:12:02 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925925183 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.2925925183 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.3493289505 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 110839500 ps |
| CPU time | 51.08 seconds |
| Started | Feb 09 06:11:19 AM UTC 25 |
| Finished | Feb 09 06:12:12 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493 289505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3493289505 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.4167991777 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1250726000 ps |
| CPU time | 93.62 seconds |
| Started | Feb 09 06:11:27 AM UTC 25 |
| Finished | Feb 09 06:13:03 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167991777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.4167991777 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2793809981 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 11250286800 ps |
| CPU time | 307.85 seconds |
| Started | Feb 09 06:11:02 AM UTC 25 |
| Finished | Feb 09 06:16:14 AM UTC 25 |
| Peak memory | 291496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793809981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2793809981 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.1886528934 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 220846500 ps |
| CPU time | 21.83 seconds |
| Started | Feb 09 06:12:03 AM UTC 25 |
| Finished | Feb 09 06:12:26 AM UTC 25 |
| Peak memory | 275208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886528934 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.1886528934 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.3749363796 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 15528000 ps |
| CPU time | 18.41 seconds |
| Started | Feb 09 06:12:00 AM UTC 25 |
| Finished | Feb 09 06:12:20 AM UTC 25 |
| Peak memory | 295288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749363796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3749363796 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.1308889449 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 19760900 ps |
| CPU time | 33.66 seconds |
| Started | Feb 09 06:11:58 AM UTC 25 |
| Finished | Feb 09 06:12:33 AM UTC 25 |
| Peak memory | 285340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 08889449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.1308889449 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.1225468021 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 8267794900 ps |
| CPU time | 95.06 seconds |
| Started | Feb 09 06:11:35 AM UTC 25 |
| Finished | Feb 09 06:13:12 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225468021 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.1225468021 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.148299525 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 37895931000 ps |
| CPU time | 341.67 seconds |
| Started | Feb 09 06:11:39 AM UTC 25 |
| Finished | Feb 09 06:17:26 AM UTC 25 |
| Peak memory | 306016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=148299525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_int r_rd_slow_flash.148299525 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1485252420 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 41571700 ps |
| CPU time | 202.08 seconds |
| Started | Feb 09 06:11:37 AM UTC 25 |
| Finished | Feb 09 06:15:02 AM UTC 25 |
| Peak memory | 271060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485252420 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.1485252420 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3063423282 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 558588900 ps |
| CPU time | 48.55 seconds |
| Started | Feb 09 06:11:39 AM UTC 25 |
| Finished | Feb 09 06:12:30 AM UTC 25 |
| Peak memory | 271472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063423282 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.3063423282 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.270360577 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 166476000 ps |
| CPU time | 52.93 seconds |
| Started | Feb 09 06:11:51 AM UTC 25 |
| Finished | Feb 09 06:12:46 AM UTC 25 |
| Peak memory | 287636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270360577 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.270360577 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.3627401626 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 70194100 ps |
| CPU time | 49.72 seconds |
| Started | Feb 09 06:11:56 AM UTC 25 |
| Finished | Feb 09 06:12:47 AM UTC 25 |
| Peak memory | 277692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627 401626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.3627401626 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.3993241652 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2912033200 ps |
| CPU time | 87.31 seconds |
| Started | Feb 09 06:11:58 AM UTC 25 |
| Finished | Feb 09 06:13:27 AM UTC 25 |
| Peak memory | 275016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993241652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3993241652 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.660313996 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 25178500 ps |
| CPU time | 161.72 seconds |
| Started | Feb 09 06:11:29 AM UTC 25 |
| Finished | Feb 09 06:14:14 AM UTC 25 |
| Peak memory | 287196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660313996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.660313996 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1572832883 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 34993200 ps |
| CPU time | 27.59 seconds |
| Started | Feb 09 06:12:42 AM UTC 25 |
| Finished | Feb 09 06:13:11 AM UTC 25 |
| Peak memory | 269324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572832883 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.1572832883 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1453740693 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 14635500 ps |
| CPU time | 20.97 seconds |
| Started | Feb 09 06:12:33 AM UTC 25 |
| Finished | Feb 09 06:12:56 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453740693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1453740693 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.3615049656 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 16589700 ps |
| CPU time | 36.23 seconds |
| Started | Feb 09 06:12:30 AM UTC 25 |
| Finished | Feb 09 06:13:08 AM UTC 25 |
| Peak memory | 285508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 15049656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.3615049656 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3639996713 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1877750800 ps |
| CPU time | 77.34 seconds |
| Started | Feb 09 06:12:08 AM UTC 25 |
| Finished | Feb 09 06:13:28 AM UTC 25 |
| Peak memory | 275176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639996713 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.3639996713 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.189641122 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1716524000 ps |
| CPU time | 125.81 seconds |
| Started | Feb 09 06:12:12 AM UTC 25 |
| Finished | Feb 09 06:14:21 AM UTC 25 |
| Peak memory | 302276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189641122 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.189641122 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3951531518 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 6068206400 ps |
| CPU time | 203.64 seconds |
| Started | Feb 09 06:12:20 AM UTC 25 |
| Finished | Feb 09 06:15:47 AM UTC 25 |
| Peak memory | 303908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3951531518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_in tr_rd_slow_flash.3951531518 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.938164269 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 211644400 ps |
| CPU time | 176.47 seconds |
| Started | Feb 09 06:12:11 AM UTC 25 |
| Finished | Feb 09 06:15:11 AM UTC 25 |
| Peak memory | 275268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938164269 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.938164269 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.2881012179 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 20787800 ps |
| CPU time | 24.15 seconds |
| Started | Feb 09 06:12:23 AM UTC 25 |
| Finished | Feb 09 06:12:49 AM UTC 25 |
| Peak memory | 271064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881012179 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.2881012179 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.882708560 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 65513900 ps |
| CPU time | 40.06 seconds |
| Started | Feb 09 06:12:25 AM UTC 25 |
| Finished | Feb 09 06:13:07 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882708560 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.882708560 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3276261528 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 26913300 ps |
| CPU time | 52.21 seconds |
| Started | Feb 09 06:12:27 AM UTC 25 |
| Finished | Feb 09 06:13:21 AM UTC 25 |
| Peak memory | 277404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276 261528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3276261528 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.3381891919 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2314526300 ps |
| CPU time | 83.65 seconds |
| Started | Feb 09 06:12:32 AM UTC 25 |
| Finished | Feb 09 06:13:58 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381891919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3381891919 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.2322674044 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 116763800 ps |
| CPU time | 113.56 seconds |
| Started | Feb 09 06:12:04 AM UTC 25 |
| Finished | Feb 09 06:14:00 AM UTC 25 |
| Peak memory | 287704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322674044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2322674044 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.965049257 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 35391400 ps |
| CPU time | 24.41 seconds |
| Started | Feb 09 06:13:09 AM UTC 25 |
| Finished | Feb 09 06:13:35 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965049257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.965049257 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.692692090 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 17031400 ps |
| CPU time | 29.08 seconds |
| Started | Feb 09 06:13:08 AM UTC 25 |
| Finished | Feb 09 06:13:38 AM UTC 25 |
| Peak memory | 295228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692692090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.692692090 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.365640221 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 14337700 ps |
| CPU time | 34.03 seconds |
| Started | Feb 09 06:13:02 AM UTC 25 |
| Finished | Feb 09 06:13:38 AM UTC 25 |
| Peak memory | 285544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 5640221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.365640221 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.4228694329 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2465336300 ps |
| CPU time | 184.11 seconds |
| Started | Feb 09 06:12:48 AM UTC 25 |
| Finished | Feb 09 06:15:55 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228694329 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.4228694329 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.200898802 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 22689291500 ps |
| CPU time | 151.17 seconds |
| Started | Feb 09 06:12:54 AM UTC 25 |
| Finished | Feb 09 06:15:28 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=200898802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_int r_rd_slow_flash.200898802 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.1750578319 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 41837400 ps |
| CPU time | 132.68 seconds |
| Started | Feb 09 06:12:50 AM UTC 25 |
| Finished | Feb 09 06:15:05 AM UTC 25 |
| Peak memory | 271164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750578319 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.1750578319 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.3642275722 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1572617300 ps |
| CPU time | 122.5 seconds |
| Started | Feb 09 06:12:56 AM UTC 25 |
| Finished | Feb 09 06:15:01 AM UTC 25 |
| Peak memory | 271120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642275722 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.3642275722 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.989205571 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 31438400 ps |
| CPU time | 51.39 seconds |
| Started | Feb 09 06:12:56 AM UTC 25 |
| Finished | Feb 09 06:13:49 AM UTC 25 |
| Peak memory | 287896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989205571 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.989205571 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3293051600 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 105959800 ps |
| CPU time | 42.95 seconds |
| Started | Feb 09 06:13:02 AM UTC 25 |
| Finished | Feb 09 06:13:47 AM UTC 25 |
| Peak memory | 287644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293 051600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3293051600 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.1935680614 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 354809000 ps |
| CPU time | 60.04 seconds |
| Started | Feb 09 06:13:03 AM UTC 25 |
| Finished | Feb 09 06:14:05 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935680614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1935680614 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.3641530927 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 56030700 ps |
| CPU time | 179.37 seconds |
| Started | Feb 09 06:12:47 AM UTC 25 |
| Finished | Feb 09 06:15:49 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641530927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3641530927 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.3168466649 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 107935900 ps |
| CPU time | 24.18 seconds |
| Started | Feb 09 06:13:46 AM UTC 25 |
| Finished | Feb 09 06:14:11 AM UTC 25 |
| Peak memory | 269068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168466649 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.3168466649 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.3714294383 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 55339700 ps |
| CPU time | 26.1 seconds |
| Started | Feb 09 06:13:39 AM UTC 25 |
| Finished | Feb 09 06:14:06 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714294383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.3714294383 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3674458002 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2620860100 ps |
| CPU time | 87.82 seconds |
| Started | Feb 09 06:13:13 AM UTC 25 |
| Finished | Feb 09 06:14:43 AM UTC 25 |
| Peak memory | 270952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674458002 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.3674458002 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1719324021 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 11690220800 ps |
| CPU time | 149.02 seconds |
| Started | Feb 09 06:13:22 AM UTC 25 |
| Finished | Feb 09 06:15:54 AM UTC 25 |
| Peak memory | 303904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1719324021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_in tr_rd_slow_flash.1719324021 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.635851975 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 472262200 ps |
| CPU time | 187.61 seconds |
| Started | Feb 09 06:13:15 AM UTC 25 |
| Finished | Feb 09 06:16:26 AM UTC 25 |
| Peak memory | 271364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635851975 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.635851975 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.2540775030 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 36666600 ps |
| CPU time | 23.32 seconds |
| Started | Feb 09 06:13:28 AM UTC 25 |
| Finished | Feb 09 06:13:53 AM UTC 25 |
| Peak memory | 269036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540775030 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.2540775030 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.416066198 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 45126100 ps |
| CPU time | 34.94 seconds |
| Started | Feb 09 06:13:28 AM UTC 25 |
| Finished | Feb 09 06:14:05 AM UTC 25 |
| Peak memory | 285624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416066198 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.416066198 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.2074689979 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 64897300 ps |
| CPU time | 51.44 seconds |
| Started | Feb 09 06:13:32 AM UTC 25 |
| Finished | Feb 09 06:14:26 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074 689979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2074689979 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1199772338 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1676399900 ps |
| CPU time | 82.99 seconds |
| Started | Feb 09 06:13:39 AM UTC 25 |
| Finished | Feb 09 06:15:04 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199772338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1199772338 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1767143511 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 18180800 ps |
| CPU time | 159.46 seconds |
| Started | Feb 09 06:13:12 AM UTC 25 |
| Finished | Feb 09 06:15:54 AM UTC 25 |
| Peak memory | 289488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767143511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1767143511 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.603433224 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 103641700 ps |
| CPU time | 16.47 seconds |
| Started | Feb 09 06:14:21 AM UTC 25 |
| Finished | Feb 09 06:14:39 AM UTC 25 |
| Peak memory | 275284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603433224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.603433224 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.2967943083 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 18877000 ps |
| CPU time | 24.65 seconds |
| Started | Feb 09 06:14:20 AM UTC 25 |
| Finished | Feb 09 06:14:46 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967943083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2967943083 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.85396196 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 11959300 ps |
| CPU time | 35.23 seconds |
| Started | Feb 09 06:14:13 AM UTC 25 |
| Finished | Feb 09 06:14:49 AM UTC 25 |
| Peak memory | 285488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85 396196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.85396196 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.1359035488 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1281682300 ps |
| CPU time | 100.46 seconds |
| Started | Feb 09 06:13:50 AM UTC 25 |
| Finished | Feb 09 06:15:33 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359035488 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.1359035488 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.3297053802 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2030366500 ps |
| CPU time | 137.74 seconds |
| Started | Feb 09 06:13:59 AM UTC 25 |
| Finished | Feb 09 06:16:20 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297053802 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.3297053802 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.4201402441 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 25437525300 ps |
| CPU time | 185.69 seconds |
| Started | Feb 09 06:14:00 AM UTC 25 |
| Finished | Feb 09 06:17:09 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4201402441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_in tr_rd_slow_flash.4201402441 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.1942107713 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 163119000 ps |
| CPU time | 169.45 seconds |
| Started | Feb 09 06:13:54 AM UTC 25 |
| Finished | Feb 09 06:16:46 AM UTC 25 |
| Peak memory | 275404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942107713 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.1942107713 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.4120193896 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 17588000 ps |
| CPU time | 19.98 seconds |
| Started | Feb 09 06:14:05 AM UTC 25 |
| Finished | Feb 09 06:14:27 AM UTC 25 |
| Peak memory | 271320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120193896 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.4120193896 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.243986840 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 29069000 ps |
| CPU time | 48.34 seconds |
| Started | Feb 09 06:14:06 AM UTC 25 |
| Finished | Feb 09 06:14:57 AM UTC 25 |
| Peak memory | 287896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243986840 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.243986840 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.1762059329 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 59582200 ps |
| CPU time | 50.95 seconds |
| Started | Feb 09 06:14:08 AM UTC 25 |
| Finished | Feb 09 06:15:00 AM UTC 25 |
| Peak memory | 285588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762 059329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1762059329 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.1650655699 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 12781826300 ps |
| CPU time | 102.09 seconds |
| Started | Feb 09 06:14:15 AM UTC 25 |
| Finished | Feb 09 06:15:59 AM UTC 25 |
| Peak memory | 273068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650655699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1650655699 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.781045035 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 49866200 ps |
| CPU time | 121.5 seconds |
| Started | Feb 09 06:13:48 AM UTC 25 |
| Finished | Feb 09 06:15:52 AM UTC 25 |
| Peak memory | 287460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781045035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.781045035 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.1323945961 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 105813700 ps |
| CPU time | 28.22 seconds |
| Started | Feb 09 06:15:02 AM UTC 25 |
| Finished | Feb 09 06:15:32 AM UTC 25 |
| Peak memory | 275212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323945961 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.1323945961 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.2786662903 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 14774200 ps |
| CPU time | 24.57 seconds |
| Started | Feb 09 06:15:01 AM UTC 25 |
| Finished | Feb 09 06:15:27 AM UTC 25 |
| Peak memory | 295028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786662903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2786662903 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2965079904 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 30682900 ps |
| CPU time | 41.05 seconds |
| Started | Feb 09 06:14:50 AM UTC 25 |
| Finished | Feb 09 06:15:33 AM UTC 25 |
| Peak memory | 285504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 65079904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.2965079904 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.1954076823 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 11218896000 ps |
| CPU time | 199.98 seconds |
| Started | Feb 09 06:14:27 AM UTC 25 |
| Finished | Feb 09 06:17:50 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954076823 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.1954076823 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.4095348497 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 759923100 ps |
| CPU time | 143.69 seconds |
| Started | Feb 09 06:14:39 AM UTC 25 |
| Finished | Feb 09 06:17:06 AM UTC 25 |
| Peak memory | 306048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095348497 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.4095348497 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.119655394 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 46809779400 ps |
| CPU time | 165.77 seconds |
| Started | Feb 09 06:14:43 AM UTC 25 |
| Finished | Feb 09 06:17:32 AM UTC 25 |
| Peak memory | 305984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=119655394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_int r_rd_slow_flash.119655394 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.1871939907 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 285539500 ps |
| CPU time | 162.65 seconds |
| Started | Feb 09 06:14:39 AM UTC 25 |
| Finished | Feb 09 06:17:25 AM UTC 25 |
| Peak memory | 271232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871939907 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.1871939907 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2552158836 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 55114300 ps |
| CPU time | 21.61 seconds |
| Started | Feb 09 06:14:45 AM UTC 25 |
| Finished | Feb 09 06:15:08 AM UTC 25 |
| Peak memory | 269000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552158836 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.2552158836 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.4277063181 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 162425500 ps |
| CPU time | 43.04 seconds |
| Started | Feb 09 06:14:47 AM UTC 25 |
| Finished | Feb 09 06:15:31 AM UTC 25 |
| Peak memory | 287680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277063181 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.4277063181 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.2736845720 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 74904000 ps |
| CPU time | 41.2 seconds |
| Started | Feb 09 06:14:48 AM UTC 25 |
| Finished | Feb 09 06:15:30 AM UTC 25 |
| Peak memory | 285880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736 845720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2736845720 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2859315034 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2226206400 ps |
| CPU time | 70.15 seconds |
| Started | Feb 09 06:14:57 AM UTC 25 |
| Finished | Feb 09 06:16:09 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859315034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2859315034 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.227578640 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 70223800 ps |
| CPU time | 257.86 seconds |
| Started | Feb 09 06:14:26 AM UTC 25 |
| Finished | Feb 09 06:18:48 AM UTC 25 |
| Peak memory | 287780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227578640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.227578640 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.941362144 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 251432900 ps |
| CPU time | 20.11 seconds |
| Started | Feb 09 06:15:33 AM UTC 25 |
| Finished | Feb 09 06:15:55 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941362144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.941362144 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.3766571886 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 25631700 ps |
| CPU time | 31.59 seconds |
| Started | Feb 09 06:15:32 AM UTC 25 |
| Finished | Feb 09 06:16:05 AM UTC 25 |
| Peak memory | 284852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766571886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.3766571886 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.1943043195 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 13069200 ps |
| CPU time | 36.84 seconds |
| Started | Feb 09 06:15:29 AM UTC 25 |
| Finished | Feb 09 06:16:08 AM UTC 25 |
| Peak memory | 285508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 43043195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.1943043195 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.3896632602 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2045684000 ps |
| CPU time | 64.03 seconds |
| Started | Feb 09 06:15:04 AM UTC 25 |
| Finished | Feb 09 06:16:11 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896632602 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.3896632602 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.702400285 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 701426300 ps |
| CPU time | 131.6 seconds |
| Started | Feb 09 06:15:09 AM UTC 25 |
| Finished | Feb 09 06:17:23 AM UTC 25 |
| Peak memory | 301956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702400285 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.702400285 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.4036415056 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 47909033000 ps |
| CPU time | 291.74 seconds |
| Started | Feb 09 06:15:12 AM UTC 25 |
| Finished | Feb 09 06:20:07 AM UTC 25 |
| Peak memory | 302052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4036415056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_in tr_rd_slow_flash.4036415056 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.2206007466 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 20386200 ps |
| CPU time | 27.4 seconds |
| Started | Feb 09 06:15:14 AM UTC 25 |
| Finished | Feb 09 06:15:43 AM UTC 25 |
| Peak memory | 275180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206007466 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.2206007466 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.1195692465 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 81254400 ps |
| CPU time | 49.12 seconds |
| Started | Feb 09 06:15:26 AM UTC 25 |
| Finished | Feb 09 06:16:17 AM UTC 25 |
| Peak memory | 287964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195692465 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.1195692465 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.1896017446 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 69432600 ps |
| CPU time | 34.58 seconds |
| Started | Feb 09 06:15:28 AM UTC 25 |
| Finished | Feb 09 06:16:04 AM UTC 25 |
| Peak memory | 285624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896 017446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1896017446 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.2943864869 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1934728600 ps |
| CPU time | 291.3 seconds |
| Started | Feb 09 06:15:03 AM UTC 25 |
| Finished | Feb 09 06:19:59 AM UTC 25 |
| Peak memory | 291676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943864869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2943864869 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.4019023237 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 186479400 ps |
| CPU time | 18.11 seconds |
| Started | Feb 09 06:16:05 AM UTC 25 |
| Finished | Feb 09 06:16:25 AM UTC 25 |
| Peak memory | 269080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019023237 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.4019023237 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.2251991612 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 51769100 ps |
| CPU time | 27.27 seconds |
| Started | Feb 09 06:16:00 AM UTC 25 |
| Finished | Feb 09 06:16:29 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251991612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2251991612 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.1375763461 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 15546100 ps |
| CPU time | 23.08 seconds |
| Started | Feb 09 06:15:56 AM UTC 25 |
| Finished | Feb 09 06:16:20 AM UTC 25 |
| Peak memory | 285768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 75763461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.1375763461 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.2090597679 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3396750400 ps |
| CPU time | 206.88 seconds |
| Started | Feb 09 06:15:49 AM UTC 25 |
| Finished | Feb 09 06:19:19 AM UTC 25 |
| Peak memory | 301924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090597679 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.2090597679 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1261517778 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 13646616000 ps |
| CPU time | 241.12 seconds |
| Started | Feb 09 06:15:50 AM UTC 25 |
| Finished | Feb 09 06:19:54 AM UTC 25 |
| Peak memory | 303868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1261517778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_in tr_rd_slow_flash.1261517778 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.1049320 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 546180400 ps |
| CPU time | 170.66 seconds |
| Started | Feb 09 06:15:44 AM UTC 25 |
| Finished | Feb 09 06:18:37 AM UTC 25 |
| Peak memory | 271324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049320 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.1049320 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.2850228403 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 38547000 ps |
| CPU time | 19.7 seconds |
| Started | Feb 09 06:15:53 AM UTC 25 |
| Finished | Feb 09 06:16:14 AM UTC 25 |
| Peak memory | 275568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850228403 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.2850228403 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.189909815 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 35191300 ps |
| CPU time | 56.24 seconds |
| Started | Feb 09 06:15:55 AM UTC 25 |
| Finished | Feb 09 06:16:53 AM UTC 25 |
| Peak memory | 285628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189909815 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.189909815 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.2650052405 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 69015400 ps |
| CPU time | 56.14 seconds |
| Started | Feb 09 06:15:55 AM UTC 25 |
| Finished | Feb 09 06:16:53 AM UTC 25 |
| Peak memory | 287636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650 052405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2650052405 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.4145256931 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 419366900 ps |
| CPU time | 82.34 seconds |
| Started | Feb 09 06:15:56 AM UTC 25 |
| Finished | Feb 09 06:17:21 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145256931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.4145256931 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.4266005390 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 34983600 ps |
| CPU time | 152 seconds |
| Started | Feb 09 06:15:33 AM UTC 25 |
| Finished | Feb 09 06:18:08 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266005390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.4266005390 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.491349216 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 40306900 ps |
| CPU time | 26.01 seconds |
| Started | Feb 09 05:24:08 AM UTC 25 |
| Finished | Feb 09 05:24:35 AM UTC 25 |
| Peak memory | 275468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491349216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.491349216 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2393495887 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 34114400 ps |
| CPU time | 24.86 seconds |
| Started | Feb 09 05:23:55 AM UTC 25 |
| Finished | Feb 09 05:24:21 AM UTC 25 |
| Peak memory | 275192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393495887 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.2393495887 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.3525822580 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 65726400 ps |
| CPU time | 18.04 seconds |
| Started | Feb 09 05:23:15 AM UTC 25 |
| Finished | Feb 09 05:23:35 AM UTC 25 |
| Peak memory | 295032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525822580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3525822580 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.3313951015 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 796613200 ps |
| CPU time | 221.34 seconds |
| Started | Feb 09 05:21:25 AM UTC 25 |
| Finished | Feb 09 05:25:10 AM UTC 25 |
| Peak memory | 291720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 + otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3313951015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ derr_detect.3313951015 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2018418594 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 11561000 ps |
| CPU time | 41.91 seconds |
| Started | Feb 09 05:22:37 AM UTC 25 |
| Finished | Feb 09 05:23:21 AM UTC 25 |
| Peak memory | 285836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 18418594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.2018418594 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2062079959 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5567943800 ps |
| CPU time | 413.39 seconds |
| Started | Feb 09 05:17:39 AM UTC 25 |
| Finished | Feb 09 05:24:37 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062079959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2062079959 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1280216722 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3036280900 ps |
| CPU time | 3080.1 seconds |
| Started | Feb 09 05:18:49 AM UTC 25 |
| Finished | Feb 09 06:10:41 AM UTC 25 |
| Peak memory | 273112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280216722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1280216722 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.1370877644 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2043493600 ps |
| CPU time | 3453.16 seconds |
| Started | Feb 09 05:18:26 AM UTC 25 |
| Finished | Feb 09 06:16:35 AM UTC 25 |
| Peak memory | 278028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370877644 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.1370877644 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.2812290622 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2098614600 ps |
| CPU time | 1060.38 seconds |
| Started | Feb 09 05:18:48 AM UTC 25 |
| Finished | Feb 09 05:36:41 AM UTC 25 |
| Peak memory | 285672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812290622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2812290622 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.615045612 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1442349600 ps |
| CPU time | 47.49 seconds |
| Started | Feb 09 05:18:15 AM UTC 25 |
| Finished | Feb 09 05:19:04 AM UTC 25 |
| Peak memory | 273120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615045612 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.615045612 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3366741013 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1296364400 ps |
| CPU time | 51.2 seconds |
| Started | Feb 09 05:23:21 AM UTC 25 |
| Finished | Feb 09 05:24:14 AM UTC 25 |
| Peak memory | 273192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366741013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fs_sup.3366741013 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.1527964291 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 91890875500 ps |
| CPU time | 2480.96 seconds |
| Started | Feb 09 05:18:20 AM UTC 25 |
| Finished | Feb 09 06:00:08 AM UTC 25 |
| Peak memory | 275268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527964291 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.1527964291 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.1270394428 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 69012400 ps |
| CPU time | 237.62 seconds |
| Started | Feb 09 05:17:36 AM UTC 25 |
| Finished | Feb 09 05:21:38 AM UTC 25 |
| Peak memory | 275152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270394428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1270394428 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3672348766 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 10042961500 ps |
| CPU time | 78.85 seconds |
| Started | Feb 09 05:24:06 AM UTC 25 |
| Finished | Feb 09 05:25:27 AM UTC 25 |
| Peak memory | 275476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3672348766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.flash_ctrl_hw_prog_rma_wipe_err.3672348766 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3314952708 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 38644000 ps |
| CPU time | 16.25 seconds |
| Started | Feb 09 05:24:05 AM UTC 25 |
| Finished | Feb 09 05:24:22 AM UTC 25 |
| Peak memory | 275260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 14952708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_s eed_err.3314952708 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.833685555 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 260238299100 ps |
| CPU time | 939.31 seconds |
| Started | Feb 09 05:17:43 AM UTC 25 |
| Finished | Feb 09 05:33:33 AM UTC 25 |
| Peak memory | 275328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833685555 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.833685555 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1223730788 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 640528300 ps |
| CPU time | 40.13 seconds |
| Started | Feb 09 05:17:37 AM UTC 25 |
| Finished | Feb 09 05:18:19 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223730788 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.1223730788 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.1081508435 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 8995287400 ps |
| CPU time | 520.15 seconds |
| Started | Feb 09 05:21:35 AM UTC 25 |
| Finished | Feb 09 05:30:21 AM UTC 25 |
| Peak memory | 340872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081508 435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integrity.1081508435 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2631584054 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 23172717000 ps |
| CPU time | 179.4 seconds |
| Started | Feb 09 05:22:07 AM UTC 25 |
| Finished | Feb 09 05:25:09 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2631584054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_int r_rd_slow_flash.2631584054 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.2529592912 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4086787200 ps |
| CPU time | 94.84 seconds |
| Started | Feb 09 05:21:57 AM UTC 25 |
| Finished | Feb 09 05:23:34 AM UTC 25 |
| Peak memory | 275484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529592912 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.2529592912 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.896119338 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 84235254800 ps |
| CPU time | 199.22 seconds |
| Started | Feb 09 05:22:16 AM UTC 25 |
| Finished | Feb 09 05:25:38 AM UTC 25 |
| Peak memory | 271100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=896119338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.flash_ctrl_intr_wr_slow_flash.896119338 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.1451112694 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2177860100 ps |
| CPU time | 111 seconds |
| Started | Feb 09 05:19:04 AM UTC 25 |
| Finished | Feb 09 05:20:58 AM UTC 25 |
| Peak memory | 271000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451112694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1451112694 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2331409215 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 177183500 ps |
| CPU time | 25.49 seconds |
| Started | Feb 09 05:24:04 AM UTC 25 |
| Finished | Feb 09 05:24:31 AM UTC 25 |
| Peak memory | 271196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 31409215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.2331409215 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.1330664032 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 85590721600 ps |
| CPU time | 660.65 seconds |
| Started | Feb 09 05:18:03 AM UTC 25 |
| Finished | Feb 09 05:29:12 AM UTC 25 |
| Peak memory | 283700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1330664032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.f lash_ctrl_mp_regions.1330664032 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2344531360 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 163757500 ps |
| CPU time | 187.94 seconds |
| Started | Feb 09 05:17:59 AM UTC 25 |
| Finished | Feb 09 05:21:10 AM UTC 25 |
| Peak memory | 271316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344531360 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.2344531360 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1008164663 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1310000600 ps |
| CPU time | 221.01 seconds |
| Started | Feb 09 05:21:29 AM UTC 25 |
| Finished | Feb 09 05:25:13 AM UTC 25 |
| Peak memory | 291744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_ pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1008164663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.f lash_ctrl_oversize_error.1008164663 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.3097655909 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1463296200 ps |
| CPU time | 388.36 seconds |
| Started | Feb 09 05:17:37 AM UTC 25 |
| Finished | Feb 09 05:24:10 AM UTC 25 |
| Peak memory | 275420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097655909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3097655909 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.1889707478 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 15581500 ps |
| CPU time | 27.59 seconds |
| Started | Feb 09 05:23:35 AM UTC 25 |
| Finished | Feb 09 05:24:03 AM UTC 25 |
| Peak memory | 275460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass _alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1889707478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1889707478 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.2009141686 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2245760600 ps |
| CPU time | 175.63 seconds |
| Started | Feb 09 05:22:19 AM UTC 25 |
| Finished | Feb 09 05:25:17 AM UTC 25 |
| Peak memory | 271412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009141686 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.2009141686 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.4089757295 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 750972800 ps |
| CPU time | 288.53 seconds |
| Started | Feb 09 05:17:32 AM UTC 25 |
| Finished | Feb 09 05:22:24 AM UTC 25 |
| Peak memory | 289496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089757295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.4089757295 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.4127447548 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 735524600 ps |
| CPU time | 170.03 seconds |
| Started | Feb 09 05:17:36 AM UTC 25 |
| Finished | Feb 09 05:20:29 AM UTC 25 |
| Peak memory | 273180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127447548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.4127447548 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.2045150426 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 73714200 ps |
| CPU time | 66.62 seconds |
| Started | Feb 09 05:22:25 AM UTC 25 |
| Finished | Feb 09 05:23:33 AM UTC 25 |
| Peak memory | 285588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045150426 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.2045150426 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.1439505612 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 19954100 ps |
| CPU time | 33.22 seconds |
| Started | Feb 09 05:20:59 AM UTC 25 |
| Finished | Feb 09 05:21:34 AM UTC 25 |
| Peak memory | 275588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439505 612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep _derr.1439505612 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.610853732 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 204803700 ps |
| CPU time | 42.36 seconds |
| Started | Feb 09 05:19:46 AM UTC 25 |
| Finished | Feb 09 05:20:30 AM UTC 25 |
| Peak memory | 275296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610853732 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.610853732 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.707979245 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 545367800 ps |
| CPU time | 125.84 seconds |
| Started | Feb 09 05:19:17 AM UTC 25 |
| Finished | Feb 09 05:21:25 AM UTC 25 |
| Peak memory | 292008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7079792 45 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.707979245 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.856618053 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 619012300 ps |
| CPU time | 160.78 seconds |
| Started | Feb 09 05:21:10 AM UTC 25 |
| Finished | Feb 09 05:23:54 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=856618053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_ro_derr.856618053 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3458033006 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 747690200 ps |
| CPU time | 178.97 seconds |
| Started | Feb 09 05:19:54 AM UTC 25 |
| Finished | Feb 09 05:22:56 AM UTC 25 |
| Peak memory | 291708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3458033006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3458033006 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.501431545 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 6899367500 ps |
| CPU time | 475.5 seconds |
| Started | Feb 09 05:19:33 AM UTC 25 |
| Finished | Feb 09 05:27:34 AM UTC 25 |
| Peak memory | 330956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501431545 -assert nopos tproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.501431545 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.2436246015 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5047588200 ps |
| CPU time | 235.91 seconds |
| Started | Feb 09 05:21:21 AM UTC 25 |
| Finished | Feb 09 05:25:21 AM UTC 25 |
| Peak memory | 295840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2436246015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ ctrl_rw_derr.2436246015 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.2102364376 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 57205600 ps |
| CPU time | 48.96 seconds |
| Started | Feb 09 05:22:19 AM UTC 25 |
| Finished | Feb 09 05:23:09 AM UTC 25 |
| Peak memory | 285632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102364376 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.2102364376 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.3413420589 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 36878600 ps |
| CPU time | 49.41 seconds |
| Started | Feb 09 05:22:24 AM UTC 25 |
| Finished | Feb 09 05:23:15 AM UTC 25 |
| Peak memory | 287892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413 420589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3413420589 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.738035811 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5098792400 ps |
| CPU time | 163.66 seconds |
| Started | Feb 09 05:20:22 AM UTC 25 |
| Finished | Feb 09 05:23:08 AM UTC 25 |
| Peak memory | 291720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738035811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.738035811 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.4128791507 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6042094400 ps |
| CPU time | 116.33 seconds |
| Started | Feb 09 05:23:09 AM UTC 25 |
| Finished | Feb 09 05:25:08 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128791507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.4128791507 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.863383095 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 992481700 ps |
| CPU time | 82.68 seconds |
| Started | Feb 09 05:20:31 AM UTC 25 |
| Finished | Feb 09 05:21:56 AM UTC 25 |
| Peak memory | 275332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863383095 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr_address.863383095 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.81645976 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1638849800 ps |
| CPU time | 102.77 seconds |
| Started | Feb 09 05:20:30 AM UTC 25 |
| Finished | Feb 09 05:22:15 AM UTC 25 |
| Peak memory | 285600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81645976 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr_counter.81645976 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1536212154 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 32677900 ps |
| CPU time | 146.03 seconds |
| Started | Feb 09 05:17:24 AM UTC 25 |
| Finished | Feb 09 05:19:53 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536212154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1536212154 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1406661914 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 19494000 ps |
| CPU time | 44.93 seconds |
| Started | Feb 09 05:17:27 AM UTC 25 |
| Finished | Feb 09 05:18:14 AM UTC 25 |
| Peak memory | 271144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406661914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1406661914 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1408041478 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 680979600 ps |
| CPU time | 2249.62 seconds |
| Started | Feb 09 05:23:10 AM UTC 25 |
| Finished | Feb 09 06:01:03 AM UTC 25 |
| Peak memory | 299948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408041478 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.1408041478 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3653326973 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 96415300 ps |
| CPU time | 51.69 seconds |
| Started | Feb 09 05:17:32 AM UTC 25 |
| Finished | Feb 09 05:18:25 AM UTC 25 |
| Peak memory | 273064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653326973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3653326973 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3985821964 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1668279900 ps |
| CPU time | 125.42 seconds |
| Started | Feb 09 05:19:13 AM UTC 25 |
| Finished | Feb 09 05:21:20 AM UTC 25 |
| Peak memory | 275540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985821964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.3985821964 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.481543489 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 70073800 ps |
| CPU time | 25.86 seconds |
| Started | Feb 09 06:16:25 AM UTC 25 |
| Finished | Feb 09 06:16:53 AM UTC 25 |
| Peak memory | 269076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481543489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.481543489 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.155399039 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 30295400 ps |
| CPU time | 26.27 seconds |
| Started | Feb 09 06:16:21 AM UTC 25 |
| Finished | Feb 09 06:16:49 AM UTC 25 |
| Peak memory | 284856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155399039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.155399039 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.4086185382 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 29216200 ps |
| CPU time | 40.43 seconds |
| Started | Feb 09 06:16:18 AM UTC 25 |
| Finished | Feb 09 06:17:00 AM UTC 25 |
| Peak memory | 285768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 86185382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.4086185382 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.3220229619 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2639345100 ps |
| CPU time | 97.97 seconds |
| Started | Feb 09 06:16:09 AM UTC 25 |
| Finished | Feb 09 06:17:49 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220229619 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.3220229619 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.2747468226 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 640372400 ps |
| CPU time | 149.64 seconds |
| Started | Feb 09 06:16:12 AM UTC 25 |
| Finished | Feb 09 06:18:44 AM UTC 25 |
| Peak memory | 306084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747468226 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.2747468226 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1221558763 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 12060747400 ps |
| CPU time | 143.09 seconds |
| Started | Feb 09 06:16:15 AM UTC 25 |
| Finished | Feb 09 06:18:41 AM UTC 25 |
| Peak memory | 306020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1221558763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_in tr_rd_slow_flash.1221558763 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.722280048 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 132237100 ps |
| CPU time | 191.05 seconds |
| Started | Feb 09 06:16:10 AM UTC 25 |
| Finished | Feb 09 06:19:24 AM UTC 25 |
| Peak memory | 270980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722280048 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.722280048 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.3063303729 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 195590800 ps |
| CPU time | 38.57 seconds |
| Started | Feb 09 06:16:15 AM UTC 25 |
| Finished | Feb 09 06:16:55 AM UTC 25 |
| Peak memory | 283544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063303729 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.3063303729 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.2580522555 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 115264300 ps |
| CPU time | 46.78 seconds |
| Started | Feb 09 06:16:15 AM UTC 25 |
| Finished | Feb 09 06:17:03 AM UTC 25 |
| Peak memory | 285620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580 522555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2580522555 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.362842218 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 608580200 ps |
| CPU time | 98.4 seconds |
| Started | Feb 09 06:16:20 AM UTC 25 |
| Finished | Feb 09 06:18:01 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362842218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.362842218 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.3627901637 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8450320100 ps |
| CPU time | 178.19 seconds |
| Started | Feb 09 06:16:06 AM UTC 25 |
| Finished | Feb 09 06:19:07 AM UTC 25 |
| Peak memory | 291792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627901637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3627901637 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.813412429 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 39582700 ps |
| CPU time | 16.53 seconds |
| Started | Feb 09 06:16:56 AM UTC 25 |
| Finished | Feb 09 06:17:14 AM UTC 25 |
| Peak memory | 275216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813412429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.813412429 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.837629011 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 43839800 ps |
| CPU time | 20.76 seconds |
| Started | Feb 09 06:16:56 AM UTC 25 |
| Finished | Feb 09 06:17:18 AM UTC 25 |
| Peak memory | 295292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837629011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.837629011 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.3973656510 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 18331400 ps |
| CPU time | 26.59 seconds |
| Started | Feb 09 06:16:54 AM UTC 25 |
| Finished | Feb 09 06:17:22 AM UTC 25 |
| Peak memory | 285800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 73656510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.3973656510 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.3710317825 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8239476600 ps |
| CPU time | 153.8 seconds |
| Started | Feb 09 06:16:30 AM UTC 25 |
| Finished | Feb 09 06:19:06 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710317825 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.3710317825 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.2025352458 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1360414300 ps |
| CPU time | 161.56 seconds |
| Started | Feb 09 06:16:39 AM UTC 25 |
| Finished | Feb 09 06:19:23 AM UTC 25 |
| Peak memory | 306080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025352458 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.2025352458 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.201775404 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 19262775800 ps |
| CPU time | 299 seconds |
| Started | Feb 09 06:16:47 AM UTC 25 |
| Finished | Feb 09 06:21:50 AM UTC 25 |
| Peak memory | 303936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=201775404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_int r_rd_slow_flash.201775404 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.3847061267 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 36065200 ps |
| CPU time | 229.8 seconds |
| Started | Feb 09 06:16:36 AM UTC 25 |
| Finished | Feb 09 06:20:29 AM UTC 25 |
| Peak memory | 271164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847061267 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.3847061267 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.2138657180 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 211291700 ps |
| CPU time | 51.97 seconds |
| Started | Feb 09 06:16:50 AM UTC 25 |
| Finished | Feb 09 06:17:44 AM UTC 25 |
| Peak memory | 287644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138657180 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.2138657180 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.172966794 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 117347700 ps |
| CPU time | 47.45 seconds |
| Started | Feb 09 06:16:53 AM UTC 25 |
| Finished | Feb 09 06:17:42 AM UTC 25 |
| Peak memory | 277396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729 66794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.172966794 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.3609282262 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 11850003800 ps |
| CPU time | 80.82 seconds |
| Started | Feb 09 06:16:54 AM UTC 25 |
| Finished | Feb 09 06:18:17 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609282262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3609282262 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.2112279931 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 28685200 ps |
| CPU time | 75.87 seconds |
| Started | Feb 09 06:16:26 AM UTC 25 |
| Finished | Feb 09 06:17:44 AM UTC 25 |
| Peak memory | 283348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112279931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2112279931 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.3006384283 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 50686800 ps |
| CPU time | 25.82 seconds |
| Started | Feb 09 06:17:24 AM UTC 25 |
| Finished | Feb 09 06:17:51 AM UTC 25 |
| Peak memory | 269068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006384283 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.3006384283 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1042047328 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 24028700 ps |
| CPU time | 14.99 seconds |
| Started | Feb 09 06:17:22 AM UTC 25 |
| Finished | Feb 09 06:17:39 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042047328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1042047328 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.3669646286 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 36018800 ps |
| CPU time | 40.29 seconds |
| Started | Feb 09 06:17:21 AM UTC 25 |
| Finished | Feb 09 06:18:03 AM UTC 25 |
| Peak memory | 285448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 69646286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.3669646286 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.3114420205 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 29451524900 ps |
| CPU time | 179.09 seconds |
| Started | Feb 09 06:17:01 AM UTC 25 |
| Finished | Feb 09 06:20:03 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114420205 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.3114420205 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.2331413613 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 4986568000 ps |
| CPU time | 133.89 seconds |
| Started | Feb 09 06:17:07 AM UTC 25 |
| Finished | Feb 09 06:19:23 AM UTC 25 |
| Peak memory | 293732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331413613 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.2331413613 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1291852421 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 21722174000 ps |
| CPU time | 281.54 seconds |
| Started | Feb 09 06:17:10 AM UTC 25 |
| Finished | Feb 09 06:21:56 AM UTC 25 |
| Peak memory | 301860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1291852421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_in tr_rd_slow_flash.1291852421 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.85657453 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 308111500 ps |
| CPU time | 181.53 seconds |
| Started | Feb 09 06:17:05 AM UTC 25 |
| Finished | Feb 09 06:20:09 AM UTC 25 |
| Peak memory | 275412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85657453 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.85657453 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.1182871175 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 31750600 ps |
| CPU time | 57.26 seconds |
| Started | Feb 09 06:17:15 AM UTC 25 |
| Finished | Feb 09 06:18:14 AM UTC 25 |
| Peak memory | 287900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182871175 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.1182871175 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2130308084 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 28568600 ps |
| CPU time | 33.37 seconds |
| Started | Feb 09 06:17:19 AM UTC 25 |
| Finished | Feb 09 06:17:54 AM UTC 25 |
| Peak memory | 285620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130 308084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.2130308084 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.1976108899 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1446729000 ps |
| CPU time | 62.73 seconds |
| Started | Feb 09 06:17:22 AM UTC 25 |
| Finished | Feb 09 06:18:27 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976108899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1976108899 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.1643379968 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 244745900 ps |
| CPU time | 264.68 seconds |
| Started | Feb 09 06:17:01 AM UTC 25 |
| Finished | Feb 09 06:21:29 AM UTC 25 |
| Peak memory | 291804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643379968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1643379968 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.203039675 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 33314900 ps |
| CPU time | 16.17 seconds |
| Started | Feb 09 06:17:49 AM UTC 25 |
| Finished | Feb 09 06:18:06 AM UTC 25 |
| Peak memory | 275476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203039675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.203039675 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.4059951656 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 46266000 ps |
| CPU time | 23.88 seconds |
| Started | Feb 09 06:17:47 AM UTC 25 |
| Finished | Feb 09 06:18:13 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059951656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.4059951656 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.378588060 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 31281300 ps |
| CPU time | 44.07 seconds |
| Started | Feb 09 06:17:44 AM UTC 25 |
| Finished | Feb 09 06:18:30 AM UTC 25 |
| Peak memory | 285836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 8588060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.378588060 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.1879049457 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1731286500 ps |
| CPU time | 112.02 seconds |
| Started | Feb 09 06:17:25 AM UTC 25 |
| Finished | Feb 09 06:19:19 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879049457 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.1879049457 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.3997299838 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 1195442800 ps |
| CPU time | 130 seconds |
| Started | Feb 09 06:17:27 AM UTC 25 |
| Finished | Feb 09 06:19:39 AM UTC 25 |
| Peak memory | 306084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997299838 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.3997299838 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2241986770 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 23783765700 ps |
| CPU time | 152.71 seconds |
| Started | Feb 09 06:17:33 AM UTC 25 |
| Finished | Feb 09 06:20:08 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2241986770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_in tr_rd_slow_flash.2241986770 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.479272704 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 78184800 ps |
| CPU time | 180.05 seconds |
| Started | Feb 09 06:17:26 AM UTC 25 |
| Finished | Feb 09 06:20:29 AM UTC 25 |
| Peak memory | 275076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479272704 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.479272704 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2283008861 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 75191900 ps |
| CPU time | 37.01 seconds |
| Started | Feb 09 06:17:39 AM UTC 25 |
| Finished | Feb 09 06:18:18 AM UTC 25 |
| Peak memory | 287928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283008861 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.2283008861 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.2698623031 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 30085300 ps |
| CPU time | 37.66 seconds |
| Started | Feb 09 06:17:43 AM UTC 25 |
| Finished | Feb 09 06:18:22 AM UTC 25 |
| Peak memory | 281492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698 623031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2698623031 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1005664350 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1545628000 ps |
| CPU time | 73.56 seconds |
| Started | Feb 09 06:17:45 AM UTC 25 |
| Finished | Feb 09 06:19:01 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005664350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1005664350 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.3829714726 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 44322400 ps |
| CPU time | 144.67 seconds |
| Started | Feb 09 06:17:24 AM UTC 25 |
| Finished | Feb 09 06:19:51 AM UTC 25 |
| Peak memory | 287432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829714726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3829714726 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.3906295639 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 104685800 ps |
| CPU time | 23.16 seconds |
| Started | Feb 09 06:18:18 AM UTC 25 |
| Finished | Feb 09 06:18:43 AM UTC 25 |
| Peak memory | 269084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906295639 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.3906295639 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.1830091063 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 74522900 ps |
| CPU time | 29.81 seconds |
| Started | Feb 09 06:18:15 AM UTC 25 |
| Finished | Feb 09 06:18:46 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830091063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1830091063 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.1543429225 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 13784500 ps |
| CPU time | 35.86 seconds |
| Started | Feb 09 06:18:10 AM UTC 25 |
| Finished | Feb 09 06:18:47 AM UTC 25 |
| Peak memory | 285544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 43429225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.1543429225 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.3350985716 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 3055610900 ps |
| CPU time | 108.27 seconds |
| Started | Feb 09 06:17:51 AM UTC 25 |
| Finished | Feb 09 06:19:41 AM UTC 25 |
| Peak memory | 270952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350985716 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.3350985716 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.2018428250 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 1124210100 ps |
| CPU time | 207.7 seconds |
| Started | Feb 09 06:17:55 AM UTC 25 |
| Finished | Feb 09 06:21:26 AM UTC 25 |
| Peak memory | 304004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018428250 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.2018428250 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3514587734 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 35109674300 ps |
| CPU time | 333.68 seconds |
| Started | Feb 09 06:18:02 AM UTC 25 |
| Finished | Feb 09 06:23:41 AM UTC 25 |
| Peak memory | 301860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3514587734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_in tr_rd_slow_flash.3514587734 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.1017953422 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 72835500 ps |
| CPU time | 165.01 seconds |
| Started | Feb 09 06:17:52 AM UTC 25 |
| Finished | Feb 09 06:20:40 AM UTC 25 |
| Peak memory | 271168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017953422 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.1017953422 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.3006361797 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 100189000 ps |
| CPU time | 50.01 seconds |
| Started | Feb 09 06:18:04 AM UTC 25 |
| Finished | Feb 09 06:18:56 AM UTC 25 |
| Peak memory | 287672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006361797 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.3006361797 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.2126806313 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 87173300 ps |
| CPU time | 54.77 seconds |
| Started | Feb 09 06:18:06 AM UTC 25 |
| Finished | Feb 09 06:19:03 AM UTC 25 |
| Peak memory | 285620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126 806313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2126806313 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.2609306776 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 25761200 ps |
| CPU time | 94.37 seconds |
| Started | Feb 09 06:17:50 AM UTC 25 |
| Finished | Feb 09 06:19:26 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609306776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2609306776 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.2964408691 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 45916400 ps |
| CPU time | 26.62 seconds |
| Started | Feb 09 06:18:45 AM UTC 25 |
| Finished | Feb 09 06:19:13 AM UTC 25 |
| Peak memory | 269324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964408691 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.2964408691 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.2984294650 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 25870700 ps |
| CPU time | 23.18 seconds |
| Started | Feb 09 06:18:43 AM UTC 25 |
| Finished | Feb 09 06:19:08 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984294650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2984294650 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.990293072 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 15024200 ps |
| CPU time | 36.82 seconds |
| Started | Feb 09 06:18:39 AM UTC 25 |
| Finished | Feb 09 06:19:18 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99 0293072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.990293072 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.1169589258 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4745478400 ps |
| CPU time | 78.72 seconds |
| Started | Feb 09 06:18:21 AM UTC 25 |
| Finished | Feb 09 06:19:42 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169589258 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.1169589258 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.179451159 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5142502000 ps |
| CPU time | 179.36 seconds |
| Started | Feb 09 06:18:27 AM UTC 25 |
| Finished | Feb 09 06:21:30 AM UTC 25 |
| Peak memory | 304000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179451159 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.179451159 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1699336357 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 51736470700 ps |
| CPU time | 250.94 seconds |
| Started | Feb 09 06:18:31 AM UTC 25 |
| Finished | Feb 09 06:22:45 AM UTC 25 |
| Peak memory | 303908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1699336357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_in tr_rd_slow_flash.1699336357 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.4189511142 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 39990200 ps |
| CPU time | 132.43 seconds |
| Started | Feb 09 06:18:23 AM UTC 25 |
| Finished | Feb 09 06:20:38 AM UTC 25 |
| Peak memory | 271232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189511142 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.4189511142 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.1087990313 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 45016500 ps |
| CPU time | 51.17 seconds |
| Started | Feb 09 06:18:31 AM UTC 25 |
| Finished | Feb 09 06:19:24 AM UTC 25 |
| Peak memory | 285756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087990313 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.1087990313 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.2701204541 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 29666200 ps |
| CPU time | 48.53 seconds |
| Started | Feb 09 06:18:38 AM UTC 25 |
| Finished | Feb 09 06:19:28 AM UTC 25 |
| Peak memory | 277396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701 204541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.2701204541 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.1251369316 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 135729100 ps |
| CPU time | 101.07 seconds |
| Started | Feb 09 06:18:19 AM UTC 25 |
| Finished | Feb 09 06:20:02 AM UTC 25 |
| Peak memory | 277416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251369316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1251369316 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.4046416546 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 50939400 ps |
| CPU time | 24.84 seconds |
| Started | Feb 09 06:19:18 AM UTC 25 |
| Finished | Feb 09 06:19:45 AM UTC 25 |
| Peak memory | 275212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046416546 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.4046416546 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.2545233538 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 23425300 ps |
| CPU time | 25.95 seconds |
| Started | Feb 09 06:19:14 AM UTC 25 |
| Finished | Feb 09 06:19:42 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545233538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2545233538 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.4192555457 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 10085400 ps |
| CPU time | 31.92 seconds |
| Started | Feb 09 06:19:08 AM UTC 25 |
| Finished | Feb 09 06:19:42 AM UTC 25 |
| Peak memory | 285764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 92555457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.4192555457 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.2562677279 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2112840400 ps |
| CPU time | 87.53 seconds |
| Started | Feb 09 06:18:48 AM UTC 25 |
| Finished | Feb 09 06:20:18 AM UTC 25 |
| Peak memory | 273000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562677279 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.2562677279 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.1378278982 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 678664000 ps |
| CPU time | 124.22 seconds |
| Started | Feb 09 06:18:57 AM UTC 25 |
| Finished | Feb 09 06:21:03 AM UTC 25 |
| Peak memory | 306080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378278982 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.1378278982 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2109568033 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 51622807400 ps |
| CPU time | 262.88 seconds |
| Started | Feb 09 06:19:02 AM UTC 25 |
| Finished | Feb 09 06:23:28 AM UTC 25 |
| Peak memory | 303868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2109568033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_in tr_rd_slow_flash.2109568033 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.2193330455 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 219992600 ps |
| CPU time | 162.68 seconds |
| Started | Feb 09 06:18:49 AM UTC 25 |
| Finished | Feb 09 06:21:34 AM UTC 25 |
| Peak memory | 270972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193330455 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.2193330455 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.3837464950 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 195104500 ps |
| CPU time | 41.72 seconds |
| Started | Feb 09 06:19:04 AM UTC 25 |
| Finished | Feb 09 06:19:47 AM UTC 25 |
| Peak memory | 283548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837464950 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.3837464950 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.3958739013 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 73384400 ps |
| CPU time | 36.11 seconds |
| Started | Feb 09 06:19:07 AM UTC 25 |
| Finished | Feb 09 06:19:45 AM UTC 25 |
| Peak memory | 285884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958 739013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3958739013 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.2067670257 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 35617500 ps |
| CPU time | 214.4 seconds |
| Started | Feb 09 06:18:46 AM UTC 25 |
| Finished | Feb 09 06:22:24 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067670257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2067670257 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.2936992036 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 128301000 ps |
| CPU time | 27.64 seconds |
| Started | Feb 09 06:19:41 AM UTC 25 |
| Finished | Feb 09 06:20:10 AM UTC 25 |
| Peak memory | 269064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936992036 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.2936992036 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.431776487 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 14043000 ps |
| CPU time | 25.5 seconds |
| Started | Feb 09 06:19:37 AM UTC 25 |
| Finished | Feb 09 06:20:04 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431776487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.431776487 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.1958482099 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 31930400 ps |
| CPU time | 25.38 seconds |
| Started | Feb 09 06:19:29 AM UTC 25 |
| Finished | Feb 09 06:19:56 AM UTC 25 |
| Peak memory | 285504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 58482099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.1958482099 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.1442188978 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 1042544900 ps |
| CPU time | 62.54 seconds |
| Started | Feb 09 06:19:20 AM UTC 25 |
| Finished | Feb 09 06:20:24 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442188978 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.1442188978 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.3586674360 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 1687364000 ps |
| CPU time | 192.41 seconds |
| Started | Feb 09 06:19:24 AM UTC 25 |
| Finished | Feb 09 06:22:39 AM UTC 25 |
| Peak memory | 293728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586674360 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.3586674360 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.226623476 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 12981541000 ps |
| CPU time | 150.66 seconds |
| Started | Feb 09 06:19:25 AM UTC 25 |
| Finished | Feb 09 06:21:58 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=226623476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_int r_rd_slow_flash.226623476 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.1486980154 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 42258500 ps |
| CPU time | 156.55 seconds |
| Started | Feb 09 06:19:24 AM UTC 25 |
| Finished | Feb 09 06:22:03 AM UTC 25 |
| Peak memory | 270972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486980154 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.1486980154 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.913697755 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 78744400 ps |
| CPU time | 51.89 seconds |
| Started | Feb 09 06:19:25 AM UTC 25 |
| Finished | Feb 09 06:20:19 AM UTC 25 |
| Peak memory | 287632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913697755 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.913697755 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.2880515271 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 40151900 ps |
| CPU time | 44.9 seconds |
| Started | Feb 09 06:19:27 AM UTC 25 |
| Finished | Feb 09 06:20:14 AM UTC 25 |
| Peak memory | 277404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880 515271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2880515271 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.1502754529 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 527505300 ps |
| CPU time | 73.41 seconds |
| Started | Feb 09 06:19:30 AM UTC 25 |
| Finished | Feb 09 06:20:46 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502754529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1502754529 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.428563487 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 64431500 ps |
| CPU time | 183.51 seconds |
| Started | Feb 09 06:19:20 AM UTC 25 |
| Finished | Feb 09 06:22:26 AM UTC 25 |
| Peak memory | 287464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428563487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.428563487 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.2620758543 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 53985900 ps |
| CPU time | 18.73 seconds |
| Started | Feb 09 06:20:00 AM UTC 25 |
| Finished | Feb 09 06:20:20 AM UTC 25 |
| Peak memory | 269064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620758543 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.2620758543 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2917005910 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 53395700 ps |
| CPU time | 19.71 seconds |
| Started | Feb 09 06:19:57 AM UTC 25 |
| Finished | Feb 09 06:20:18 AM UTC 25 |
| Peak memory | 295088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917005910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2917005910 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.3397828388 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 11390800 ps |
| CPU time | 37.64 seconds |
| Started | Feb 09 06:19:51 AM UTC 25 |
| Finished | Feb 09 06:20:31 AM UTC 25 |
| Peak memory | 285504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 97828388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.3397828388 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.4068070010 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 14067328600 ps |
| CPU time | 119.08 seconds |
| Started | Feb 09 06:19:43 AM UTC 25 |
| Finished | Feb 09 06:21:44 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068070010 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.4068070010 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.2953477966 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3615904700 ps |
| CPU time | 253.84 seconds |
| Started | Feb 09 06:19:43 AM UTC 25 |
| Finished | Feb 09 06:24:01 AM UTC 25 |
| Peak memory | 302148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953477966 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.2953477966 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1709653143 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 154993367600 ps |
| CPU time | 327.32 seconds |
| Started | Feb 09 06:19:46 AM UTC 25 |
| Finished | Feb 09 06:25:18 AM UTC 25 |
| Peak memory | 303716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1709653143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_in tr_rd_slow_flash.1709653143 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.2218477037 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 73426500 ps |
| CPU time | 179.14 seconds |
| Started | Feb 09 06:19:43 AM UTC 25 |
| Finished | Feb 09 06:22:45 AM UTC 25 |
| Peak memory | 274880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218477037 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.2218477037 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.1956941165 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 96640000 ps |
| CPU time | 34.91 seconds |
| Started | Feb 09 06:19:46 AM UTC 25 |
| Finished | Feb 09 06:20:23 AM UTC 25 |
| Peak memory | 287720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956941165 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.1956941165 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.575374909 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 48914600 ps |
| CPU time | 48.66 seconds |
| Started | Feb 09 06:19:48 AM UTC 25 |
| Finished | Feb 09 06:20:39 AM UTC 25 |
| Peak memory | 277432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5753 74909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.575374909 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.392699685 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 545086900 ps |
| CPU time | 90.02 seconds |
| Started | Feb 09 06:19:55 AM UTC 25 |
| Finished | Feb 09 06:21:28 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392699685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.392699685 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.2077062021 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 23193400 ps |
| CPU time | 269.02 seconds |
| Started | Feb 09 06:19:43 AM UTC 25 |
| Finished | Feb 09 06:24:16 AM UTC 25 |
| Peak memory | 288888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077062021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2077062021 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.395094303 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 244508100 ps |
| CPU time | 18.9 seconds |
| Started | Feb 09 06:20:20 AM UTC 25 |
| Finished | Feb 09 06:20:40 AM UTC 25 |
| Peak memory | 269332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395094303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.395094303 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.3228787049 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 19442000 ps |
| CPU time | 21.91 seconds |
| Started | Feb 09 06:20:19 AM UTC 25 |
| Finished | Feb 09 06:20:42 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228787049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3228787049 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.2184386221 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 3423600800 ps |
| CPU time | 136.55 seconds |
| Started | Feb 09 06:20:04 AM UTC 25 |
| Finished | Feb 09 06:22:23 AM UTC 25 |
| Peak memory | 275176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184386221 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.2184386221 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.2968969753 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 6414320500 ps |
| CPU time | 168.67 seconds |
| Started | Feb 09 06:20:08 AM UTC 25 |
| Finished | Feb 09 06:23:00 AM UTC 25 |
| Peak memory | 301892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968969753 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.2968969753 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4021058596 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 119173737000 ps |
| CPU time | 367.28 seconds |
| Started | Feb 09 06:20:09 AM UTC 25 |
| Finished | Feb 09 06:26:21 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4021058596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_in tr_rd_slow_flash.4021058596 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.2905736057 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 105215000 ps |
| CPU time | 155.54 seconds |
| Started | Feb 09 06:20:05 AM UTC 25 |
| Finished | Feb 09 06:22:43 AM UTC 25 |
| Peak memory | 271360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905736057 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.2905736057 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.287981906 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 30603100 ps |
| CPU time | 54.05 seconds |
| Started | Feb 09 06:20:10 AM UTC 25 |
| Finished | Feb 09 06:21:06 AM UTC 25 |
| Peak memory | 287960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287981906 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.287981906 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.2490303697 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 30484600 ps |
| CPU time | 51.96 seconds |
| Started | Feb 09 06:20:10 AM UTC 25 |
| Finished | Feb 09 06:21:04 AM UTC 25 |
| Peak memory | 281500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490 303697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2490303697 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.2050623805 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1603560500 ps |
| CPU time | 78.97 seconds |
| Started | Feb 09 06:20:19 AM UTC 25 |
| Finished | Feb 09 06:21:40 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050623805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2050623805 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.740330000 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 21013400 ps |
| CPU time | 155.49 seconds |
| Started | Feb 09 06:20:03 AM UTC 25 |
| Finished | Feb 09 06:22:41 AM UTC 25 |
| Peak memory | 289508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740330000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.740330000 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1655455714 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 43008100 ps |
| CPU time | 25.14 seconds |
| Started | Feb 09 05:30:50 AM UTC 25 |
| Finished | Feb 09 05:31:16 AM UTC 25 |
| Peak memory | 269080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655455714 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1655455714 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3563920334 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 19851200 ps |
| CPU time | 24.79 seconds |
| Started | Feb 09 05:30:22 AM UTC 25 |
| Finished | Feb 09 05:30:49 AM UTC 25 |
| Peak memory | 273136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563920334 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.3563920334 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2481814534 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 28111800 ps |
| CPU time | 25.39 seconds |
| Started | Feb 09 05:30:11 AM UTC 25 |
| Finished | Feb 09 05:30:38 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481814534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2481814534 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.4217724491 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 746861600 ps |
| CPU time | 221.09 seconds |
| Started | Feb 09 05:27:35 AM UTC 25 |
| Finished | Feb 09 05:31:19 AM UTC 25 |
| Peak memory | 289672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 + otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4217724491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ derr_detect.4217724491 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1540501262 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 279541700 ps |
| CPU time | 431.56 seconds |
| Started | Feb 09 05:24:41 AM UTC 25 |
| Finished | Feb 09 05:31:58 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540501262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1540501262 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.3332025372 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 3927894600 ps |
| CPU time | 3341.55 seconds |
| Started | Feb 09 05:25:28 AM UTC 25 |
| Finished | Feb 09 06:21:44 AM UTC 25 |
| Peak memory | 275964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332025372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.3332025372 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.3854164279 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1469267500 ps |
| CPU time | 3066.25 seconds |
| Started | Feb 09 05:25:18 AM UTC 25 |
| Finished | Feb 09 06:16:55 AM UTC 25 |
| Peak memory | 278024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854164279 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3854164279 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.2033420017 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3054957700 ps |
| CPU time | 1160.34 seconds |
| Started | Feb 09 05:25:22 AM UTC 25 |
| Finished | Feb 09 05:44:54 AM UTC 25 |
| Peak memory | 285732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033420017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2033420017 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2035431134 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3207752300 ps |
| CPU time | 30.77 seconds |
| Started | Feb 09 05:25:11 AM UTC 25 |
| Finished | Feb 09 05:25:44 AM UTC 25 |
| Peak memory | 273064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035431134 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2035431134 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.4179640771 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 594381900 ps |
| CPU time | 50.23 seconds |
| Started | Feb 09 05:30:13 AM UTC 25 |
| Finished | Feb 09 05:31:05 AM UTC 25 |
| Peak memory | 273188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179640771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fs_sup.4179640771 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.1429161098 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 193639998300 ps |
| CPU time | 2595.7 seconds |
| Started | Feb 09 05:25:14 AM UTC 25 |
| Finished | Feb 09 06:08:58 AM UTC 25 |
| Peak memory | 275012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429161098 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.1429161098 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.3365353307 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 503689300 ps |
| CPU time | 151.08 seconds |
| Started | Feb 09 05:24:35 AM UTC 25 |
| Finished | Feb 09 05:27:09 AM UTC 25 |
| Peak memory | 272684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365353307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3365353307 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.3037509373 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 46671000 ps |
| CPU time | 24.84 seconds |
| Started | Feb 09 05:30:39 AM UTC 25 |
| Finished | Feb 09 05:31:05 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 37509373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_s eed_err.3037509373 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.757612719 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 120161338700 ps |
| CPU time | 882.25 seconds |
| Started | Feb 09 05:24:55 AM UTC 25 |
| Finished | Feb 09 05:39:47 AM UTC 25 |
| Peak memory | 275296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757612719 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.757612719 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.3260226669 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1923166100 ps |
| CPU time | 93.86 seconds |
| Started | Feb 09 05:24:38 AM UTC 25 |
| Finished | Feb 09 05:26:14 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260226669 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.3260226669 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2138693545 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3978263600 ps |
| CPU time | 531.42 seconds |
| Started | Feb 09 05:27:52 AM UTC 25 |
| Finished | Feb 09 05:36:50 AM UTC 25 |
| Peak memory | 332676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138693 545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integrity.2138693545 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1450444372 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 12078373300 ps |
| CPU time | 190.65 seconds |
| Started | Feb 09 05:28:15 AM UTC 25 |
| Finished | Feb 09 05:31:29 AM UTC 25 |
| Peak memory | 303868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1450444372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_int r_rd_slow_flash.1450444372 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.389207249 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 10684782800 ps |
| CPU time | 100.76 seconds |
| Started | Feb 09 05:28:14 AM UTC 25 |
| Finished | Feb 09 05:29:57 AM UTC 25 |
| Peak memory | 275244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389207249 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.389207249 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2731155547 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 27474945400 ps |
| CPU time | 221.14 seconds |
| Started | Feb 09 05:28:41 AM UTC 25 |
| Finished | Feb 09 05:32:25 AM UTC 25 |
| Peak memory | 271372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2731155547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 4.flash_ctrl_intr_wr_slow_flash.2731155547 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3525080618 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2769140000 ps |
| CPU time | 88.5 seconds |
| Started | Feb 09 05:25:38 AM UTC 25 |
| Finished | Feb 09 05:27:08 AM UTC 25 |
| Peak memory | 275100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525080618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3525080618 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3284562252 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 15805400 ps |
| CPU time | 24.6 seconds |
| Started | Feb 09 05:30:29 AM UTC 25 |
| Finished | Feb 09 05:30:55 AM UTC 25 |
| Peak memory | 275292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 84562252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3284562252 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.430467396 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 945694300 ps |
| CPU time | 83.32 seconds |
| Started | Feb 09 05:25:39 AM UTC 25 |
| Finished | Feb 09 05:27:04 AM UTC 25 |
| Peak memory | 270904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430467396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.430467396 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.4019750469 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 29075361300 ps |
| CPU time | 384.9 seconds |
| Started | Feb 09 05:25:10 AM UTC 25 |
| Finished | Feb 09 05:31:40 AM UTC 25 |
| Peak memory | 283440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4019750469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.f lash_ctrl_mp_regions.4019750469 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1328310514 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 41823700 ps |
| CPU time | 226.65 seconds |
| Started | Feb 09 05:25:05 AM UTC 25 |
| Finished | Feb 09 05:28:55 AM UTC 25 |
| Peak memory | 275520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328310514 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.1328310514 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.3256399434 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 19540481600 ps |
| CPU time | 187.58 seconds |
| Started | Feb 09 05:27:50 AM UTC 25 |
| Finished | Feb 09 05:31:01 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_ pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3256399434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.f lash_ctrl_oversize_error.3256399434 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3328087261 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 27359900 ps |
| CPU time | 26.33 seconds |
| Started | Feb 09 05:30:22 AM UTC 25 |
| Finished | Feb 09 05:30:50 AM UTC 25 |
| Peak memory | 273388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct =4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328087261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ph y_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3328087261 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.642858075 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2090746000 ps |
| CPU time | 514.3 seconds |
| Started | Feb 09 05:24:36 AM UTC 25 |
| Finished | Feb 09 05:33:16 AM UTC 25 |
| Peak memory | 275168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642858075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.642858075 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2107071538 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 675617100 ps |
| CPU time | 44.62 seconds |
| Started | Feb 09 05:28:57 AM UTC 25 |
| Finished | Feb 09 05:29:44 AM UTC 25 |
| Peak memory | 271120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107071538 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.2107071538 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.360727859 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 634349500 ps |
| CPU time | 945.49 seconds |
| Started | Feb 09 05:24:21 AM UTC 25 |
| Finished | Feb 09 05:40:17 AM UTC 25 |
| Peak memory | 293600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360727859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.360727859 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1129192389 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1183695000 ps |
| CPU time | 193.42 seconds |
| Started | Feb 09 05:24:35 AM UTC 25 |
| Finished | Feb 09 05:27:51 AM UTC 25 |
| Peak memory | 272896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129192389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1129192389 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2262772603 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 157958200 ps |
| CPU time | 58.11 seconds |
| Started | Feb 09 05:29:28 AM UTC 25 |
| Finished | Feb 09 05:30:28 AM UTC 25 |
| Peak memory | 287900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262772603 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.2262772603 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.3529190518 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 18977000 ps |
| CPU time | 37.92 seconds |
| Started | Feb 09 05:27:10 AM UTC 25 |
| Finished | Feb 09 05:27:49 AM UTC 25 |
| Peak memory | 275272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529190 518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep _derr.3529190518 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.2988936231 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 121079800 ps |
| CPU time | 44.82 seconds |
| Started | Feb 09 05:26:32 AM UTC 25 |
| Finished | Feb 09 05:27:18 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988936231 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.2988936231 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.2246851825 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1009428800 ps |
| CPU time | 109.27 seconds |
| Started | Feb 09 05:26:10 AM UTC 25 |
| Finished | Feb 09 05:28:02 AM UTC 25 |
| Peak memory | 301960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246851 825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.2246851825 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.483839927 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 755764300 ps |
| CPU time | 146.09 seconds |
| Started | Feb 09 05:27:10 AM UTC 25 |
| Finished | Feb 09 05:29:38 AM UTC 25 |
| Peak memory | 291744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=483839927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_ro_derr.483839927 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.3775075685 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2366236900 ps |
| CPU time | 124.99 seconds |
| Started | Feb 09 05:26:32 AM UTC 25 |
| Finished | Feb 09 05:28:39 AM UTC 25 |
| Peak memory | 291844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3775075685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3775075685 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3033367886 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2792671200 ps |
| CPU time | 450.53 seconds |
| Started | Feb 09 05:26:15 AM UTC 25 |
| Finished | Feb 09 05:33:51 AM UTC 25 |
| Peak memory | 324440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033367886 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.3033367886 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.950317379 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 30630400 ps |
| CPU time | 54.93 seconds |
| Started | Feb 09 05:29:13 AM UTC 25 |
| Finished | Feb 09 05:30:10 AM UTC 25 |
| Peak memory | 287900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950317379 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.950317379 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1023105421 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 71564200 ps |
| CPU time | 42.17 seconds |
| Started | Feb 09 05:29:23 AM UTC 25 |
| Finished | Feb 09 05:30:07 AM UTC 25 |
| Peak memory | 285620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023 105421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1023105421 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.1127194046 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1810907500 ps |
| CPU time | 206.96 seconds |
| Started | Feb 09 05:26:46 AM UTC 25 |
| Finished | Feb 09 05:30:16 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112719404 6 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.1127194046 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3315980796 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2764684200 ps |
| CPU time | 7199.2 seconds |
| Started | Feb 09 05:29:45 AM UTC 25 |
| Finished | Feb 09 07:30:58 AM UTC 25 |
| Peak memory | 312184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315980796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3315980796 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.3270418540 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1727287500 ps |
| CPU time | 87.74 seconds |
| Started | Feb 09 05:29:58 AM UTC 25 |
| Finished | Feb 09 05:31:28 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270418540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.3270418540 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1862739060 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 477572300 ps |
| CPU time | 64.86 seconds |
| Started | Feb 09 05:27:05 AM UTC 25 |
| Finished | Feb 09 05:28:13 AM UTC 25 |
| Peak memory | 275340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862739060 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_serr_address.1862739060 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.3671610792 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1872958600 ps |
| CPU time | 84.87 seconds |
| Started | Feb 09 05:26:47 AM UTC 25 |
| Finished | Feb 09 05:28:14 AM UTC 25 |
| Peak memory | 285832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671610792 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_serr_counter.3671610792 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.3645153007 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 81320100 ps |
| CPU time | 153.01 seconds |
| Started | Feb 09 05:24:11 AM UTC 25 |
| Finished | Feb 09 05:26:47 AM UTC 25 |
| Peak memory | 287696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645153007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3645153007 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.1280387648 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 92199100 ps |
| CPU time | 37.32 seconds |
| Started | Feb 09 05:24:15 AM UTC 25 |
| Finished | Feb 09 05:24:54 AM UTC 25 |
| Peak memory | 271144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280387648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1280387648 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.4190725623 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 762346000 ps |
| CPU time | 789.95 seconds |
| Started | Feb 09 05:30:08 AM UTC 25 |
| Finished | Feb 09 05:43:27 AM UTC 25 |
| Peak memory | 289580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190725623 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.4190725623 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.1571907939 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 42973500 ps |
| CPU time | 39.45 seconds |
| Started | Feb 09 05:24:23 AM UTC 25 |
| Finished | Feb 09 05:25:04 AM UTC 25 |
| Peak memory | 270888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571907939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1571907939 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.2446393965 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2149727700 ps |
| CPU time | 214.4 seconds |
| Started | Feb 09 05:25:45 AM UTC 25 |
| Finished | Feb 09 05:29:23 AM UTC 25 |
| Peak memory | 275244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446393965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.2446393965 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.1727752774 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 91419400 ps |
| CPU time | 18.15 seconds |
| Started | Feb 09 06:20:30 AM UTC 25 |
| Finished | Feb 09 06:20:50 AM UTC 25 |
| Peak memory | 269084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727752774 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.1727752774 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.3588282287 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 44723300 ps |
| CPU time | 26.6 seconds |
| Started | Feb 09 06:20:29 AM UTC 25 |
| Finished | Feb 09 06:20:57 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588282287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3588282287 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.1843927417 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 5172441400 ps |
| CPU time | 192.41 seconds |
| Started | Feb 09 06:20:24 AM UTC 25 |
| Finished | Feb 09 06:23:39 AM UTC 25 |
| Peak memory | 270948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843927417 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.1843927417 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.4011634477 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 78372800 ps |
| CPU time | 176.44 seconds |
| Started | Feb 09 06:20:25 AM UTC 25 |
| Finished | Feb 09 06:23:24 AM UTC 25 |
| Peak memory | 275328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011634477 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.4011634477 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.4220240462 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 11528353400 ps |
| CPU time | 98.08 seconds |
| Started | Feb 09 06:20:29 AM UTC 25 |
| Finished | Feb 09 06:22:10 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220240462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.4220240462 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.2330134800 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 32925200 ps |
| CPU time | 216.95 seconds |
| Started | Feb 09 06:20:21 AM UTC 25 |
| Finished | Feb 09 06:24:01 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330134800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2330134800 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3681408221 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 433101400 ps |
| CPU time | 17.36 seconds |
| Started | Feb 09 06:20:45 AM UTC 25 |
| Finished | Feb 09 06:21:04 AM UTC 25 |
| Peak memory | 269340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681408221 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3681408221 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3872594278 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 151934800 ps |
| CPU time | 23.71 seconds |
| Started | Feb 09 06:20:43 AM UTC 25 |
| Finished | Feb 09 06:21:08 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872594278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3872594278 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.4261367786 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 14980400 ps |
| CPU time | 30.76 seconds |
| Started | Feb 09 06:20:41 AM UTC 25 |
| Finished | Feb 09 06:21:13 AM UTC 25 |
| Peak memory | 285768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 61367786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.4261367786 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.3598028372 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 6981333100 ps |
| CPU time | 97.57 seconds |
| Started | Feb 09 06:20:39 AM UTC 25 |
| Finished | Feb 09 06:22:18 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598028372 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.3598028372 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.3083830674 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 39578000 ps |
| CPU time | 197.68 seconds |
| Started | Feb 09 06:20:40 AM UTC 25 |
| Finished | Feb 09 06:24:01 AM UTC 25 |
| Peak memory | 275328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083830674 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.3083830674 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.2986199286 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4036544400 ps |
| CPU time | 81.63 seconds |
| Started | Feb 09 06:20:41 AM UTC 25 |
| Finished | Feb 09 06:22:04 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986199286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2986199286 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.2482678532 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 27831500 ps |
| CPU time | 96.21 seconds |
| Started | Feb 09 06:20:31 AM UTC 25 |
| Finished | Feb 09 06:22:10 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482678532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2482678532 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.3322092408 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 29991700 ps |
| CPU time | 19.92 seconds |
| Started | Feb 09 06:21:05 AM UTC 25 |
| Finished | Feb 09 06:21:26 AM UTC 25 |
| Peak memory | 269064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322092408 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.3322092408 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.1936861677 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 45457300 ps |
| CPU time | 32.34 seconds |
| Started | Feb 09 06:21:05 AM UTC 25 |
| Finished | Feb 09 06:21:39 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936861677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1936861677 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.3844570554 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 46206200 ps |
| CPU time | 38.09 seconds |
| Started | Feb 09 06:21:02 AM UTC 25 |
| Finished | Feb 09 06:21:42 AM UTC 25 |
| Peak memory | 285704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 44570554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.3844570554 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.2912815718 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3309670700 ps |
| CPU time | 245.64 seconds |
| Started | Feb 09 06:20:51 AM UTC 25 |
| Finished | Feb 09 06:25:00 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912815718 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.2912815718 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.1140909712 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 165500400 ps |
| CPU time | 158.15 seconds |
| Started | Feb 09 06:20:58 AM UTC 25 |
| Finished | Feb 09 06:23:39 AM UTC 25 |
| Peak memory | 271316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140909712 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.1140909712 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.1118539930 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 3683998000 ps |
| CPU time | 74.37 seconds |
| Started | Feb 09 06:21:04 AM UTC 25 |
| Finished | Feb 09 06:22:20 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118539930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1118539930 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.2506050013 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 87260600 ps |
| CPU time | 181.18 seconds |
| Started | Feb 09 06:20:46 AM UTC 25 |
| Finished | Feb 09 06:23:50 AM UTC 25 |
| Peak memory | 287452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506050013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2506050013 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.1846766384 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 79211500 ps |
| CPU time | 18.04 seconds |
| Started | Feb 09 06:21:28 AM UTC 25 |
| Finished | Feb 09 06:21:47 AM UTC 25 |
| Peak memory | 275224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846766384 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.1846766384 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.3189187316 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 24391700 ps |
| CPU time | 15.8 seconds |
| Started | Feb 09 06:21:27 AM UTC 25 |
| Finished | Feb 09 06:21:45 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189187316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3189187316 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.887854759 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 10782600 ps |
| CPU time | 31.21 seconds |
| Started | Feb 09 06:21:14 AM UTC 25 |
| Finished | Feb 09 06:21:47 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88 7854759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.887854759 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.823416937 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 1277642600 ps |
| CPU time | 84.69 seconds |
| Started | Feb 09 06:21:07 AM UTC 25 |
| Finished | Feb 09 06:22:34 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823416937 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.823416937 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.3232197830 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 43622400 ps |
| CPU time | 179.72 seconds |
| Started | Feb 09 06:21:09 AM UTC 25 |
| Finished | Feb 09 06:24:12 AM UTC 25 |
| Peak memory | 275476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232197830 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.3232197830 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.101334310 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3619921100 ps |
| CPU time | 100.04 seconds |
| Started | Feb 09 06:21:17 AM UTC 25 |
| Finished | Feb 09 06:23:00 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101334310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.101334310 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2856957968 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 31475900 ps |
| CPU time | 154.7 seconds |
| Started | Feb 09 06:21:05 AM UTC 25 |
| Finished | Feb 09 06:23:42 AM UTC 25 |
| Peak memory | 287696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856957968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2856957968 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.2396505037 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 54017300 ps |
| CPU time | 21.26 seconds |
| Started | Feb 09 06:21:43 AM UTC 25 |
| Finished | Feb 09 06:22:06 AM UTC 25 |
| Peak memory | 275208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396505037 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.2396505037 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.105128865 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 26984000 ps |
| CPU time | 21.71 seconds |
| Started | Feb 09 06:21:40 AM UTC 25 |
| Finished | Feb 09 06:22:03 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105128865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.105128865 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.424092374 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 22631200 ps |
| CPU time | 34.51 seconds |
| Started | Feb 09 06:21:35 AM UTC 25 |
| Finished | Feb 09 06:22:11 AM UTC 25 |
| Peak memory | 285548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 4092374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.424092374 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.350160083 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1589299400 ps |
| CPU time | 135.71 seconds |
| Started | Feb 09 06:21:30 AM UTC 25 |
| Finished | Feb 09 06:23:48 AM UTC 25 |
| Peak memory | 272996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350160083 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.350160083 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.620327444 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 6513379500 ps |
| CPU time | 81.23 seconds |
| Started | Feb 09 06:21:39 AM UTC 25 |
| Finished | Feb 09 06:23:02 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620327444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.620327444 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.408935685 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 21834600 ps |
| CPU time | 138.54 seconds |
| Started | Feb 09 06:21:29 AM UTC 25 |
| Finished | Feb 09 06:23:50 AM UTC 25 |
| Peak memory | 287716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408935685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.408935685 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.2169032228 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 131781800 ps |
| CPU time | 22.85 seconds |
| Started | Feb 09 06:21:57 AM UTC 25 |
| Finished | Feb 09 06:22:21 AM UTC 25 |
| Peak memory | 275484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169032228 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.2169032228 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.3663591830 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 25581300 ps |
| CPU time | 17.58 seconds |
| Started | Feb 09 06:21:51 AM UTC 25 |
| Finished | Feb 09 06:22:10 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663591830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3663591830 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2777427691 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 26056100 ps |
| CPU time | 25.49 seconds |
| Started | Feb 09 06:21:48 AM UTC 25 |
| Finished | Feb 09 06:22:14 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 77427691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.2777427691 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.674756000 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 19226428700 ps |
| CPU time | 144.61 seconds |
| Started | Feb 09 06:21:45 AM UTC 25 |
| Finished | Feb 09 06:24:13 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674756000 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.674756000 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2807961695 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 154772400 ps |
| CPU time | 166.51 seconds |
| Started | Feb 09 06:21:46 AM UTC 25 |
| Finished | Feb 09 06:24:35 AM UTC 25 |
| Peak memory | 271316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807961695 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.2807961695 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.1178249750 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9289510900 ps |
| CPU time | 86.67 seconds |
| Started | Feb 09 06:21:48 AM UTC 25 |
| Finished | Feb 09 06:23:16 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178249750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1178249750 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1169414004 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 42788700 ps |
| CPU time | 119.44 seconds |
| Started | Feb 09 06:21:45 AM UTC 25 |
| Finished | Feb 09 06:23:47 AM UTC 25 |
| Peak memory | 287708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169414004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1169414004 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.1696473493 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 52239800 ps |
| CPU time | 22.93 seconds |
| Started | Feb 09 06:22:11 AM UTC 25 |
| Finished | Feb 09 06:22:35 AM UTC 25 |
| Peak memory | 269080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696473493 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.1696473493 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.3075253418 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 14337700 ps |
| CPU time | 20.7 seconds |
| Started | Feb 09 06:22:11 AM UTC 25 |
| Finished | Feb 09 06:22:33 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075253418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3075253418 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.4122658775 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 10990400 ps |
| CPU time | 39.97 seconds |
| Started | Feb 09 06:22:05 AM UTC 25 |
| Finished | Feb 09 06:22:47 AM UTC 25 |
| Peak memory | 285480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 22658775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.4122658775 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3332902351 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 14937071100 ps |
| CPU time | 119.69 seconds |
| Started | Feb 09 06:22:04 AM UTC 25 |
| Finished | Feb 09 06:24:06 AM UTC 25 |
| Peak memory | 275048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332902351 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.3332902351 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2739728857 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 152587900 ps |
| CPU time | 161.18 seconds |
| Started | Feb 09 06:22:04 AM UTC 25 |
| Finished | Feb 09 06:24:48 AM UTC 25 |
| Peak memory | 271360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739728857 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.2739728857 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3143275678 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 1473010200 ps |
| CPU time | 73.7 seconds |
| Started | Feb 09 06:22:06 AM UTC 25 |
| Finished | Feb 09 06:23:22 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143275678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3143275678 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.2723244468 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 30408600 ps |
| CPU time | 116.34 seconds |
| Started | Feb 09 06:21:59 AM UTC 25 |
| Finished | Feb 09 06:23:58 AM UTC 25 |
| Peak memory | 287708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723244468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2723244468 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.1846172377 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 27757900 ps |
| CPU time | 22.28 seconds |
| Started | Feb 09 06:22:24 AM UTC 25 |
| Finished | Feb 09 06:22:48 AM UTC 25 |
| Peak memory | 269068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846172377 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.1846172377 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.2396979369 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 48232400 ps |
| CPU time | 27.42 seconds |
| Started | Feb 09 06:22:22 AM UTC 25 |
| Finished | Feb 09 06:22:51 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396979369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2396979369 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.1924545277 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 10742300 ps |
| CPU time | 29.84 seconds |
| Started | Feb 09 06:22:19 AM UTC 25 |
| Finished | Feb 09 06:22:50 AM UTC 25 |
| Peak memory | 285704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 24545277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.1924545277 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.3042450400 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2010253900 ps |
| CPU time | 71.37 seconds |
| Started | Feb 09 06:22:12 AM UTC 25 |
| Finished | Feb 09 06:23:26 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042450400 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.3042450400 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.574064843 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 150460600 ps |
| CPU time | 133.82 seconds |
| Started | Feb 09 06:22:16 AM UTC 25 |
| Finished | Feb 09 06:24:32 AM UTC 25 |
| Peak memory | 271320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574064843 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.574064843 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.3279601417 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 1124888900 ps |
| CPU time | 90.48 seconds |
| Started | Feb 09 06:22:21 AM UTC 25 |
| Finished | Feb 09 06:23:54 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279601417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3279601417 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3350299839 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 208610300 ps |
| CPU time | 221.89 seconds |
| Started | Feb 09 06:22:11 AM UTC 25 |
| Finished | Feb 09 06:25:56 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350299839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3350299839 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.3623095045 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 135299700 ps |
| CPU time | 16.15 seconds |
| Started | Feb 09 06:22:42 AM UTC 25 |
| Finished | Feb 09 06:22:59 AM UTC 25 |
| Peak memory | 275484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623095045 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.3623095045 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.3320727452 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 49784300 ps |
| CPU time | 22.54 seconds |
| Started | Feb 09 06:22:40 AM UTC 25 |
| Finished | Feb 09 06:23:04 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320727452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3320727452 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.2230921039 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 16245300 ps |
| CPU time | 42.59 seconds |
| Started | Feb 09 06:22:35 AM UTC 25 |
| Finished | Feb 09 06:23:19 AM UTC 25 |
| Peak memory | 285440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 30921039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.2230921039 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.561395891 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 3752107000 ps |
| CPU time | 90.7 seconds |
| Started | Feb 09 06:22:27 AM UTC 25 |
| Finished | Feb 09 06:24:00 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561395891 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.561395891 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.1459134002 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 122139900 ps |
| CPU time | 153.25 seconds |
| Started | Feb 09 06:22:33 AM UTC 25 |
| Finished | Feb 09 06:25:09 AM UTC 25 |
| Peak memory | 271316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459134002 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.1459134002 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.1080209746 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3968201900 ps |
| CPU time | 82.06 seconds |
| Started | Feb 09 06:22:36 AM UTC 25 |
| Finished | Feb 09 06:24:00 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080209746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1080209746 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.4165605814 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 23224000 ps |
| CPU time | 91.9 seconds |
| Started | Feb 09 06:22:25 AM UTC 25 |
| Finished | Feb 09 06:23:59 AM UTC 25 |
| Peak memory | 287448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165605814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4165605814 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.2250942329 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 21169100 ps |
| CPU time | 23.75 seconds |
| Started | Feb 09 06:22:51 AM UTC 25 |
| Finished | Feb 09 06:23:17 AM UTC 25 |
| Peak memory | 269324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250942329 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.2250942329 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.3190916744 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 13817400 ps |
| CPU time | 26.04 seconds |
| Started | Feb 09 06:22:51 AM UTC 25 |
| Finished | Feb 09 06:23:19 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190916744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3190916744 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.2848182163 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 26697000 ps |
| CPU time | 29.68 seconds |
| Started | Feb 09 06:22:48 AM UTC 25 |
| Finished | Feb 09 06:23:19 AM UTC 25 |
| Peak memory | 285476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28 48182163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.2848182163 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.2890456858 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 550111600 ps |
| CPU time | 73.19 seconds |
| Started | Feb 09 06:22:46 AM UTC 25 |
| Finished | Feb 09 06:24:01 AM UTC 25 |
| Peak memory | 272996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890456858 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.2890456858 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2964276672 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 40673700 ps |
| CPU time | 164.17 seconds |
| Started | Feb 09 06:22:46 AM UTC 25 |
| Finished | Feb 09 06:25:33 AM UTC 25 |
| Peak memory | 271188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964276672 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.2964276672 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.96691299 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3827514100 ps |
| CPU time | 92.05 seconds |
| Started | Feb 09 06:22:48 AM UTC 25 |
| Finished | Feb 09 06:24:22 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96691299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.96691299 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.665896497 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 29101500 ps |
| CPU time | 179.8 seconds |
| Started | Feb 09 06:22:44 AM UTC 25 |
| Finished | Feb 09 06:25:47 AM UTC 25 |
| Peak memory | 287720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665896497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.665896497 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1321033188 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 15332100 ps |
| CPU time | 26.23 seconds |
| Started | Feb 09 05:33:46 AM UTC 25 |
| Finished | Feb 09 05:34:13 AM UTC 25 |
| Peak memory | 295028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321033188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1321033188 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.2229891892 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 18313000 ps |
| CPU time | 40.76 seconds |
| Started | Feb 09 05:33:41 AM UTC 25 |
| Finished | Feb 09 05:34:24 AM UTC 25 |
| Peak memory | 285508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 29891892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.2229891892 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.447554003 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 7785815700 ps |
| CPU time | 3109.8 seconds |
| Started | Feb 09 05:31:17 AM UTC 25 |
| Finished | Feb 09 06:23:40 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447554003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_err or_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 5.flash_ctrl_error_mp.447554003 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.1181387117 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 365369900 ps |
| CPU time | 1170.29 seconds |
| Started | Feb 09 05:31:07 AM UTC 25 |
| Finished | Feb 09 05:50:50 AM UTC 25 |
| Peak memory | 283364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181387117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1181387117 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2383344990 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 383777500 ps |
| CPU time | 42.12 seconds |
| Started | Feb 09 05:31:05 AM UTC 25 |
| Finished | Feb 09 05:31:49 AM UTC 25 |
| Peak memory | 273072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383344990 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2383344990 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1625975394 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 10052991600 ps |
| CPU time | 55.54 seconds |
| Started | Feb 09 05:34:07 AM UTC 25 |
| Finished | Feb 09 05:35:04 AM UTC 25 |
| Peak memory | 285588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1625975394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 5.flash_ctrl_hw_prog_rma_wipe_err.1625975394 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.4276548358 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 40120850300 ps |
| CPU time | 843.46 seconds |
| Started | Feb 09 05:30:58 AM UTC 25 |
| Finished | Feb 09 05:45:11 AM UTC 25 |
| Peak memory | 275004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276548358 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.4276548358 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2509125859 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2353545800 ps |
| CPU time | 215.32 seconds |
| Started | Feb 09 05:30:56 AM UTC 25 |
| Finished | Feb 09 05:34:35 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509125859 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.2509125859 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.1656201111 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3681404400 ps |
| CPU time | 180.59 seconds |
| Started | Feb 09 05:32:26 AM UTC 25 |
| Finished | Feb 09 05:35:30 AM UTC 25 |
| Peak memory | 306048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656201111 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.1656201111 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2676098082 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 24635992900 ps |
| CPU time | 205.8 seconds |
| Started | Feb 09 05:32:41 AM UTC 25 |
| Finished | Feb 09 05:36:10 AM UTC 25 |
| Peak memory | 303872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2676098082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_int r_rd_slow_flash.2676098082 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.2211834960 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5018835200 ps |
| CPU time | 106.45 seconds |
| Started | Feb 09 05:32:29 AM UTC 25 |
| Finished | Feb 09 05:34:19 AM UTC 25 |
| Peak memory | 271124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211834960 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.2211834960 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2077263257 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 24206628700 ps |
| CPU time | 207.04 seconds |
| Started | Feb 09 05:33:02 AM UTC 25 |
| Finished | Feb 09 05:36:32 AM UTC 25 |
| Peak memory | 275464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2077263257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_intr_wr_slow_flash.2077263257 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.3723998245 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3198674300 ps |
| CPU time | 58.15 seconds |
| Started | Feb 09 05:31:21 AM UTC 25 |
| Finished | Feb 09 05:32:20 AM UTC 25 |
| Peak memory | 275096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723998245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3723998245 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3026891607 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 15482800 ps |
| CPU time | 24.94 seconds |
| Started | Feb 09 05:33:52 AM UTC 25 |
| Finished | Feb 09 05:34:18 AM UTC 25 |
| Peak memory | 275292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 26891607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3026891607 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1230445489 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 6145549400 ps |
| CPU time | 136.15 seconds |
| Started | Feb 09 05:31:05 AM UTC 25 |
| Finished | Feb 09 05:33:24 AM UTC 25 |
| Peak memory | 275480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1230445489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.f lash_ctrl_mp_regions.1230445489 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.2102917609 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 329535500 ps |
| CPU time | 160.26 seconds |
| Started | Feb 09 05:31:01 AM UTC 25 |
| Finished | Feb 09 05:33:44 AM UTC 25 |
| Peak memory | 270916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102917609 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.2102917609 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.522173261 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 126737600 ps |
| CPU time | 375.44 seconds |
| Started | Feb 09 05:30:54 AM UTC 25 |
| Finished | Feb 09 05:37:14 AM UTC 25 |
| Peak memory | 275168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522173261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.522173261 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3204418350 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 879658200 ps |
| CPU time | 32.17 seconds |
| Started | Feb 09 05:33:07 AM UTC 25 |
| Finished | Feb 09 05:33:40 AM UTC 25 |
| Peak memory | 271124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204418350 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.3204418350 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1780742202 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 206056700 ps |
| CPU time | 456.75 seconds |
| Started | Feb 09 05:30:51 AM UTC 25 |
| Finished | Feb 09 05:38:33 AM UTC 25 |
| Peak memory | 289500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780742202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1780742202 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1035548908 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 66508900 ps |
| CPU time | 56.18 seconds |
| Started | Feb 09 05:33:33 AM UTC 25 |
| Finished | Feb 09 05:34:31 AM UTC 25 |
| Peak memory | 285632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035548908 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.1035548908 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.4167156874 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2786576500 ps |
| CPU time | 89.21 seconds |
| Started | Feb 09 05:31:30 AM UTC 25 |
| Finished | Feb 09 05:33:01 AM UTC 25 |
| Peak memory | 292000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167156 874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.4167156874 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.694397504 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1304066600 ps |
| CPU time | 132.75 seconds |
| Started | Feb 09 05:32:00 AM UTC 25 |
| Finished | Feb 09 05:34:15 AM UTC 25 |
| Peak memory | 291720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=694397504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_ro_derr.694397504 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.1975826241 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 602693500 ps |
| CPU time | 152.35 seconds |
| Started | Feb 09 05:31:41 AM UTC 25 |
| Finished | Feb 09 05:34:16 AM UTC 25 |
| Peak memory | 291972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1975826241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.1975826241 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2399691045 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4016453300 ps |
| CPU time | 176.15 seconds |
| Started | Feb 09 05:32:22 AM UTC 25 |
| Finished | Feb 09 05:35:21 AM UTC 25 |
| Peak memory | 291712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2399691045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ ctrl_rw_derr.2399691045 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3550448245 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 93993800 ps |
| CPU time | 41.49 seconds |
| Started | Feb 09 05:33:17 AM UTC 25 |
| Finished | Feb 09 05:34:00 AM UTC 25 |
| Peak memory | 283544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550448245 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.3550448245 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.675220376 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 71767800 ps |
| CPU time | 39.08 seconds |
| Started | Feb 09 05:33:25 AM UTC 25 |
| Finished | Feb 09 05:34:06 AM UTC 25 |
| Peak memory | 277396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6752 20376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.675220376 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4223665836 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1431058400 ps |
| CPU time | 189.8 seconds |
| Started | Feb 09 05:31:49 AM UTC 25 |
| Finished | Feb 09 05:35:02 AM UTC 25 |
| Peak memory | 306404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422366583 6 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.4223665836 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3323320600 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 629934200 ps |
| CPU time | 98.16 seconds |
| Started | Feb 09 05:33:46 AM UTC 25 |
| Finished | Feb 09 05:35:26 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323320600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3323320600 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2034348046 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 76822400 ps |
| CPU time | 171.03 seconds |
| Started | Feb 09 05:30:51 AM UTC 25 |
| Finished | Feb 09 05:33:45 AM UTC 25 |
| Peak memory | 287708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034348046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2034348046 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.303341625 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 4547890800 ps |
| CPU time | 155.56 seconds |
| Started | Feb 09 05:31:29 AM UTC 25 |
| Finished | Feb 09 05:34:07 AM UTC 25 |
| Peak memory | 271144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303341625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.303341625 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.3140848905 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 40774200 ps |
| CPU time | 26.07 seconds |
| Started | Feb 09 06:23:01 AM UTC 25 |
| Finished | Feb 09 06:23:28 AM UTC 25 |
| Peak memory | 284852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140848905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3140848905 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.3859026268 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 132510400 ps |
| CPU time | 143.93 seconds |
| Started | Feb 09 06:22:52 AM UTC 25 |
| Finished | Feb 09 06:25:18 AM UTC 25 |
| Peak memory | 275668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859026268 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.3859026268 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.4273909266 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 14481000 ps |
| CPU time | 26.26 seconds |
| Started | Feb 09 06:23:01 AM UTC 25 |
| Finished | Feb 09 06:23:28 AM UTC 25 |
| Peak memory | 295076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273909266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.4273909266 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1007645681 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 39107600 ps |
| CPU time | 194.75 seconds |
| Started | Feb 09 06:23:01 AM UTC 25 |
| Finished | Feb 09 06:26:19 AM UTC 25 |
| Peak memory | 275444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007645681 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.1007645681 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.756470275 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 16001400 ps |
| CPU time | 19.92 seconds |
| Started | Feb 09 06:23:05 AM UTC 25 |
| Finished | Feb 09 06:23:26 AM UTC 25 |
| Peak memory | 295228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756470275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.756470275 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3690691813 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 179182200 ps |
| CPU time | 185.44 seconds |
| Started | Feb 09 06:23:03 AM UTC 25 |
| Finished | Feb 09 06:26:11 AM UTC 25 |
| Peak memory | 271360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690691813 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.3690691813 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.2045174427 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 25761500 ps |
| CPU time | 23.6 seconds |
| Started | Feb 09 06:23:17 AM UTC 25 |
| Finished | Feb 09 06:23:42 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045174427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2045174427 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1995331967 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 38933800 ps |
| CPU time | 184.98 seconds |
| Started | Feb 09 06:23:10 AM UTC 25 |
| Finished | Feb 09 06:26:18 AM UTC 25 |
| Peak memory | 271060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995331967 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.1995331967 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.2059085416 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 14760300 ps |
| CPU time | 18.56 seconds |
| Started | Feb 09 06:23:19 AM UTC 25 |
| Finished | Feb 09 06:23:39 AM UTC 25 |
| Peak memory | 295288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059085416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2059085416 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1312004688 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 42130600 ps |
| CPU time | 179.42 seconds |
| Started | Feb 09 06:23:17 AM UTC 25 |
| Finished | Feb 09 06:26:20 AM UTC 25 |
| Peak memory | 271308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312004688 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.1312004688 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.2260083149 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 14415600 ps |
| CPU time | 19.67 seconds |
| Started | Feb 09 06:23:21 AM UTC 25 |
| Finished | Feb 09 06:23:42 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260083149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2260083149 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4182986307 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 139648300 ps |
| CPU time | 153.13 seconds |
| Started | Feb 09 06:23:19 AM UTC 25 |
| Finished | Feb 09 06:25:55 AM UTC 25 |
| Peak memory | 270976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182986307 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.4182986307 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.2547954474 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 51017800 ps |
| CPU time | 19.49 seconds |
| Started | Feb 09 06:23:26 AM UTC 25 |
| Finished | Feb 09 06:23:46 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547954474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2547954474 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3784625470 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 71440000 ps |
| CPU time | 161.94 seconds |
| Started | Feb 09 06:23:23 AM UTC 25 |
| Finished | Feb 09 06:26:07 AM UTC 25 |
| Peak memory | 275324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784625470 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.3784625470 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.1898068385 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 21322100 ps |
| CPU time | 23.75 seconds |
| Started | Feb 09 06:23:27 AM UTC 25 |
| Finished | Feb 09 06:23:52 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898068385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1898068385 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1987238439 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 78418000 ps |
| CPU time | 166.72 seconds |
| Started | Feb 09 06:23:27 AM UTC 25 |
| Finished | Feb 09 06:26:16 AM UTC 25 |
| Peak memory | 271424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987238439 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1987238439 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.3838772819 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 14072500 ps |
| CPU time | 22.53 seconds |
| Started | Feb 09 06:23:29 AM UTC 25 |
| Finished | Feb 09 06:23:53 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838772819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3838772819 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.4113397917 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 74504400 ps |
| CPU time | 154.72 seconds |
| Started | Feb 09 06:23:29 AM UTC 25 |
| Finished | Feb 09 06:26:07 AM UTC 25 |
| Peak memory | 271056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113397917 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.4113397917 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.639918973 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 40538800 ps |
| CPU time | 22.66 seconds |
| Started | Feb 09 06:23:41 AM UTC 25 |
| Finished | Feb 09 06:24:05 AM UTC 25 |
| Peak memory | 295004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639918973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.639918973 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.1953753850 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 727660800 ps |
| CPU time | 169.11 seconds |
| Started | Feb 09 06:23:29 AM UTC 25 |
| Finished | Feb 09 06:26:21 AM UTC 25 |
| Peak memory | 275476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953753850 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.1953753850 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3195385748 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 115117400 ps |
| CPU time | 25.19 seconds |
| Started | Feb 09 05:37:36 AM UTC 25 |
| Finished | Feb 09 05:38:03 AM UTC 25 |
| Peak memory | 269340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195385748 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3195385748 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2276528271 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 88205500 ps |
| CPU time | 19.31 seconds |
| Started | Feb 09 05:37:23 AM UTC 25 |
| Finished | Feb 09 05:37:44 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276528271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2276528271 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.749226519 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 24654800 ps |
| CPU time | 37.97 seconds |
| Started | Feb 09 05:36:56 AM UTC 25 |
| Finished | Feb 09 05:37:35 AM UTC 25 |
| Peak memory | 285512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74 9226519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.749226519 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.4089204142 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 10091013400 ps |
| CPU time | 3087.28 seconds |
| Started | Feb 09 05:34:36 AM UTC 25 |
| Finished | Feb 09 06:26:35 AM UTC 25 |
| Peak memory | 275424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089204142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.4089204142 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2035538426 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5975743500 ps |
| CPU time | 1105.33 seconds |
| Started | Feb 09 05:34:32 AM UTC 25 |
| Finished | Feb 09 05:53:10 AM UTC 25 |
| Peak memory | 285672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035538426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2035538426 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.3314710591 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 266931200 ps |
| CPU time | 34.22 seconds |
| Started | Feb 09 05:34:32 AM UTC 25 |
| Finished | Feb 09 05:35:08 AM UTC 25 |
| Peak memory | 275428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314710591 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3314710591 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2052367257 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 10013326500 ps |
| CPU time | 248.66 seconds |
| Started | Feb 09 05:37:36 AM UTC 25 |
| Finished | Feb 09 05:41:49 AM UTC 25 |
| Peak memory | 275276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2052367257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 6.flash_ctrl_hw_prog_rma_wipe_err.2052367257 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.237833142 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 30263900 ps |
| CPU time | 20.82 seconds |
| Started | Feb 09 05:37:27 AM UTC 25 |
| Finished | Feb 09 05:37:49 AM UTC 25 |
| Peak memory | 269592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 7833142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_se ed_err.237833142 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1530938610 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 50123943500 ps |
| CPU time | 875.33 seconds |
| Started | Feb 09 05:34:19 AM UTC 25 |
| Finished | Feb 09 05:49:04 AM UTC 25 |
| Peak memory | 275060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530938610 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.1530938610 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.765520 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2676980500 ps |
| CPU time | 175.95 seconds |
| Started | Feb 09 05:36:05 AM UTC 25 |
| Finished | Feb 09 05:39:04 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765520 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.765520 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2373915332 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 49224940900 ps |
| CPU time | 467.97 seconds |
| Started | Feb 09 05:36:23 AM UTC 25 |
| Finished | Feb 09 05:44:18 AM UTC 25 |
| Peak memory | 303904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2373915332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_int r_rd_slow_flash.2373915332 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.4248121644 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1985780900 ps |
| CPU time | 70.91 seconds |
| Started | Feb 09 05:36:11 AM UTC 25 |
| Finished | Feb 09 05:37:24 AM UTC 25 |
| Peak memory | 275248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248121644 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.4248121644 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2268199179 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 48803302900 ps |
| CPU time | 223.45 seconds |
| Started | Feb 09 05:36:32 AM UTC 25 |
| Finished | Feb 09 05:40:19 AM UTC 25 |
| Peak memory | 275212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2268199179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_intr_wr_slow_flash.2268199179 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3710182852 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1918138900 ps |
| CPU time | 88.37 seconds |
| Started | Feb 09 05:35:03 AM UTC 25 |
| Finished | Feb 09 05:36:33 AM UTC 25 |
| Peak memory | 271012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710182852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3710182852 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3203327039 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 45308600 ps |
| CPU time | 23.28 seconds |
| Started | Feb 09 05:37:24 AM UTC 25 |
| Finished | Feb 09 05:37:49 AM UTC 25 |
| Peak memory | 275612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 03327039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3203327039 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.2253391759 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 44785900700 ps |
| CPU time | 308.03 seconds |
| Started | Feb 09 05:34:27 AM UTC 25 |
| Finished | Feb 09 05:39:39 AM UTC 25 |
| Peak memory | 283440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2253391759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.f lash_ctrl_mp_regions.2253391759 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3762820663 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 40374900 ps |
| CPU time | 175.09 seconds |
| Started | Feb 09 05:34:24 AM UTC 25 |
| Finished | Feb 09 05:37:22 AM UTC 25 |
| Peak memory | 271312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762820663 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.3762820663 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.301598233 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 258225900 ps |
| CPU time | 462.89 seconds |
| Started | Feb 09 05:34:17 AM UTC 25 |
| Finished | Feb 09 05:42:06 AM UTC 25 |
| Peak memory | 275168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301598233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.301598233 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.846134810 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 88899300 ps |
| CPU time | 18.84 seconds |
| Started | Feb 09 05:36:35 AM UTC 25 |
| Finished | Feb 09 05:36:55 AM UTC 25 |
| Peak memory | 275508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846134810 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.846134810 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.3178432804 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 6106904600 ps |
| CPU time | 514.11 seconds |
| Started | Feb 09 05:34:16 AM UTC 25 |
| Finished | Feb 09 05:42:56 AM UTC 25 |
| Peak memory | 291548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178432804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3178432804 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2616529529 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 71816900 ps |
| CPU time | 49.74 seconds |
| Started | Feb 09 05:36:54 AM UTC 25 |
| Finished | Feb 09 05:37:45 AM UTC 25 |
| Peak memory | 285632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616529529 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2616529529 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3839113056 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 476178200 ps |
| CPU time | 101.78 seconds |
| Started | Feb 09 05:35:09 AM UTC 25 |
| Finished | Feb 09 05:36:53 AM UTC 25 |
| Peak memory | 291868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839113 056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.3839113056 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.134790219 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3028062400 ps |
| CPU time | 192.07 seconds |
| Started | Feb 09 05:35:30 AM UTC 25 |
| Finished | Feb 09 05:38:45 AM UTC 25 |
| Peak memory | 291972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=134790219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_ro_derr.134790219 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1660641910 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1075909100 ps |
| CPU time | 160.86 seconds |
| Started | Feb 09 05:35:22 AM UTC 25 |
| Finished | Feb 09 05:38:06 AM UTC 25 |
| Peak memory | 291972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1660641910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1660641910 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2133680243 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4575303500 ps |
| CPU time | 592.77 seconds |
| Started | Feb 09 05:35:14 AM UTC 25 |
| Finished | Feb 09 05:45:14 AM UTC 25 |
| Peak memory | 324788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133680243 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.2133680243 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2211058113 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1309518400 ps |
| CPU time | 214.82 seconds |
| Started | Feb 09 05:35:59 AM UTC 25 |
| Finished | Feb 09 05:39:37 AM UTC 25 |
| Peak memory | 291740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2211058113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ ctrl_rw_derr.2211058113 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3318627889 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 34745900 ps |
| CPU time | 42.7 seconds |
| Started | Feb 09 05:36:42 AM UTC 25 |
| Finished | Feb 09 05:37:26 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318627889 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.3318627889 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.3148965185 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 29170900 ps |
| CPU time | 42.59 seconds |
| Started | Feb 09 05:36:51 AM UTC 25 |
| Finished | Feb 09 05:37:35 AM UTC 25 |
| Peak memory | 285620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148 965185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3148965185 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.4072579532 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 22341459100 ps |
| CPU time | 234.34 seconds |
| Started | Feb 09 05:35:26 AM UTC 25 |
| Finished | Feb 09 05:39:24 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407257953 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.4072579532 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3358628838 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 22967174900 ps |
| CPU time | 72.42 seconds |
| Started | Feb 09 05:37:15 AM UTC 25 |
| Finished | Feb 09 05:38:29 AM UTC 25 |
| Peak memory | 275436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358628838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3358628838 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.452416448 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 36168900 ps |
| CPU time | 58.15 seconds |
| Started | Feb 09 05:34:14 AM UTC 25 |
| Finished | Feb 09 05:35:14 AM UTC 25 |
| Peak memory | 285408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452416448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.452416448 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.3535685247 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2227935600 ps |
| CPU time | 224.49 seconds |
| Started | Feb 09 05:35:05 AM UTC 25 |
| Finished | Feb 09 05:38:53 AM UTC 25 |
| Peak memory | 275500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535685247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.3535685247 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.2146450070 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 36877000 ps |
| CPU time | 22.67 seconds |
| Started | Feb 09 06:23:41 AM UTC 25 |
| Finished | Feb 09 06:24:05 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146450070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2146450070 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.954408443 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 80128200 ps |
| CPU time | 145.4 seconds |
| Started | Feb 09 06:23:41 AM UTC 25 |
| Finished | Feb 09 06:26:08 AM UTC 25 |
| Peak memory | 271216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954408443 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.954408443 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.3437775208 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 23819300 ps |
| CPU time | 21.82 seconds |
| Started | Feb 09 06:23:42 AM UTC 25 |
| Finished | Feb 09 06:24:05 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437775208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3437775208 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.2404495951 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 38173700 ps |
| CPU time | 179.78 seconds |
| Started | Feb 09 06:23:41 AM UTC 25 |
| Finished | Feb 09 06:26:43 AM UTC 25 |
| Peak memory | 275072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404495951 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.2404495951 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.3447004856 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 209650600 ps |
| CPU time | 20.48 seconds |
| Started | Feb 09 06:23:43 AM UTC 25 |
| Finished | Feb 09 06:24:05 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447004856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3447004856 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.4179592912 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 195460700 ps |
| CPU time | 157.56 seconds |
| Started | Feb 09 06:23:43 AM UTC 25 |
| Finished | Feb 09 06:26:23 AM UTC 25 |
| Peak memory | 275604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179592912 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.4179592912 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.2320126339 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 49499600 ps |
| CPU time | 16.47 seconds |
| Started | Feb 09 06:23:47 AM UTC 25 |
| Finished | Feb 09 06:24:05 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320126339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2320126339 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.4230574216 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 657705100 ps |
| CPU time | 133.9 seconds |
| Started | Feb 09 06:23:43 AM UTC 25 |
| Finished | Feb 09 06:25:59 AM UTC 25 |
| Peak memory | 271232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230574216 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.4230574216 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.758355691 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 22692200 ps |
| CPU time | 23.49 seconds |
| Started | Feb 09 06:23:49 AM UTC 25 |
| Finished | Feb 09 06:24:14 AM UTC 25 |
| Peak memory | 295104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758355691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.758355691 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.2193721811 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 303518900 ps |
| CPU time | 159.68 seconds |
| Started | Feb 09 06:23:48 AM UTC 25 |
| Finished | Feb 09 06:26:31 AM UTC 25 |
| Peak memory | 270976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193721811 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.2193721811 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.1293336540 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 14076200 ps |
| CPU time | 22.22 seconds |
| Started | Feb 09 06:23:51 AM UTC 25 |
| Finished | Feb 09 06:24:15 AM UTC 25 |
| Peak memory | 295028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293336540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1293336540 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.4042369093 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 38571700 ps |
| CPU time | 160.57 seconds |
| Started | Feb 09 06:23:50 AM UTC 25 |
| Finished | Feb 09 06:26:34 AM UTC 25 |
| Peak memory | 275328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042369093 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.4042369093 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.1424804036 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 13313400 ps |
| CPU time | 26.25 seconds |
| Started | Feb 09 06:23:54 AM UTC 25 |
| Finished | Feb 09 06:24:21 AM UTC 25 |
| Peak memory | 284980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424804036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1424804036 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.327537201 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 39135600 ps |
| CPU time | 165.91 seconds |
| Started | Feb 09 06:23:52 AM UTC 25 |
| Finished | Feb 09 06:26:41 AM UTC 25 |
| Peak memory | 271040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327537201 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.327537201 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.3350586856 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 130111500 ps |
| CPU time | 24.7 seconds |
| Started | Feb 09 06:23:59 AM UTC 25 |
| Finished | Feb 09 06:24:25 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350586856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3350586856 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3811484158 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 108453200 ps |
| CPU time | 165.55 seconds |
| Started | Feb 09 06:23:55 AM UTC 25 |
| Finished | Feb 09 06:26:43 AM UTC 25 |
| Peak memory | 271164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811484158 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.3811484158 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3116290662 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 29136800 ps |
| CPU time | 27.43 seconds |
| Started | Feb 09 06:24:01 AM UTC 25 |
| Finished | Feb 09 06:24:30 AM UTC 25 |
| Peak memory | 294928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116290662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3116290662 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.592157261 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 36260000 ps |
| CPU time | 152.33 seconds |
| Started | Feb 09 06:24:00 AM UTC 25 |
| Finished | Feb 09 06:26:35 AM UTC 25 |
| Peak memory | 275264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592157261 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.592157261 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.1608558098 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 58897400 ps |
| CPU time | 15.74 seconds |
| Started | Feb 09 06:24:01 AM UTC 25 |
| Finished | Feb 09 06:24:18 AM UTC 25 |
| Peak memory | 295224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608558098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1608558098 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1500603762 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 147018300 ps |
| CPU time | 175.77 seconds |
| Started | Feb 09 06:24:01 AM UTC 25 |
| Finished | Feb 09 06:27:00 AM UTC 25 |
| Peak memory | 270756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500603762 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.1500603762 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1217918111 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 125870400 ps |
| CPU time | 19.21 seconds |
| Started | Feb 09 05:42:33 AM UTC 25 |
| Finished | Feb 09 05:42:54 AM UTC 25 |
| Peak memory | 275212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217918111 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1217918111 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.3264706945 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 17498600 ps |
| CPU time | 24.06 seconds |
| Started | Feb 09 05:42:07 AM UTC 25 |
| Finished | Feb 09 05:42:32 AM UTC 25 |
| Peak memory | 295164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264706945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.3264706945 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3545955439 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 64042900 ps |
| CPU time | 44.18 seconds |
| Started | Feb 09 05:41:45 AM UTC 25 |
| Finished | Feb 09 05:42:30 AM UTC 25 |
| Peak memory | 285516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 45955439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.3545955439 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3529407269 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 5504164800 ps |
| CPU time | 2697.6 seconds |
| Started | Feb 09 05:38:46 AM UTC 25 |
| Finished | Feb 09 06:24:11 AM UTC 25 |
| Peak memory | 273140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529407269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3529407269 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3520339977 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2354777900 ps |
| CPU time | 1097.94 seconds |
| Started | Feb 09 05:38:34 AM UTC 25 |
| Finished | Feb 09 05:57:04 AM UTC 25 |
| Peak memory | 285416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520339977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3520339977 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1730228997 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 38842800 ps |
| CPU time | 23.47 seconds |
| Started | Feb 09 05:42:31 AM UTC 25 |
| Finished | Feb 09 05:42:56 AM UTC 25 |
| Peak memory | 269144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 30228997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_s eed_err.1730228997 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1584367211 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 80136286500 ps |
| CPU time | 817.39 seconds |
| Started | Feb 09 05:38:04 AM UTC 25 |
| Finished | Feb 09 05:51:50 AM UTC 25 |
| Peak memory | 275080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584367211 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.1584367211 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1368473382 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 9388804900 ps |
| CPU time | 196.3 seconds |
| Started | Feb 09 05:37:50 AM UTC 25 |
| Finished | Feb 09 05:41:09 AM UTC 25 |
| Peak memory | 272996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368473382 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.1368473382 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.4147782298 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 7868324900 ps |
| CPU time | 216.81 seconds |
| Started | Feb 09 05:40:06 AM UTC 25 |
| Finished | Feb 09 05:43:46 AM UTC 25 |
| Peak memory | 293984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147782298 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.4147782298 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1737856226 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 12649660700 ps |
| CPU time | 319.57 seconds |
| Started | Feb 09 05:40:20 AM UTC 25 |
| Finished | Feb 09 05:45:44 AM UTC 25 |
| Peak memory | 301860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1737856226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_int r_rd_slow_flash.1737856226 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3276481197 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3539505300 ps |
| CPU time | 83.93 seconds |
| Started | Feb 09 05:40:18 AM UTC 25 |
| Finished | Feb 09 05:41:44 AM UTC 25 |
| Peak memory | 271128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276481197 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.3276481197 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2999967893 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 20929341300 ps |
| CPU time | 218.6 seconds |
| Started | Feb 09 05:40:43 AM UTC 25 |
| Finished | Feb 09 05:44:25 AM UTC 25 |
| Peak memory | 271112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2999967893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_intr_wr_slow_flash.2999967893 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.903719048 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 28840581700 ps |
| CPU time | 106.9 seconds |
| Started | Feb 09 05:38:53 AM UTC 25 |
| Finished | Feb 09 05:40:43 AM UTC 25 |
| Peak memory | 271004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903719048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.903719048 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3115244038 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 26234700 ps |
| CPU time | 23.18 seconds |
| Started | Feb 09 05:42:17 AM UTC 25 |
| Finished | Feb 09 05:42:42 AM UTC 25 |
| Peak memory | 275292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 15244038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3115244038 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3311223127 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 7269589900 ps |
| CPU time | 522.35 seconds |
| Started | Feb 09 05:38:07 AM UTC 25 |
| Finished | Feb 09 05:46:56 AM UTC 25 |
| Peak memory | 283412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3311223127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.f lash_ctrl_mp_regions.3311223127 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1031561100 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 245341700 ps |
| CPU time | 261.97 seconds |
| Started | Feb 09 05:38:04 AM UTC 25 |
| Finished | Feb 09 05:42:30 AM UTC 25 |
| Peak memory | 275216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031561100 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.1031561100 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.836004219 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 343299400 ps |
| CPU time | 675.99 seconds |
| Started | Feb 09 05:37:50 AM UTC 25 |
| Finished | Feb 09 05:49:14 AM UTC 25 |
| Peak memory | 273376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836004219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.836004219 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.361654563 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 132250900 ps |
| CPU time | 27.19 seconds |
| Started | Feb 09 05:41:10 AM UTC 25 |
| Finished | Feb 09 05:41:39 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361654563 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.361654563 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.522844961 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 7719202400 ps |
| CPU time | 1825 seconds |
| Started | Feb 09 05:37:47 AM UTC 25 |
| Finished | Feb 09 06:08:31 AM UTC 25 |
| Peak memory | 297696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522844961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.522844961 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.21480838 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 126252700 ps |
| CPU time | 64.02 seconds |
| Started | Feb 09 05:41:40 AM UTC 25 |
| Finished | Feb 09 05:42:45 AM UTC 25 |
| Peak memory | 287588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21480838 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.21480838 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.520261401 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 540370200 ps |
| CPU time | 150.93 seconds |
| Started | Feb 09 05:39:05 AM UTC 25 |
| Finished | Feb 09 05:41:38 AM UTC 25 |
| Peak memory | 291612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5202614 01 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.520261401 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3766985734 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2540403000 ps |
| CPU time | 153.3 seconds |
| Started | Feb 09 05:39:40 AM UTC 25 |
| Finished | Feb 09 05:42:16 AM UTC 25 |
| Peak memory | 291972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3766985734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_ro_derr.3766985734 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.897243952 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1394111000 ps |
| CPU time | 130.75 seconds |
| Started | Feb 09 05:39:25 AM UTC 25 |
| Finished | Feb 09 05:41:38 AM UTC 25 |
| Peak memory | 306056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=897243952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.897243952 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.3348449129 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3769292300 ps |
| CPU time | 474.76 seconds |
| Started | Feb 09 05:39:18 AM UTC 25 |
| Finished | Feb 09 05:47:18 AM UTC 25 |
| Peak memory | 332656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348449129 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.3348449129 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3253992254 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 3987423700 ps |
| CPU time | 194.72 seconds |
| Started | Feb 09 05:39:49 AM UTC 25 |
| Finished | Feb 09 05:43:06 AM UTC 25 |
| Peak memory | 302152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3253992254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ ctrl_rw_derr.3253992254 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.1941461219 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 64086800 ps |
| CPU time | 51.82 seconds |
| Started | Feb 09 05:41:38 AM UTC 25 |
| Finished | Feb 09 05:42:32 AM UTC 25 |
| Peak memory | 287644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941461219 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.1941461219 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.361209234 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 69905300 ps |
| CPU time | 53.59 seconds |
| Started | Feb 09 05:41:40 AM UTC 25 |
| Finished | Feb 09 05:42:35 AM UTC 25 |
| Peak memory | 277308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612 09234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.361209234 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.3720641123 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3286827300 ps |
| CPU time | 182.95 seconds |
| Started | Feb 09 05:39:38 AM UTC 25 |
| Finished | Feb 09 05:42:44 AM UTC 25 |
| Peak memory | 306084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372064112 3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.3720641123 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2876516076 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1928289800 ps |
| CPU time | 86.17 seconds |
| Started | Feb 09 05:41:50 AM UTC 25 |
| Finished | Feb 09 05:43:18 AM UTC 25 |
| Peak memory | 275372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876516076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2876516076 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.4119097794 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 75000200 ps |
| CPU time | 137.99 seconds |
| Started | Feb 09 05:37:44 AM UTC 25 |
| Finished | Feb 09 05:40:05 AM UTC 25 |
| Peak memory | 287580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119097794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.4119097794 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1726550940 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 11706905400 ps |
| CPU time | 276.29 seconds |
| Started | Feb 09 05:38:58 AM UTC 25 |
| Finished | Feb 09 05:43:39 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726550940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.1726550940 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.291200932 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 18805200 ps |
| CPU time | 23.94 seconds |
| Started | Feb 09 06:24:02 AM UTC 25 |
| Finished | Feb 09 06:24:28 AM UTC 25 |
| Peak memory | 295208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291200932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.291200932 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1108486178 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 77763300 ps |
| CPU time | 163.47 seconds |
| Started | Feb 09 06:24:02 AM UTC 25 |
| Finished | Feb 09 06:26:49 AM UTC 25 |
| Peak memory | 275276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108486178 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.1108486178 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.1671406826 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 13762400 ps |
| CPU time | 19.88 seconds |
| Started | Feb 09 06:24:06 AM UTC 25 |
| Finished | Feb 09 06:24:27 AM UTC 25 |
| Peak memory | 284852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671406826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1671406826 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2377668384 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 152942600 ps |
| CPU time | 167.08 seconds |
| Started | Feb 09 06:24:02 AM UTC 25 |
| Finished | Feb 09 06:26:52 AM UTC 25 |
| Peak memory | 275460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377668384 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.2377668384 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.1471749942 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 24230500 ps |
| CPU time | 25.61 seconds |
| Started | Feb 09 06:24:06 AM UTC 25 |
| Finished | Feb 09 06:24:33 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471749942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1471749942 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.15569815 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 74831200 ps |
| CPU time | 153.79 seconds |
| Started | Feb 09 06:24:06 AM UTC 25 |
| Finished | Feb 09 06:26:42 AM UTC 25 |
| Peak memory | 271168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15569815 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.15569815 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.2800506987 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 53942700 ps |
| CPU time | 17.11 seconds |
| Started | Feb 09 06:24:06 AM UTC 25 |
| Finished | Feb 09 06:24:24 AM UTC 25 |
| Peak memory | 295288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800506987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2800506987 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1834606824 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 121517800 ps |
| CPU time | 170.26 seconds |
| Started | Feb 09 06:24:06 AM UTC 25 |
| Finished | Feb 09 06:26:59 AM UTC 25 |
| Peak memory | 270972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834606824 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.1834606824 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3212467014 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 24826300 ps |
| CPU time | 19.64 seconds |
| Started | Feb 09 06:24:10 AM UTC 25 |
| Finished | Feb 09 06:24:31 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212467014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3212467014 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3917519573 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 43285600 ps |
| CPU time | 155.04 seconds |
| Started | Feb 09 06:24:07 AM UTC 25 |
| Finished | Feb 09 06:26:45 AM UTC 25 |
| Peak memory | 271124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917519573 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.3917519573 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.4119755843 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 15149900 ps |
| CPU time | 17.43 seconds |
| Started | Feb 09 06:24:12 AM UTC 25 |
| Finished | Feb 09 06:24:31 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119755843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.4119755843 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1316818793 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 71092500 ps |
| CPU time | 139.51 seconds |
| Started | Feb 09 06:24:12 AM UTC 25 |
| Finished | Feb 09 06:26:34 AM UTC 25 |
| Peak memory | 275152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316818793 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.1316818793 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.330822351 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 63688300 ps |
| CPU time | 27.12 seconds |
| Started | Feb 09 06:24:15 AM UTC 25 |
| Finished | Feb 09 06:24:44 AM UTC 25 |
| Peak memory | 295028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330822351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.330822351 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3899845227 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 602896600 ps |
| CPU time | 129.17 seconds |
| Started | Feb 09 06:24:13 AM UTC 25 |
| Finished | Feb 09 06:26:25 AM UTC 25 |
| Peak memory | 270976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899845227 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.3899845227 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3083909767 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 26515100 ps |
| CPU time | 20.74 seconds |
| Started | Feb 09 06:24:17 AM UTC 25 |
| Finished | Feb 09 06:24:39 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083909767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3083909767 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1848418725 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 75058100 ps |
| CPU time | 175.36 seconds |
| Started | Feb 09 06:24:16 AM UTC 25 |
| Finished | Feb 09 06:27:14 AM UTC 25 |
| Peak memory | 271168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848418725 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.1848418725 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.300493382 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 21685200 ps |
| CPU time | 24.42 seconds |
| Started | Feb 09 06:24:22 AM UTC 25 |
| Finished | Feb 09 06:24:48 AM UTC 25 |
| Peak memory | 295092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300493382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.300493382 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2476345479 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 737978100 ps |
| CPU time | 160.86 seconds |
| Started | Feb 09 06:24:19 AM UTC 25 |
| Finished | Feb 09 06:27:02 AM UTC 25 |
| Peak memory | 271232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476345479 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.2476345479 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.3697486343 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 45130900 ps |
| CPU time | 23.8 seconds |
| Started | Feb 09 06:24:25 AM UTC 25 |
| Finished | Feb 09 06:24:50 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697486343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3697486343 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1449571536 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 79698300 ps |
| CPU time | 175.33 seconds |
| Started | Feb 09 06:24:23 AM UTC 25 |
| Finished | Feb 09 06:27:21 AM UTC 25 |
| Peak memory | 271252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449571536 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.1449571536 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.436533590 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 56051100 ps |
| CPU time | 17.68 seconds |
| Started | Feb 09 05:46:07 AM UTC 25 |
| Finished | Feb 09 05:46:26 AM UTC 25 |
| Peak memory | 275212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436533590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.436533590 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.2909538835 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 46879700 ps |
| CPU time | 17.82 seconds |
| Started | Feb 09 05:45:47 AM UTC 25 |
| Finished | Feb 09 05:46:06 AM UTC 25 |
| Peak memory | 295292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909538835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2909538835 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2759459571 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 20697500 ps |
| CPU time | 44.4 seconds |
| Started | Feb 09 05:45:29 AM UTC 25 |
| Finished | Feb 09 05:46:15 AM UTC 25 |
| Peak memory | 285772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 59459571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.2759459571 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1773950233 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3788087000 ps |
| CPU time | 3018.12 seconds |
| Started | Feb 09 05:43:19 AM UTC 25 |
| Finished | Feb 09 06:34:08 AM UTC 25 |
| Peak memory | 277960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773950233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_er ror_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.1773950233 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3857816403 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 323831400 ps |
| CPU time | 1220.59 seconds |
| Started | Feb 09 05:43:07 AM UTC 25 |
| Finished | Feb 09 06:03:43 AM UTC 25 |
| Peak memory | 285416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857816403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3857816403 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.1249393651 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 382683800 ps |
| CPU time | 31.5 seconds |
| Started | Feb 09 05:42:57 AM UTC 25 |
| Finished | Feb 09 05:43:31 AM UTC 25 |
| Peak memory | 275376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249393651 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.1249393651 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.356058189 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 10032083600 ps |
| CPU time | 74.94 seconds |
| Started | Feb 09 05:46:07 AM UTC 25 |
| Finished | Feb 09 05:47:24 AM UTC 25 |
| Peak memory | 301936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=356058189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_hw_prog_rma_wipe_err.356058189 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1606671283 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 109146600 ps |
| CPU time | 29.03 seconds |
| Started | Feb 09 05:45:53 AM UTC 25 |
| Finished | Feb 09 05:46:23 AM UTC 25 |
| Peak memory | 275260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 06671283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_s eed_err.1606671283 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.3502534105 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 40120293400 ps |
| CPU time | 741.62 seconds |
| Started | Feb 09 05:42:47 AM UTC 25 |
| Finished | Feb 09 05:55:17 AM UTC 25 |
| Peak memory | 275084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502534105 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.3502534105 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.2378112034 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 26266346100 ps |
| CPU time | 124.56 seconds |
| Started | Feb 09 05:42:46 AM UTC 25 |
| Finished | Feb 09 05:44:53 AM UTC 25 |
| Peak memory | 275044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378112034 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.2378112034 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1645446989 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 562860600 ps |
| CPU time | 127.36 seconds |
| Started | Feb 09 05:44:26 AM UTC 25 |
| Finished | Feb 09 05:46:36 AM UTC 25 |
| Peak memory | 303904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645446989 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.1645446989 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3121575126 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 26754426500 ps |
| CPU time | 345.16 seconds |
| Started | Feb 09 05:44:54 AM UTC 25 |
| Finished | Feb 09 05:50:44 AM UTC 25 |
| Peak memory | 301820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3121575126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_int r_rd_slow_flash.3121575126 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.1124403660 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4381163500 ps |
| CPU time | 80.93 seconds |
| Started | Feb 09 05:44:26 AM UTC 25 |
| Finished | Feb 09 05:45:50 AM UTC 25 |
| Peak memory | 275160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124403660 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.1124403660 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2428642990 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 88595614200 ps |
| CPU time | 318.24 seconds |
| Started | Feb 09 05:44:55 AM UTC 25 |
| Finished | Feb 09 05:50:18 AM UTC 25 |
| Peak memory | 271296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2428642990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_intr_wr_slow_flash.2428642990 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3900904703 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1082309000 ps |
| CPU time | 63.7 seconds |
| Started | Feb 09 05:43:20 AM UTC 25 |
| Finished | Feb 09 05:44:25 AM UTC 25 |
| Peak memory | 273052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900904703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3900904703 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.33853163 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 26669400 ps |
| CPU time | 21.86 seconds |
| Started | Feb 09 05:45:51 AM UTC 25 |
| Finished | Feb 09 05:46:14 AM UTC 25 |
| Peak memory | 275324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 853163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.33853163 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.4031398031 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 56297779400 ps |
| CPU time | 984.6 seconds |
| Started | Feb 09 05:42:57 AM UTC 25 |
| Finished | Feb 09 05:59:33 AM UTC 25 |
| Peak memory | 283416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4031398031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.f lash_ctrl_mp_regions.4031398031 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.50818696 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 59883400 ps |
| CPU time | 84.91 seconds |
| Started | Feb 09 05:42:42 AM UTC 25 |
| Finished | Feb 09 05:44:09 AM UTC 25 |
| Peak memory | 275120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50818696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.50818696 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.41902400 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 33871600 ps |
| CPU time | 21.05 seconds |
| Started | Feb 09 05:45:06 AM UTC 25 |
| Finished | Feb 09 05:45:29 AM UTC 25 |
| Peak memory | 275184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41902400 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.41902400 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.1429331847 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 119247400 ps |
| CPU time | 153.01 seconds |
| Started | Feb 09 05:42:35 AM UTC 25 |
| Finished | Feb 09 05:45:11 AM UTC 25 |
| Peak memory | 281308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429331847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1429331847 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.21545371 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 309472200 ps |
| CPU time | 52.11 seconds |
| Started | Feb 09 05:45:15 AM UTC 25 |
| Finished | Feb 09 05:46:09 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21545371 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.21545371 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.286800780 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1859943700 ps |
| CPU time | 91.1 seconds |
| Started | Feb 09 05:43:32 AM UTC 25 |
| Finished | Feb 09 05:45:05 AM UTC 25 |
| Peak memory | 291604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868007 80 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.286800780 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.3384661395 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 661281800 ps |
| CPU time | 156.46 seconds |
| Started | Feb 09 05:44:10 AM UTC 25 |
| Finished | Feb 09 05:46:50 AM UTC 25 |
| Peak memory | 291972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3384661395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_ro_derr.3384661395 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.2746892289 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 626393800 ps |
| CPU time | 164.31 seconds |
| Started | Feb 09 05:43:46 AM UTC 25 |
| Finished | Feb 09 05:46:34 AM UTC 25 |
| Peak memory | 306052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2746892289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2746892289 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.1929803704 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 6849436600 ps |
| CPU time | 462.36 seconds |
| Started | Feb 09 05:43:40 AM UTC 25 |
| Finished | Feb 09 05:51:29 AM UTC 25 |
| Peak memory | 320348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929803704 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.1929803704 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.2025890409 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1538043700 ps |
| CPU time | 195.34 seconds |
| Started | Feb 09 05:44:18 AM UTC 25 |
| Finished | Feb 09 05:47:37 AM UTC 25 |
| Peak memory | 294024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2025890409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ ctrl_rw_derr.2025890409 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3647527743 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 34693000 ps |
| CPU time | 37.73 seconds |
| Started | Feb 09 05:45:12 AM UTC 25 |
| Finished | Feb 09 05:45:52 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647527743 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.3647527743 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.387289585 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 35301300 ps |
| CPU time | 51.44 seconds |
| Started | Feb 09 05:45:12 AM UTC 25 |
| Finished | Feb 09 05:46:06 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872 89585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.387289585 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.640802617 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 3271447000 ps |
| CPU time | 214.96 seconds |
| Started | Feb 09 05:44:10 AM UTC 25 |
| Finished | Feb 09 05:47:49 AM UTC 25 |
| Peak memory | 291748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640802617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.640802617 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.493685556 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 32726846300 ps |
| CPU time | 100.52 seconds |
| Started | Feb 09 05:45:44 AM UTC 25 |
| Finished | Feb 09 05:47:27 AM UTC 25 |
| Peak memory | 275116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493685556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.493685556 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3330017794 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 58817300 ps |
| CPU time | 266.02 seconds |
| Started | Feb 09 05:42:33 AM UTC 25 |
| Finished | Feb 09 05:47:03 AM UTC 25 |
| Peak memory | 291536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330017794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3330017794 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3412996276 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3748631100 ps |
| CPU time | 182.68 seconds |
| Started | Feb 09 05:43:28 AM UTC 25 |
| Finished | Feb 09 05:46:34 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412996276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.3412996276 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2037359694 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 18800300 ps |
| CPU time | 16.07 seconds |
| Started | Feb 09 05:49:37 AM UTC 25 |
| Finished | Feb 09 05:49:54 AM UTC 25 |
| Peak memory | 275228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037359694 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2037359694 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.1251087461 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 186198100 ps |
| CPU time | 24.94 seconds |
| Started | Feb 09 05:49:14 AM UTC 25 |
| Finished | Feb 09 05:49:41 AM UTC 25 |
| Peak memory | 295096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251087461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1251087461 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2976659198 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 13833700 ps |
| CPU time | 41.84 seconds |
| Started | Feb 09 05:49:05 AM UTC 25 |
| Finished | Feb 09 05:49:49 AM UTC 25 |
| Peak memory | 285548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 76659198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.2976659198 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.961007066 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 1421916500 ps |
| CPU time | 3029.48 seconds |
| Started | Feb 09 05:46:56 AM UTC 25 |
| Finished | Feb 09 06:37:57 AM UTC 25 |
| Peak memory | 275900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_ on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961007066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_err or_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 9.flash_ctrl_error_mp.961007066 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.1477827207 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 731716100 ps |
| CPU time | 1172.18 seconds |
| Started | Feb 09 05:46:51 AM UTC 25 |
| Finished | Feb 09 06:06:37 AM UTC 25 |
| Peak memory | 283364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477827207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1477827207 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.4224637045 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 604339400 ps |
| CPU time | 38.11 seconds |
| Started | Feb 09 05:46:37 AM UTC 25 |
| Finished | Feb 09 05:47:17 AM UTC 25 |
| Peak memory | 273112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224637045 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.4224637045 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4083264908 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 10034532100 ps |
| CPU time | 107.77 seconds |
| Started | Feb 09 05:49:36 AM UTC 25 |
| Finished | Feb 09 05:51:26 AM UTC 25 |
| Peak memory | 301940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_ale rt_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4083264908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.flash_ctrl_hw_prog_rma_wipe_err.4083264908 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3084487135 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 67184400 ps |
| CPU time | 23.35 seconds |
| Started | Feb 09 05:49:36 AM UTC 25 |
| Finished | Feb 09 05:50:00 AM UTC 25 |
| Peak memory | 275304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 84487135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_s eed_err.3084487135 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.4023956237 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 40121685300 ps |
| CPU time | 797.06 seconds |
| Started | Feb 09 05:46:26 AM UTC 25 |
| Finished | Feb 09 05:59:53 AM UTC 25 |
| Peak memory | 275072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023956237 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.4023956237 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.2657302297 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1552500600 ps |
| CPU time | 83.17 seconds |
| Started | Feb 09 05:46:24 AM UTC 25 |
| Finished | Feb 09 05:47:49 AM UTC 25 |
| Peak memory | 271204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657302297 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.2657302297 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1895317727 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2058964300 ps |
| CPU time | 162.19 seconds |
| Started | Feb 09 05:47:46 AM UTC 25 |
| Finished | Feb 09 05:50:31 AM UTC 25 |
| Peak memory | 306048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895317727 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.1895317727 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2753688049 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 8768564800 ps |
| CPU time | 217.16 seconds |
| Started | Feb 09 05:47:50 AM UTC 25 |
| Finished | Feb 09 05:51:31 AM UTC 25 |
| Peak memory | 307752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_n s=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2753688049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_int r_rd_slow_flash.2753688049 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2062866862 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4895472400 ps |
| CPU time | 102.06 seconds |
| Started | Feb 09 05:47:50 AM UTC 25 |
| Finished | Feb 09 05:49:35 AM UTC 25 |
| Peak memory | 275068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062866862 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.2062866862 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.866394117 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 24489445600 ps |
| CPU time | 347.5 seconds |
| Started | Feb 09 05:47:59 AM UTC 25 |
| Finished | Feb 09 05:53:51 AM UTC 25 |
| Peak memory | 271112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=5 00_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=866394117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.flash_ctrl_intr_wr_slow_flash.866394117 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.3979473387 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2727387200 ps |
| CPU time | 58.48 seconds |
| Started | Feb 09 05:46:57 AM UTC 25 |
| Finished | Feb 09 05:47:58 AM UTC 25 |
| Peak memory | 271004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979473387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3979473387 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1511640270 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 44934400 ps |
| CPU time | 20.46 seconds |
| Started | Feb 09 05:49:25 AM UTC 25 |
| Finished | Feb 09 05:49:47 AM UTC 25 |
| Peak memory | 275548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 11640270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1511640270 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1676050775 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 12275289800 ps |
| CPU time | 883.91 seconds |
| Started | Feb 09 05:46:35 AM UTC 25 |
| Finished | Feb 09 06:01:29 AM UTC 25 |
| Peak memory | 283416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readon ly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1676050775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.f lash_ctrl_mp_regions.1676050775 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3157756645 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 70745400 ps |
| CPU time | 154.54 seconds |
| Started | Feb 09 05:46:34 AM UTC 25 |
| Finished | Feb 09 05:49:12 AM UTC 25 |
| Peak memory | 275068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157756645 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.3157756645 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.860086885 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 837341300 ps |
| CPU time | 426.44 seconds |
| Started | Feb 09 05:46:16 AM UTC 25 |
| Finished | Feb 09 05:53:28 AM UTC 25 |
| Peak memory | 273116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860086885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.860086885 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1149068756 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 33470900 ps |
| CPU time | 27.41 seconds |
| Started | Feb 09 05:48:21 AM UTC 25 |
| Finished | Feb 09 05:48:50 AM UTC 25 |
| Peak memory | 275188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149068756 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.1149068756 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.301163234 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 136244300 ps |
| CPU time | 1270.46 seconds |
| Started | Feb 09 05:46:15 AM UTC 25 |
| Finished | Feb 09 06:07:39 AM UTC 25 |
| Peak memory | 291552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301163234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.301163234 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.414316615 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 274125200 ps |
| CPU time | 57.39 seconds |
| Started | Feb 09 05:49:02 AM UTC 25 |
| Finished | Feb 09 05:50:01 AM UTC 25 |
| Peak memory | 287640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414316615 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.414316615 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2421299324 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2119862200 ps |
| CPU time | 106.14 seconds |
| Started | Feb 09 05:47:13 AM UTC 25 |
| Finished | Feb 09 05:49:02 AM UTC 25 |
| Peak memory | 291748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421299 324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.2421299324 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.185868130 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1970401600 ps |
| CPU time | 141.84 seconds |
| Started | Feb 09 05:47:28 AM UTC 25 |
| Finished | Feb 09 05:49:53 AM UTC 25 |
| Peak memory | 291716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=185868130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_ro_derr.185868130 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3989389798 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1073583000 ps |
| CPU time | 133.44 seconds |
| Started | Feb 09 05:47:20 AM UTC 25 |
| Finished | Feb 09 05:49:36 AM UTC 25 |
| Peak memory | 292036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_ pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3989389798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3989389798 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.3540837786 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 15911065600 ps |
| CPU time | 551.03 seconds |
| Started | Feb 09 05:47:18 AM UTC 25 |
| Finished | Feb 09 05:56:36 AM UTC 25 |
| Peak memory | 330680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540837786 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.3540837786 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2844858786 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2387262200 ps |
| CPU time | 233.02 seconds |
| Started | Feb 09 05:47:38 AM UTC 25 |
| Finished | Feb 09 05:51:35 AM UTC 25 |
| Peak memory | 295840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_ alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2844858786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ ctrl_rw_derr.2844858786 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.864702890 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 105810000 ps |
| CPU time | 41.57 seconds |
| Started | Feb 09 05:48:55 AM UTC 25 |
| Finished | Feb 09 05:49:38 AM UTC 25 |
| Peak memory | 281496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8647 02890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.864702890 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3369979969 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1460433100 ps |
| CPU time | 65.53 seconds |
| Started | Feb 09 05:49:12 AM UTC 25 |
| Finished | Feb 09 05:50:20 AM UTC 25 |
| Peak memory | 275112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369979969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3369979969 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3578949657 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 77025200 ps |
| CPU time | 161.08 seconds |
| Started | Feb 09 05:46:10 AM UTC 25 |
| Finished | Feb 09 05:48:54 AM UTC 25 |
| Peak memory | 287448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578949657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3578949657 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2943770757 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4800875100 ps |
| CPU time | 137.99 seconds |
| Started | Feb 09 05:47:03 AM UTC 25 |
| Finished | Feb 09 05:49:25 AM UTC 25 |
| Peak memory | 275220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943770757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.2943770757 |
| Directory | /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest |
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