Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.73	95.23	93.61	97.22	91.84	97.05	97.00	98.18

Total test records in report: 1263

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T279	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1311946527			Oct 15 07:56:37 AM UTC 24	Oct 15 08:17:08 AM UTC 24	677669800 ps
T278	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1040635435			Oct 15 07:55:34 AM UTC 24	Oct 15 08:17:09 AM UTC 24	1089300200 ps
T378	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3078473865			Oct 15 08:00:32 AM UTC 24	Oct 15 08:17:28 AM UTC 24	1341756100 ps
T374	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1523001392			Oct 15 07:59:07 AM UTC 24	Oct 15 08:18:15 AM UTC 24	2031353300 ps
T379	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.622436909			Oct 15 08:00:57 AM UTC 24	Oct 15 08:19:20 AM UTC 24	373600200 ps
T275	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3393040884			Oct 15 08:04:35 AM UTC 24	Oct 15 08:20:06 AM UTC 24	930092300 ps
T276	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2350634317			Oct 15 08:01:37 AM UTC 24	Oct 15 08:20:58 AM UTC 24	784974800 ps
T1261	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1122087714			Oct 15 08:02:29 AM UTC 24	Oct 15 08:22:46 AM UTC 24	2673463500 ps
T1262	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.842554659			Oct 15 08:01:10 AM UTC 24	Oct 15 08:22:51 AM UTC 24	4321141900 ps
T376	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3787835457			Oct 15 08:02:04 AM UTC 24	Oct 15 08:23:32 AM UTC 24	2759200900 ps
T381	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2699388948			Oct 15 08:03:01 AM UTC 24	Oct 15 08:26:06 AM UTC 24	3953850200 ps
T380	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1461097402			Oct 15 08:04:57 AM UTC 24	Oct 15 08:26:25 AM UTC 24	7303226900 ps
T1263	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1920094987			Oct 15 08:03:27 AM UTC 24	Oct 15 08:27:29 AM UTC 24	3432642600 ps

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.2676791039
Short name	T18
Test name
Test status
Simulation time	4888018900 ps
CPU time	97.58 seconds
Started	Oct 15 08:18:16 AM UTC 24
Finished	Oct 15 08:19:55 AM UTC 24
Peak memory	274888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676791039 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2676791039
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2191723950
Short name	T11
Test name
Test status
Simulation time	463444400 ps
CPU time	52.37 seconds
Started	Oct 15 08:19:53 AM UTC 24
Finished	Oct 15 08:20:47 AM UTC 24
Peak memory	285380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 91723950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se rr_counter.2191723950
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3812869772
Short name	T132
Test name
Test status
Simulation time	374755600 ps
CPU time	34 seconds
Started	Oct 15 07:56:29 AM UTC 24
Finished	Oct 15 07:57:04 AM UTC 24
Peak memory	286720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3812869772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3812869772
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.782205732
Short name	T37
Test name
Test status
Simulation time	37706631800 ps
CPU time	201.04 seconds
Started	Oct 15 08:17:30 AM UTC 24
Finished	Oct 15 08:20:54 AM UTC 24
Peak memory	274956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=782205732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_mp_regions.782205732
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.44687840
Short name	T4
Test name
Test status
Simulation time	43043400 ps
CPU time	167.72 seconds
Started	Oct 15 08:17:18 AM UTC 24
Finished	Oct 15 08:20:09 AM UTC 24
Peak memory	271112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44687840 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.44687840
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3105928101
Short name	T90
Test name
Test status
Simulation time	1521918800 ps
CPU time	203.45 seconds
Started	Oct 15 08:20:13 AM UTC 24
Finished	Oct 15 08:23:39 AM UTC 24
Peak memory	289472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3105928101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.3105928101
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2400088996
Short name	T30
Test name
Test status
Simulation time	40211578400 ps
CPU time	851.82 seconds
Started	Oct 15 08:22:15 AM UTC 24
Finished	Oct 15 08:36:37 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2400088996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. flash_ctrl_rma_err.2400088996
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.847055784
Short name	T12
Test name
Test status
Simulation time	1044946000 ps
CPU time	6343.52 seconds
Started	Oct 15 08:21:23 AM UTC 24
Finished	Oct 15 10:08:16 AM UTC 24
Peak memory	309900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847055784 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.847055784
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2528416524
Short name	T386
Test name
Test status
Simulation time	660484500 ps
CPU time	84.68 seconds
Started	Oct 15 07:58:03 AM UTC 24
Finished	Oct 15 07:59:30 AM UTC 24
Peak memory	274376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528416524 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.2528416524
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3011563006
Short name	T34
Test name
Test status
Simulation time	1424636800 ps
CPU time	503.74 seconds
Started	Oct 15 08:17:09 AM UTC 24
Finished	Oct 15 08:25:40 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011563006 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3011563006
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2344860441
Short name	T83
Test name
Test status
Simulation time	19600796400 ps
CPU time	234.94 seconds
Started	Oct 15 08:20:49 AM UTC 24
Finished	Oct 15 08:24:47 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2344860441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_intr_rd_slow_flash.2344860441
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2579553180
Short name	T80
Test name
Test status
Simulation time	338172400 ps
CPU time	61.28 seconds
Started	Oct 15 07:55:01 AM UTC 24
Finished	Oct 15 07:56:04 AM UTC 24
Peak memory	276616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579553180 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.2579553180
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3373997907
Short name	T81
Test name
Test status
Simulation time	842348900 ps
CPU time	103.26 seconds
Started	Oct 15 08:32:46 AM UTC 24
Finished	Oct 15 08:34:32 AM UTC 24
Peak memory	270704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373997907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3373997907
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1221017022
Short name	T27
Test name
Test status
Simulation time	14227875800 ps
CPU time	249.99 seconds
Started	Oct 15 08:17:07 AM UTC 24
Finished	Oct 15 08:21:21 AM UTC 24
Peak memory	274856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221017022 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.1221017022
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1295567389
Short name	T97
Test name
Test status
Simulation time	37404600 ps
CPU time	132.62 seconds
Started	Oct 15 08:31:52 AM UTC 24
Finished	Oct 15 08:34:07 AM UTC 24
Peak memory	270984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295567389 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.1295567389
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.258970022
Short name	T135
Test name
Test status
Simulation time	340574452200 ps
CPU time	1967.46 seconds
Started	Oct 15 08:22:52 AM UTC 24
Finished	Oct 15 08:55:59 AM UTC 24
Peak memory	273560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258970022 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.258970022
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1720338520
Short name	T3
Test name
Test status
Simulation time	1376998600 ps
CPU time	44.35 seconds
Started	Oct 15 08:17:33 AM UTC 24
Finished	Oct 15 08:18:19 AM UTC 24
Peak memory	272976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 20338520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc h_code.1720338520
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3268672156
Short name	T6
Test name
Test status
Simulation time	148898100 ps
CPU time	24.18 seconds
Started	Oct 15 08:21:54 AM UTC 24
Finished	Oct 15 08:22:20 AM UTC 24
Peak memory	275028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268672156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_wr_intg.3268672156
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.3018832662
Short name	T331
Test name
Test status
Simulation time	25303000 ps
CPU time	24.8 seconds
Started	Oct 15 07:57:00 AM UTC 24
Finished	Oct 15 07:57:26 AM UTC 24
Peak memory	274172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018832662 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3018832662
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.628954197
Short name	T89
Test name
Test status
Simulation time	3485881300 ps
CPU time	228.71 seconds
Started	Oct 15 08:24:51 AM UTC 24
Finished	Oct 15 08:28:43 AM UTC 24
Peak memory	291520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=628954197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_derr_detect.628954197
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1311946527
Short name	T279
Test name
Test status
Simulation time	677669800 ps
CPU time	1217.16 seconds
Started	Oct 15 07:56:37 AM UTC 24
Finished	Oct 15 08:17:08 AM UTC 24
Peak memory	276688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311946527 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.1311946527
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1181566246
Short name	T185
Test name
Test status
Simulation time	44209900 ps
CPU time	161.2 seconds
Started	Oct 15 09:23:35 AM UTC 24
Finished	Oct 15 09:26:19 AM UTC 24
Peak memory	275020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181566246 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.1181566246
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4052659267
Short name	T47
Test name
Test status
Simulation time	4359471800 ps
CPU time	78.53 seconds
Started	Oct 15 08:21:37 AM UTC 24
Finished	Oct 15 08:22:57 AM UTC 24
Peak memory	275052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052659267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.4052659267
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2367854691
Short name	T233
Test name
Test status
Simulation time	114267600 ps
CPU time	22.42 seconds
Started	Oct 15 07:58:14 AM UTC 24
Finished	Oct 15 07:58:37 AM UTC 24
Peak memory	276372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367854691 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2367854691
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.3672204562
Short name	T53
Test name
Test status
Simulation time	675084500 ps
CPU time	157.52 seconds
Started	Oct 15 08:25:05 AM UTC 24
Finished	Oct 15 08:27:46 AM UTC 24
Peak memory	305984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672204562 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.3672204562
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.963000254
Short name	T120
Test name
Test status
Simulation time	138686700 ps
CPU time	24.52 seconds
Started	Oct 15 08:22:36 AM UTC 24
Finished	Oct 15 08:23:02 AM UTC 24
Peak memory	268928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963000254 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.963000254
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.883505569
Short name	T352
Test name
Test status
Simulation time	15502500 ps
CPU time	22.65 seconds
Started	Oct 15 08:48:40 AM UTC 24
Finished	Oct 15 08:49:04 AM UTC 24
Peak memory	274944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=883505569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6 .flash_ctrl_hw_read_seed_err.883505569
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.3215065249
Short name	T192
Test name
Test status
Simulation time	246187200 ps
CPU time	173.19 seconds
Started	Oct 15 09:11:37 AM UTC 24
Finished	Oct 15 09:14:33 AM UTC 24
Peak memory	273016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215065249 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.3215065249
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.718399558
Short name	T328
Test name
Test status
Simulation time	159427500 ps
CPU time	154.64 seconds
Started	Oct 15 09:33:30 AM UTC 24
Finished	Oct 15 09:36:07 AM UTC 24
Peak memory	275272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718399558 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.718399558
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2664014542
Short name	T195
Test name
Test status
Simulation time	264659551300 ps
CPU time	3363.5 seconds
Started	Oct 15 08:23:02 AM UTC 24
Finished	Oct 15 09:19:40 AM UTC 24
Peak memory	277752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664014542 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.2664014542
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3462121055
Short name	T157
Test name
Test status
Simulation time	1780608100 ps
CPU time	276.6 seconds
Started	Oct 15 08:20:10 AM UTC 24
Finished	Oct 15 08:24:50 AM UTC 24
Peak memory	301784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3462121055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_rw_derr.3462121055
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.232664969
Short name	T42
Test name
Test status
Simulation time	274153000 ps
CPU time	46.65 seconds
Started	Oct 15 08:21:20 AM UTC 24
Finished	Oct 15 08:22:08 AM UTC 24
Peak memory	287424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232664969 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.232664969
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.1643878432
Short name	T205
Test name
Test status
Simulation time	1987915500 ps
CPU time	174.23 seconds
Started	Oct 15 08:24:54 AM UTC 24
Finished	Oct 15 08:27:51 AM UTC 24
Peak memory	291516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1643878432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1643878432
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.3356011405
Short name	T141
Test name
Test status
Simulation time	14352280100 ps
CPU time	447.74 seconds
Started	Oct 15 09:01:39 AM UTC 24
Finished	Oct 15 09:09:13 AM UTC 24
Peak memory	283144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3356011405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.3356011405
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1736421188
Short name	T31
Test name
Test status
Simulation time	10031486300 ps
CPU time	68.77 seconds
Started	Oct 15 08:22:27 AM UTC 24
Finished	Oct 15 08:23:37 AM UTC 24
Peak memory	287248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1736421188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1736421188
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1467189275
Short name	T244
Test name
Test status
Simulation time	16225300 ps
CPU time	25.33 seconds
Started	Oct 15 07:54:45 AM UTC 24
Finished	Oct 15 07:55:12 AM UTC 24
Peak memory	276364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467189275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.1467189275
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3730474686
Short name	T291
Test name
Test status
Simulation time	15660400 ps
CPU time	22.58 seconds
Started	Oct 15 08:45:01 AM UTC 24
Finished	Oct 15 08:45:25 AM UTC 24
Peak memory	271000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3730474686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_lcmgr_intg.3730474686
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3327584124
Short name	T264
Test name
Test status
Simulation time	6350098800 ps
CPU time	70.25 seconds
Started	Oct 15 07:56:19 AM UTC 24
Finished	Oct 15 07:57:31 AM UTC 24
Peak memory	276408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327584124 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.3327584124
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.894806430
Short name	T55
Test name
Test status
Simulation time	737846200 ps
CPU time	161.84 seconds
Started	Oct 15 08:19:21 AM UTC 24
Finished	Oct 15 08:22:06 AM UTC 24
Peak memory	305868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=894806430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ ctrl_ro_serr.894806430
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1423962442
Short name	T360
Test name
Test status
Simulation time	660832900 ps
CPU time	50.22 seconds
Started	Oct 15 08:41:11 AM UTC 24
Finished	Oct 15 08:42:02 AM UTC 24
Peak memory	275088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423962 442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f s_sup.1423962442
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2963432804
Short name	T337
Test name
Test status
Simulation time	15729300 ps
CPU time	15.63 seconds
Started	Oct 15 08:01:05 AM UTC 24
Finished	Oct 15 08:01:22 AM UTC 24
Peak memory	274452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963432804 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2963432804
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.4202594417
Short name	T129
Test name
Test status
Simulation time	22016800 ps
CPU time	25.73 seconds
Started	Oct 15 09:05:48 AM UTC 24
Finished	Oct 15 09:06:15 AM UTC 24
Peak memory	285340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4202594417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ ctrl_disable.4202594417
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2699388948
Short name	T381
Test name
Test status
Simulation time	3953850200 ps
CPU time	1368.98 seconds
Started	Oct 15 08:03:01 AM UTC 24
Finished	Oct 15 08:26:06 AM UTC 24
Peak memory	276688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699388948 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2699388948
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3241475214
Short name	T35
Test name
Test status
Simulation time	2708274700 ps
CPU time	196.05 seconds
Started	Oct 15 08:22:47 AM UTC 24
Finished	Oct 15 08:26:06 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241475214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3241475214
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.410890900
Short name	T238
Test name
Test status
Simulation time	776567400 ps
CPU time	36.76 seconds
Started	Oct 15 08:36:07 AM UTC 24
Finished	Oct 15 08:36:46 AM UTC 24
Peak memory	275444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=410890900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.410890900
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3291422970
Short name	T358
Test name
Test status
Simulation time	76357000 ps
CPU time	54.02 seconds
Started	Oct 15 09:03:19 AM UTC 24
Finished	Oct 15 09:04:15 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291422970 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.3291422970
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2263356874
Short name	T77
Test name
Test status
Simulation time	51008100 ps
CPU time	31.24 seconds
Started	Oct 15 07:53:55 AM UTC 24
Finished	Oct 15 07:54:28 AM UTC 24
Peak memory	276412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263356874 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2263356874
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3328981706
Short name	T218
Test name
Test status
Simulation time	17141700 ps
CPU time	26.23 seconds
Started	Oct 15 08:36:07 AM UTC 24
Finished	Oct 15 08:36:35 AM UTC 24
Peak memory	275320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3328981706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3328981706
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2552151404
Short name	T75
Test name
Test status
Simulation time	16327700 ps
CPU time	19.45 seconds
Started	Oct 15 08:31:00 AM UTC 24
Finished	Oct 15 08:31:21 AM UTC 24
Peak memory	282856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552151404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2552151404
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.3732255124
Short name	T340
Test name
Test status
Simulation time	9591397600 ps
CPU time	187.86 seconds
Started	Oct 15 08:51:16 AM UTC 24
Finished	Oct 15 08:54:27 AM UTC 24
Peak memory	303836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732255124 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.3732255124
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.766850900
Short name	T286
Test name
Test status
Simulation time	15760200 ps
CPU time	26.49 seconds
Started	Oct 15 09:03:37 AM UTC 24
Finished	Oct 15 09:04:05 AM UTC 24
Peak memory	270976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=766850900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.flash_ctrl_hw_read_seed_err.766850900
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.3823663193
Short name	T7
Test name
Test status
Simulation time	12059500 ps
CPU time	23.51 seconds
Started	Oct 15 08:21:56 AM UTC 24
Finished	Oct 15 08:22:21 AM UTC 24
Peak memory	273036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3823663193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3823663193
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.999305101
Short name	T41
Test name
Test status
Simulation time	28001200 ps
CPU time	53.64 seconds
Started	Oct 15 08:21:00 AM UTC 24
Finished	Oct 15 08:21:56 AM UTC 24
Peak memory	287424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999305101 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.999305101
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4286018882
Short name	T197
Test name
Test status
Simulation time	10012033700 ps
CPU time	173.28 seconds
Started	Oct 15 08:45:02 AM UTC 24
Finished	Oct 15 08:47:58 AM UTC 24
Peak memory	322464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4286018882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.4286018882
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3620240548
Short name	T362
Test name
Test status
Simulation time	184121100 ps
CPU time	52.9 seconds
Started	Oct 15 09:10:31 AM UTC 24
Finished	Oct 15 09:11:26 AM UTC 24
Peak memory	285412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3620240548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c trl_rw_evict_all_en.3620240548
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.303010459
Short name	T92
Test name
Test status
Simulation time	9941253300 ps
CPU time	743.03 seconds
Started	Oct 15 08:32:04 AM UTC 24
Finished	Oct 15 08:44:36 AM UTC 24
Peak memory	283148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=303010459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_mp_regions.303010459
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3536205564
Short name	T115
Test name
Test status
Simulation time	10031301200 ps
CPU time	100.82 seconds
Started	Oct 15 09:08:30 AM UTC 24
Finished	Oct 15 09:10:13 AM UTC 24
Peak memory	283184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3536205564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3536205564
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.3185718600
Short name	T139
Test name
Test status
Simulation time	6462979300 ps
CPU time	6832 seconds
Started	Oct 15 08:35:35 AM UTC 24
Finished	Oct 15 10:30:44 AM UTC 24
Peak memory	316052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185718600 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.3185718600
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3393040884
Short name	T275
Test name
Test status
Simulation time	930092300 ps
CPU time	921.17 seconds
Started	Oct 15 08:04:35 AM UTC 24
Finished	Oct 15 08:20:06 AM UTC 24
Peak memory	274640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393040884 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.3393040884
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.2482498951
Short name	T223
Test name
Test status
Simulation time	14314671800 ps
CPU time	512 seconds
Started	Oct 15 08:23:51 AM UTC 24
Finished	Oct 15 08:32:30 AM UTC 24
Peak memory	320192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482498951 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.2482498951
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.558313020
Short name	T266
Test name
Test status
Simulation time	2798249600 ps
CPU time	50.93 seconds
Started	Oct 15 07:56:12 AM UTC 24
Finished	Oct 15 07:57:04 AM UTC 24
Peak memory	276400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558313020 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.558313020
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.902709912
Short name	T261
Test name
Test status
Simulation time	1608462000 ps
CPU time	518.1 seconds
Started	Oct 15 07:59:42 AM UTC 24
Finished	Oct 15 08:08:26 AM UTC 24
Peak memory	276492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902709912 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.902709912
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2127034463
Short name	T427
Test name
Test status
Simulation time	8948831500 ps
CPU time	104.81 seconds
Started	Oct 15 09:03:28 AM UTC 24
Finished	Oct 15 09:05:15 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127034463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2127034463
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.4080624369
Short name	T173
Test name
Test status
Simulation time	45737000 ps
CPU time	23.3 seconds
Started	Oct 15 08:22:22 AM UTC 24
Finished	Oct 15 08:22:47 AM UTC 24
Peak memory	269016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4080624369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.4080624369
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.1584675317
Short name	T24
Test name
Test status
Simulation time	109468400 ps
CPU time	21.12 seconds
Started	Oct 15 08:26:09 AM UTC 24
Finished	Oct 15 08:26:31 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584675317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1584675317
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.2775261624
Short name	T619
Test name
Test status
Simulation time	1196275600 ps
CPU time	1038.14 seconds
Started	Oct 15 08:49:22 AM UTC 24
Finished	Oct 15 09:06:51 AM UTC 24
Peak memory	283112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775261624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2775261624
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3520816497
Short name	T186
Test name
Test status
Simulation time	40127428100 ps
CPU time	793.45 seconds
Started	Oct 15 08:49:05 AM UTC 24
Finished	Oct 15 09:02:28 AM UTC 24
Peak memory	274816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520816497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.3520816497
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.3560924890
Short name	T210
Test name
Test status
Simulation time	13641515500 ps
CPU time	527.85 seconds
Started	Oct 15 08:18:59 AM UTC 24
Finished	Oct 15 08:27:54 AM UTC 24
Peak memory	324292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560924890 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.3560924890
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2566674135
Short name	T113
Test name
Test status
Simulation time	1929817100 ps
CPU time	2134.41 seconds
Started	Oct 15 08:23:27 AM UTC 24
Finished	Oct 15 08:59:24 AM UTC 24
Peak memory	277748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 66674135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _error_prog_type.2566674135
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.3714969454
Short name	T103
Test name
Test status
Simulation time	879828600 ps
CPU time	21.68 seconds
Started	Oct 15 08:41:11 AM UTC 24
Finished	Oct 15 08:41:33 AM UTC 24
Peak memory	273228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3714969454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3714969454
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2352452391
Short name	T51
Test name
Test status
Simulation time	2807714700 ps
CPU time	128.94 seconds
Started	Oct 15 09:02:29 AM UTC 24
Finished	Oct 15 09:04:40 AM UTC 24
Peak memory	303808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352452391 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.2352452391
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3413299109
Short name	T359
Test name
Test status
Simulation time	236237000 ps
CPU time	55.38 seconds
Started	Oct 15 09:12:30 AM UTC 24
Finished	Oct 15 09:13:27 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413299109 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.3413299109
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3169262402
Short name	T271
Test name
Test status
Simulation time	62709700 ps
CPU time	34.76 seconds
Started	Oct 15 08:00:48 AM UTC 24
Finished	Oct 15 08:01:24 AM UTC 24
Peak memory	276364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169262402 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3169262402
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1549952023
Short name	T677
Test name
Test status
Simulation time	15294700 ps
CPU time	15.16 seconds
Started	Oct 15 09:14:52 AM UTC 24
Finished	Oct 15 09:15:08 AM UTC 24
Peak memory	273044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1549952023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_lcmgr_intg.1549952023
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2594143881
Short name	T420
Test name
Test status
Simulation time	31914980000 ps
CPU time	87.22 seconds
Started	Oct 15 09:10:58 AM UTC 24
Finished	Oct 15 09:12:27 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594143881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2594143881
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2244946393
Short name	T422
Test name
Test status
Simulation time	3564084700 ps
CPU time	92.02 seconds
Started	Oct 15 09:31:50 AM UTC 24
Finished	Oct 15 09:33:24 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244946393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2244946393
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.574636835
Short name	T68
Test name
Test status
Simulation time	327538900 ps
CPU time	35.34 seconds
Started	Oct 15 08:32:08 AM UTC 24
Finished	Oct 15 08:32:45 AM UTC 24
Peak memory	272856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57 4636835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch _code.574636835
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.861381239
Short name	T15
Test name
Test status
Simulation time	121498100 ps
CPU time	85.31 seconds
Started	Oct 15 08:16:59 AM UTC 24
Finished	Oct 15 08:18:27 AM UTC 24
Peak memory	285132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861381239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.861381239
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2808212312
Short name	T323
Test name
Test status
Simulation time	203317800 ps
CPU time	1237.11 seconds
Started	Oct 15 08:21:51 AM UTC 24
Finished	Oct 15 08:42:41 AM UTC 24
Peak memory	304260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808212312 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.2808212312
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2194359236
Short name	T277
Test name
Test status
Simulation time	491143300 ps
CPU time	558.04 seconds
Started	Oct 15 08:05:18 AM UTC 24
Finished	Oct 15 08:14:43 AM UTC 24
Peak memory	276488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194359236 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.2194359236
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.2923429864
Short name	T214
Test name
Test status
Simulation time	36072400 ps
CPU time	25.52 seconds
Started	Oct 15 08:26:42 AM UTC 24
Finished	Oct 15 08:27:09 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923429864 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.2923429864
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1295177760
Short name	T625
Test name
Test status
Simulation time	68715700 ps
CPU time	35.9 seconds
Started	Oct 15 09:07:52 AM UTC 24
Finished	Oct 15 09:08:30 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295177760 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.1295177760
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.2064668589
Short name	T62
Test name
Test status
Simulation time	844067200 ps
CPU time	21.46 seconds
Started	Oct 15 08:22:03 AM UTC 24
Finished	Oct 15 08:22:25 AM UTC 24
Peak memory	273260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2064668589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2064668589
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2845828481
Short name	T56
Test name
Test status
Simulation time	154363100 ps
CPU time	49.97 seconds
Started	Oct 15 08:21:53 AM UTC 24
Finished	Oct 15 08:22:45 AM UTC 24
Peak memory	285480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284582848 1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.2845828481
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.657150528
Short name	T109
Test name
Test status
Simulation time	878870777500 ps
CPU time	2030.88 seconds
Started	Oct 15 08:17:09 AM UTC 24
Finished	Oct 15 08:51:22 AM UTC 24
Peak memory	277632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657150528 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.657150528
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1719218364
Short name	T232
Test name
Test status
Simulation time	670448500 ps
CPU time	59.57 seconds
Started	Oct 15 07:55:06 AM UTC 24
Finished	Oct 15 07:56:07 AM UTC 24
Peak memory	274360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719218364 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.1719218364
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2166981893
Short name	T105
Test name
Test status
Simulation time	10819400 ps
CPU time	37.26 seconds
Started	Oct 15 08:26:07 AM UTC 24
Finished	Oct 15 08:26:46 AM UTC 24
Peak memory	285328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2166981893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_disable.2166981893
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1020271763
Short name	T123
Test name
Test status
Simulation time	55975300 ps
CPU time	49.61 seconds
Started	Oct 15 08:26:02 AM UTC 24
Finished	Oct 15 08:26:53 AM UTC 24
Peak memory	287464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1020271763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_rw_evict_all_en.1020271763
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.249086952
Short name	T350
Test name
Test status
Simulation time	47597394000 ps
CPU time	310.68 seconds
Started	Oct 15 09:07:44 AM UTC 24
Finished	Oct 15 09:12:59 AM UTC 24
Peak memory	301644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=249086952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 12.flash_ctrl_intr_rd_slow_flash.249086952
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.3936698551
Short name	T412
Test name
Test status
Simulation time	39744700 ps
CPU time	33.25 seconds
Started	Oct 15 09:12:43 AM UTC 24
Finished	Oct 15 09:13:18 AM UTC 24
Peak memory	285336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3936698551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ ctrl_disable.3936698551
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1098537975
Short name	T364
Test name
Test status
Simulation time	46001500 ps
CPU time	37.62 seconds
Started	Oct 15 09:17:41 AM UTC 24
Finished	Oct 15 09:18:20 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1098537975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c trl_rw_evict_all_en.1098537975
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.821773066
Short name	T392
Test name
Test status
Simulation time	35730600 ps
CPU time	37.74 seconds
Started	Oct 15 09:25:15 AM UTC 24
Finished	Oct 15 09:25:54 AM UTC 24
Peak memory	285256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=821773066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_disable.821773066
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.2070913804
Short name	T421
Test name
Test status
Simulation time	9639696100 ps
CPU time	79.96 seconds
Started	Oct 15 09:25:44 AM UTC 24
Finished	Oct 15 09:27:06 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070913804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2070913804
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2835011070
Short name	T416
Test name
Test status
Simulation time	18176300 ps
CPU time	40.51 seconds
Started	Oct 15 09:26:48 AM UTC 24
Finished	Oct 15 09:27:30 AM UTC 24
Peak memory	285308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2835011070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ ctrl_disable.2835011070
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2588597238
Short name	T426
Test name
Test status
Simulation time	8546995300 ps
CPU time	105.69 seconds
Started	Oct 15 09:26:50 AM UTC 24
Finished	Oct 15 09:28:38 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588597238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2588597238
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.2697941267
Short name	T430
Test name
Test status
Simulation time	400311300 ps
CPU time	62.3 seconds
Started	Oct 15 09:27:18 AM UTC 24
Finished	Oct 15 09:28:22 AM UTC 24
Peak memory	275112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697941267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2697941267
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.1740651280
Short name	T131
Test name
Test status
Simulation time	21425500 ps
CPU time	26.37 seconds
Started	Oct 15 09:28:15 AM UTC 24
Finished	Oct 15 09:28:43 AM UTC 24
Peak memory	285316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1740651280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ ctrl_disable.1740651280
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.1328221717
Short name	T389
Test name
Test status
Simulation time	10753600 ps
CPU time	34.62 seconds
Started	Oct 15 09:29:09 AM UTC 24
Finished	Oct 15 09:29:45 AM UTC 24
Peak memory	285316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1328221717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ ctrl_disable.1328221717
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.174237086
Short name	T423
Test name
Test status
Simulation time	2619107200 ps
CPU time	62.6 seconds
Started	Oct 15 08:57:16 AM UTC 24
Finished	Oct 15 08:58:20 AM UTC 24
Peak memory	274988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174237086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.174237086
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3425043236
Short name	T44
Test name
Test status
Simulation time	9945345400 ps
CPU time	102.92 seconds
Started	Oct 15 08:20:48 AM UTC 24
Finished	Oct 15 08:22:33 AM UTC 24
Peak memory	270924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425043236 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.3425043236
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2403068376
Short name	T176
Test name
Test status
Simulation time	575265900 ps
CPU time	131.11 seconds
Started	Oct 15 08:28:43 AM UTC 24
Finished	Oct 15 08:30:57 AM UTC 24
Peak memory	291520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403068376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2403068376
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.3283644441
Short name	T118
Test name
Test status
Simulation time	45044796900 ps
CPU time	394.29 seconds
Started	Oct 15 09:11:42 AM UTC 24
Finished	Oct 15 09:18:21 AM UTC 24
Peak memory	322204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283644441 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.3283644441
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1900809362
Short name	T239
Test name
Test status
Simulation time	17692700 ps
CPU time	28.44 seconds
Started	Oct 15 08:36:08 AM UTC 24
Finished	Oct 15 08:36:38 AM UTC 24
Peak memory	273264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900809362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1900809362
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1150565596
Short name	T134
Test name
Test status
Simulation time	73175300 ps
CPU time	28.95 seconds
Started	Oct 15 07:55:19 AM UTC 24
Finished	Oct 15 07:55:50 AM UTC 24
Peak memory	276372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150565596 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1150565596
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3570350211
Short name	T293
Test name
Test status
Simulation time	11268962300 ps
CPU time	2967.72 seconds
Started	Oct 15 08:18:03 AM UTC 24
Finished	Oct 15 09:08:03 AM UTC 24
Peak memory	275640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570350211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.3570350211
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1690049227
Short name	T63
Test name
Test status
Simulation time	2907805100 ps
CPU time	152.11 seconds
Started	Oct 15 08:20:07 AM UTC 24
Finished	Oct 15 08:22:42 AM UTC 24
Peak memory	291712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690049227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1690049227
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2165207476
Short name	T8
Test name
Test status
Simulation time	355677400 ps
CPU time	26.93 seconds
Started	Oct 15 08:26:26 AM UTC 24
Finished	Oct 15 08:26:54 AM UTC 24
Peak memory	272988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165207476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_wr_intg.2165207476
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.797470133
Short name	T102
Test name
Test status
Simulation time	710385800 ps
CPU time	27.8 seconds
Started	Oct 15 08:30:58 AM UTC 24
Finished	Oct 15 08:31:27 AM UTC 24
Peak memory	275280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=797470133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.797470133
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.497752751
Short name	T82
Test name
Test status
Simulation time	1656836200 ps
CPU time	127.75 seconds
Started	Oct 15 08:37:36 AM UTC 24
Finished	Oct 15 08:39:46 AM UTC 24
Peak memory	270708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497752751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.497752751
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3457586235
Short name	T263
Test name
Test status
Simulation time	48729800 ps
CPU time	69.23 seconds
Started	Oct 15 07:54:55 AM UTC 24
Finished	Oct 15 07:56:06 AM UTC 24
Peak memory	276416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457586235 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.3457586235
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3538866094
Short name	T79
Test name
Test status
Simulation time	51711200 ps
CPU time	19.32 seconds
Started	Oct 15 07:55:13 AM UTC 24
Finished	Oct 15 07:55:34 AM UTC 24
Peak memory	290816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3538866094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3538866094
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.994787013
Short name	T78
Test name
Test status
Simulation time	61374200 ps
CPU time	20.62 seconds
Started	Oct 15 07:54:56 AM UTC 24
Finished	Oct 15 07:55:18 AM UTC 24
Peak memory	274368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994787013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.994787013
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.231659504
Short name	T262
Test name
Test status
Simulation time	15987700 ps
CPU time	24.99 seconds
Started	Oct 15 07:54:29 AM UTC 24
Finished	Oct 15 07:54:56 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231659504 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.231659504
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.170986980
Short name	T1128
Test name
Test status
Simulation time	16084000 ps
CPU time	24.62 seconds
Started	Oct 15 07:54:33 AM UTC 24
Finished	Oct 15 07:54:59 AM UTC 24
Peak memory	274372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170986980 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.170986980
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1289571700
Short name	T249
Test name
Test status
Simulation time	337852800 ps
CPU time	57.3 seconds
Started	Oct 15 07:55:12 AM UTC 24
Finished	Oct 15 07:56:11 AM UTC 24
Peak memory	276592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1289571700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ same_csr_outstanding.1289571700
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3357406911
Short name	T1126
Test name
Test status
Simulation time	13921300 ps
CPU time	28.35 seconds
Started	Oct 15 07:54:14 AM UTC 24
Finished	Oct 15 07:54:44 AM UTC 24
Peak memory	274420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335 7406911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha dow_reg_errors.3357406911
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.255040886
Short name	T1127
Test name
Test status
Simulation time	76013000 ps
CPU time	25.04 seconds
Started	Oct 15 07:54:28 AM UTC 24
Finished	Oct 15 07:54:54 AM UTC 24
Peak memory	274304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=255040886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_shadow_reg_errors_with_csr_rw.255040886
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.220750983
Short name	T382
Test name
Test status
Simulation time	1680505300 ps
CPU time	1132.29 seconds
Started	Oct 15 07:54:02 AM UTC 24
Finished	Oct 15 08:13:07 AM UTC 24
Peak memory	276488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220750983 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.220750983
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3278613681
Short name	T315
Test name
Test status
Simulation time	45417500 ps
CPU time	70.67 seconds
Started	Oct 15 07:56:08 AM UTC 24
Finished	Oct 15 07:57:20 AM UTC 24
Peak memory	276400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278613681 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.3278613681
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1881845561
Short name	T250
Test name
Test status
Simulation time	67580400 ps
CPU time	29.9 seconds
Started	Oct 15 07:56:08 AM UTC 24
Finished	Oct 15 07:56:39 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881845561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.1881845561
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2450280573
Short name	T269
Test name
Test status
Simulation time	15013500 ps
CPU time	24.64 seconds
Started	Oct 15 07:55:52 AM UTC 24
Finished	Oct 15 07:56:19 AM UTC 24
Peak memory	274188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450280573 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2450280573
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2774930147
Short name	T245
Test name
Test status
Simulation time	30219200 ps
CPU time	24.52 seconds
Started	Oct 15 07:56:05 AM UTC 24
Finished	Oct 15 07:56:30 AM UTC 24
Peak memory	276360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774930147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.2774930147
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3720672122
Short name	T1131
Test name
Test status
Simulation time	21563000 ps
CPU time	24.7 seconds
Started	Oct 15 07:56:02 AM UTC 24
Finished	Oct 15 07:56:29 AM UTC 24
Peak memory	274372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720672122 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.3720672122
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3385367330
Short name	T251
Test name
Test status
Simulation time	440672700 ps
CPU time	25.34 seconds
Started	Oct 15 07:56:24 AM UTC 24
Finished	Oct 15 07:56:51 AM UTC 24
Peak memory	274364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3385367330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ same_csr_outstanding.3385367330
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2075630480
Short name	T1129
Test name
Test status
Simulation time	49858300 ps
CPU time	19.05 seconds
Started	Oct 15 07:55:42 AM UTC 24
Finished	Oct 15 07:56:02 AM UTC 24
Peak memory	274228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207 5630480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha dow_reg_errors.2075630480
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1498695495
Short name	T1130
Test name
Test status
Simulation time	43386500 ps
CPU time	29.12 seconds
Started	Oct 15 07:55:52 AM UTC 24
Finished	Oct 15 07:56:23 AM UTC 24
Peak memory	274432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1498695495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1498695495
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1040635435
Short name	T278
Test name
Test status
Simulation time	1089300200 ps
CPU time	1279.44 seconds
Started	Oct 15 07:55:34 AM UTC 24
Finished	Oct 15 08:17:09 AM UTC 24
Peak memory	276688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040635435 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.1040635435
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3279989923
Short name	T1168
Test name
Test status
Simulation time	352310700 ps
CPU time	31.66 seconds
Started	Oct 15 08:01:35 AM UTC 24
Finished	Oct 15 08:02:08 AM UTC 24
Peak memory	286716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3279989923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3279989923
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.643819681
Short name	T1163
Test name
Test status
Simulation time	21426200 ps
CPU time	18.75 seconds
Started	Oct 15 08:01:25 AM UTC 24
Finished	Oct 15 08:01:45 AM UTC 24
Peak memory	274548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643819681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.643819681
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.622192047
Short name	T338
Test name
Test status
Simulation time	47868800 ps
CPU time	24.03 seconds
Started	Oct 15 08:01:23 AM UTC 24
Finished	Oct 15 08:01:48 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622192047 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.622192047
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1526635713
Short name	T1167
Test name
Test status
Simulation time	351006900 ps
CPU time	27.91 seconds
Started	Oct 15 08:01:33 AM UTC 24
Finished	Oct 15 08:02:02 AM UTC 24
Peak memory	274560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1526635713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl _same_csr_outstanding.1526635713
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1231200367
Short name	T1164
Test name
Test status
Simulation time	82800500 ps
CPU time	27.13 seconds
Started	Oct 15 08:01:21 AM UTC 24
Finished	Oct 15 08:01:49 AM UTC 24
Peak memory	274224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123 1200367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh adow_reg_errors.1231200367
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.191114619
Short name	T1165
Test name
Test status
Simulation time	76007700 ps
CPU time	27.07 seconds
Started	Oct 15 08:01:23 AM UTC 24
Finished	Oct 15 08:01:51 AM UTC 24
Peak memory	274236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=191114619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_shadow_reg_errors_with_csr_rw.191114619
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3096683838
Short name	T274
Test name
Test status
Simulation time	35054500 ps
CPU time	24.61 seconds
Started	Oct 15 08:01:08 AM UTC 24
Finished	Oct 15 08:01:34 AM UTC 24
Peak memory	276484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096683838 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.3096683838
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.842554659
Short name	T1262
Test name
Test status
Simulation time	4321141900 ps
CPU time	1284.8 seconds
Started	Oct 15 08:01:10 AM UTC 24
Finished	Oct 15 08:22:51 AM UTC 24
Peak memory	276480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842554659 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.842554659
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2879464944
Short name	T1173
Test name
Test status
Simulation time	53632300 ps
CPU time	21.19 seconds
Started	Oct 15 08:02:02 AM UTC 24
Finished	Oct 15 08:02:25 AM UTC 24
Peak memory	286784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2879464944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2879464944
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.216928041
Short name	T1170
Test name
Test status
Simulation time	200391800 ps
CPU time	22.91 seconds
Started	Oct 15 08:01:51 AM UTC 24
Finished	Oct 15 08:02:16 AM UTC 24
Peak memory	276612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216928041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.216928041
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.607351294
Short name	T1172
Test name
Test status
Simulation time	47669100 ps
CPU time	25.78 seconds
Started	Oct 15 08:01:50 AM UTC 24
Finished	Oct 15 08:02:17 AM UTC 24
Peak memory	274176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607351294 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.607351294
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2003569296
Short name	T1174
Test name
Test status
Simulation time	354616500 ps
CPU time	34.35 seconds
Started	Oct 15 08:01:53 AM UTC 24
Finished	Oct 15 08:02:28 AM UTC 24
Peak memory	276412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2003569296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _same_csr_outstanding.2003569296
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.390095843
Short name	T1169
Test name
Test status
Simulation time	37477700 ps
CPU time	23.79 seconds
Started	Oct 15 08:01:45 AM UTC 24
Finished	Oct 15 08:02:10 AM UTC 24
Peak memory	274484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390 095843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sha dow_reg_errors.390095843
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4228520673
Short name	T1171
Test name
Test status
Simulation time	24656300 ps
CPU time	25.52 seconds
Started	Oct 15 08:01:49 AM UTC 24
Finished	Oct 15 08:02:16 AM UTC 24
Peak memory	274220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4228520673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f lash_ctrl_shadow_reg_errors_with_csr_rw.4228520673
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2598350794
Short name	T273
Test name
Test status
Simulation time	346393200 ps
CPU time	25.6 seconds
Started	Oct 15 08:01:36 AM UTC 24
Finished	Oct 15 08:02:03 AM UTC 24
Peak memory	276628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598350794 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.2598350794
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2350634317
Short name	T276
Test name
Test status
Simulation time	784974800 ps
CPU time	1148.69 seconds
Started	Oct 15 08:01:37 AM UTC 24
Finished	Oct 15 08:20:58 AM UTC 24
Peak memory	276496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350634317 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.2350634317
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4111988585
Short name	T1180
Test name
Test status
Simulation time	56684600 ps
CPU time	31.46 seconds
Started	Oct 15 08:02:18 AM UTC 24
Finished	Oct 15 08:02:51 AM UTC 24
Peak memory	286712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4111988585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.4111988585
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2092941346
Short name	T1179
Test name
Test status
Simulation time	710437100 ps
CPU time	31.98 seconds
Started	Oct 15 08:02:16 AM UTC 24
Finished	Oct 15 08:02:50 AM UTC 24
Peak memory	274368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092941346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.2092941346
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3725540512
Short name	T1178
Test name
Test status
Simulation time	260027000 ps
CPU time	24.56 seconds
Started	Oct 15 08:02:16 AM UTC 24
Finished	Oct 15 08:02:42 AM UTC 24
Peak memory	274180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725540512 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.3725540512
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.145615368
Short name	T1186
Test name
Test status
Simulation time	121444400 ps
CPU time	52.66 seconds
Started	Oct 15 08:02:17 AM UTC 24
Finished	Oct 15 08:03:12 AM UTC 24
Peak memory	274352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 145615368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ same_csr_outstanding.145615368
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2506942303
Short name	T1175
Test name
Test status
Simulation time	13916600 ps
CPU time	25.16 seconds
Started	Oct 15 08:02:09 AM UTC 24
Finished	Oct 15 08:02:36 AM UTC 24
Peak memory	274228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250 6942303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh adow_reg_errors.2506942303
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2971667415
Short name	T1177
Test name
Test status
Simulation time	40682600 ps
CPU time	28.36 seconds
Started	Oct 15 08:02:11 AM UTC 24
Finished	Oct 15 08:02:41 AM UTC 24
Peak memory	274240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2971667415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f lash_ctrl_shadow_reg_errors_with_csr_rw.2971667415
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2761639151
Short name	T1176
Test name
Test status
Simulation time	61775900 ps
CPU time	35.54 seconds
Started	Oct 15 08:02:03 AM UTC 24
Finished	Oct 15 08:02:40 AM UTC 24
Peak memory	276436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761639151 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.2761639151
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3787835457
Short name	T376
Test name
Test status
Simulation time	2759200900 ps
CPU time	1272.97 seconds
Started	Oct 15 08:02:04 AM UTC 24
Finished	Oct 15 08:23:32 AM UTC 24
Peak memory	286736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787835457 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.3787835457
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3730140269
Short name	T1187
Test name
Test status
Simulation time	81585300 ps
CPU time	25.83 seconds
Started	Oct 15 08:02:52 AM UTC 24
Finished	Oct 15 08:03:19 AM UTC 24
Peak memory	292856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3730140269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3730140269
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.155661186
Short name	T1183
Test name
Test status
Simulation time	37512600 ps
CPU time	20.95 seconds
Started	Oct 15 08:02:43 AM UTC 24
Finished	Oct 15 08:03:05 AM UTC 24
Peak memory	276420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155661186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.155661186
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1665012965
Short name	T1184
Test name
Test status
Simulation time	42826800 ps
CPU time	22.77 seconds
Started	Oct 15 08:02:42 AM UTC 24
Finished	Oct 15 08:03:06 AM UTC 24
Peak memory	274388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665012965 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1665012965
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2257222017
Short name	T1188
Test name
Test status
Simulation time	164660400 ps
CPU time	30.05 seconds
Started	Oct 15 08:02:51 AM UTC 24
Finished	Oct 15 08:03:22 AM UTC 24
Peak memory	276412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2257222017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl _same_csr_outstanding.2257222017
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.843573696
Short name	T1185
Test name
Test status
Simulation time	14385100 ps
CPU time	28.55 seconds
Started	Oct 15 08:02:36 AM UTC 24
Finished	Oct 15 08:03:06 AM UTC 24
Peak memory	274220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843 573696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sha dow_reg_errors.843573696
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1523931065
Short name	T1182
Test name
Test status
Simulation time	102825600 ps
CPU time	18.7 seconds
Started	Oct 15 08:02:41 AM UTC 24
Finished	Oct 15 08:03:00 AM UTC 24
Peak memory	274244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1523931065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f lash_ctrl_shadow_reg_errors_with_csr_rw.1523931065
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1569919296
Short name	T1181
Test name
Test status
Simulation time	314151900 ps
CPU time	31.88 seconds
Started	Oct 15 08:02:25 AM UTC 24
Finished	Oct 15 08:02:59 AM UTC 24
Peak memory	276376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569919296 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.1569919296
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1122087714
Short name	T1261
Test name
Test status
Simulation time	2673463500 ps
CPU time	1202.58 seconds
Started	Oct 15 08:02:29 AM UTC 24
Finished	Oct 15 08:22:46 AM UTC 24
Peak memory	276692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122087714 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.1122087714
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2438663761
Short name	T1194
Test name
Test status
Simulation time	492715100 ps
CPU time	29.38 seconds
Started	Oct 15 08:03:23 AM UTC 24
Finished	Oct 15 08:03:53 AM UTC 24
Peak memory	286912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2438663761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2438663761
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.791315455
Short name	T1193
Test name
Test status
Simulation time	61550700 ps
CPU time	26.85 seconds
Started	Oct 15 08:03:12 AM UTC 24
Finished	Oct 15 08:03:41 AM UTC 24
Peak memory	274352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791315455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.791315455
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.586021886
Short name	T1189
Test name
Test status
Simulation time	30771700 ps
CPU time	15.21 seconds
Started	Oct 15 08:03:07 AM UTC 24
Finished	Oct 15 08:03:24 AM UTC 24
Peak memory	274456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586021886 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.586021886
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.46537343
Short name	T1196
Test name
Test status
Simulation time	61724200 ps
CPU time	40.49 seconds
Started	Oct 15 08:03:19 AM UTC 24
Finished	Oct 15 08:04:01 AM UTC 24
Peak memory	276620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 46537343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_s ame_csr_outstanding.46537343
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1159586549
Short name	T1191
Test name
Test status
Simulation time	23351000 ps
CPU time	24.87 seconds
Started	Oct 15 08:03:06 AM UTC 24
Finished	Oct 15 08:03:32 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115 9586549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh adow_reg_errors.1159586549
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.770670329
Short name	T1192
Test name
Test status
Simulation time	14587700 ps
CPU time	28.85 seconds
Started	Oct 15 08:03:06 AM UTC 24
Finished	Oct 15 08:03:36 AM UTC 24
Peak memory	274220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=770670329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_shadow_reg_errors_with_csr_rw.770670329
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.288593872
Short name	T1190
Test name
Test status
Simulation time	76334400 ps
CPU time	24.64 seconds
Started	Oct 15 08:03:00 AM UTC 24
Finished	Oct 15 08:03:26 AM UTC 24
Peak memory	276360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288593872 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.288593872
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3722396888
Short name	T1201
Test name
Test status
Simulation time	24606100 ps
CPU time	23.02 seconds
Started	Oct 15 08:04:02 AM UTC 24
Finished	Oct 15 08:04:27 AM UTC 24
Peak memory	290812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3722396888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3722396888
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.440225730
Short name	T1200
Test name
Test status
Simulation time	20819400 ps
CPU time	24.95 seconds
Started	Oct 15 08:03:54 AM UTC 24
Finished	Oct 15 08:04:20 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440225730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.440225730
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3461890324
Short name	T1199
Test name
Test status
Simulation time	44516100 ps
CPU time	23.2 seconds
Started	Oct 15 08:03:41 AM UTC 24
Finished	Oct 15 08:04:05 AM UTC 24
Peak memory	274196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461890324 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.3461890324
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.54119600
Short name	T1202
Test name
Test status
Simulation time	184774900 ps
CPU time	27.98 seconds
Started	Oct 15 08:04:00 AM UTC 24
Finished	Oct 15 08:04:29 AM UTC 24
Peak memory	276476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 54119600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_s ame_csr_outstanding.54119600
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2788649973
Short name	T1197
Test name
Test status
Simulation time	18800100 ps
CPU time	28.62 seconds
Started	Oct 15 08:03:33 AM UTC 24
Finished	Oct 15 08:04:03 AM UTC 24
Peak memory	274228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278 8649973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh adow_reg_errors.2788649973
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.387763507
Short name	T1198
Test name
Test status
Simulation time	83586100 ps
CPU time	26.35 seconds
Started	Oct 15 08:03:37 AM UTC 24
Finished	Oct 15 08:04:05 AM UTC 24
Peak memory	274236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=387763507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_shadow_reg_errors_with_csr_rw.387763507
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1393238137
Short name	T1195
Test name
Test status
Simulation time	62104900 ps
CPU time	32.86 seconds
Started	Oct 15 08:03:25 AM UTC 24
Finished	Oct 15 08:03:59 AM UTC 24
Peak memory	276552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393238137 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.1393238137
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1920094987
Short name	T1263
Test name
Test status
Simulation time	3432642600 ps
CPU time	1425.18 seconds
Started	Oct 15 08:03:27 AM UTC 24
Finished	Oct 15 08:27:29 AM UTC 24
Peak memory	276580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920094987 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.1920094987
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.893436568
Short name	T1208
Test name
Test status
Simulation time	64357700 ps
CPU time	22.73 seconds
Started	Oct 15 08:04:27 AM UTC 24
Finished	Oct 15 08:04:51 AM UTC 24
Peak memory	290816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=893436568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.893436568
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3906060242
Short name	T1207
Test name
Test status
Simulation time	67722800 ps
CPU time	27.16 seconds
Started	Oct 15 08:04:22 AM UTC 24
Finished	Oct 15 08:04:50 AM UTC 24
Peak memory	274564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906060242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.3906060242
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2270779016
Short name	T1206
Test name
Test status
Simulation time	17324000 ps
CPU time	25.18 seconds
Started	Oct 15 08:04:13 AM UTC 24
Finished	Oct 15 08:04:40 AM UTC 24
Peak memory	274172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270779016 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.2270779016
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.230001932
Short name	T1210
Test name
Test status
Simulation time	37123200 ps
CPU time	27.07 seconds
Started	Oct 15 08:04:25 AM UTC 24
Finished	Oct 15 08:04:54 AM UTC 24
Peak memory	276420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 230001932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ same_csr_outstanding.230001932
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.170839675
Short name	T1205
Test name
Test status
Simulation time	94826800 ps
CPU time	27.98 seconds
Started	Oct 15 08:04:05 AM UTC 24
Finished	Oct 15 08:04:35 AM UTC 24
Peak memory	274236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170 839675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sha dow_reg_errors.170839675
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1088102686
Short name	T1204
Test name
Test status
Simulation time	13710400 ps
CPU time	26.68 seconds
Started	Oct 15 08:04:06 AM UTC 24
Finished	Oct 15 08:04:35 AM UTC 24
Peak memory	274244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1088102686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f lash_ctrl_shadow_reg_errors_with_csr_rw.1088102686
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2159832662
Short name	T1203
Test name
Test status
Simulation time	48828700 ps
CPU time	27.85 seconds
Started	Oct 15 08:04:04 AM UTC 24
Finished	Oct 15 08:04:33 AM UTC 24
Peak memory	276548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159832662 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.2159832662
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1984266487
Short name	T377
Test name
Test status
Simulation time	718630300 ps
CPU time	477.69 seconds
Started	Oct 15 08:04:04 AM UTC 24
Finished	Oct 15 08:12:08 AM UTC 24
Peak memory	276624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984266487 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.1984266487
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1885604557
Short name	T1220
Test name
Test status
Simulation time	45620300 ps
CPU time	35.28 seconds
Started	Oct 15 08:04:52 AM UTC 24
Finished	Oct 15 08:05:28 AM UTC 24
Peak memory	286720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1885604557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1885604557
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2185351053
Short name	T1214
Test name
Test status
Simulation time	137116000 ps
CPU time	25.79 seconds
Started	Oct 15 08:04:40 AM UTC 24
Finished	Oct 15 08:05:08 AM UTC 24
Peak memory	274628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185351053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.2185351053
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2399508678
Short name	T1213
Test name
Test status
Simulation time	17628700 ps
CPU time	24.9 seconds
Started	Oct 15 08:04:36 AM UTC 24
Finished	Oct 15 08:05:03 AM UTC 24
Peak memory	274180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399508678 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.2399508678
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.773003334
Short name	T1217
Test name
Test status
Simulation time	42326600 ps
CPU time	25.9 seconds
Started	Oct 15 08:04:51 AM UTC 24
Finished	Oct 15 08:05:18 AM UTC 24
Peak memory	276416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 773003334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ same_csr_outstanding.773003334
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2519290805
Short name	T1212
Test name
Test status
Simulation time	31232600 ps
CPU time	24.67 seconds
Started	Oct 15 08:04:35 AM UTC 24
Finished	Oct 15 08:05:01 AM UTC 24
Peak memory	274244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251 9290805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh adow_reg_errors.2519290805
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.8286275
Short name	T1209
Test name
Test status
Simulation time	91852100 ps
CPU time	15.37 seconds
Started	Oct 15 08:04:35 AM UTC 24
Finished	Oct 15 08:04:52 AM UTC 24
Peak memory	274216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=8286275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_shadow_reg_errors_with_csr_rw.8286275
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1757989556
Short name	T1211
Test name
Test status
Simulation time	42829100 ps
CPU time	29.39 seconds
Started	Oct 15 08:04:30 AM UTC 24
Finished	Oct 15 08:05:01 AM UTC 24
Peak memory	276564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757989556 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.1757989556
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3359988864
Short name	T1222
Test name
Test status
Simulation time	151686700 ps
CPU time	20.69 seconds
Started	Oct 15 08:05:14 AM UTC 24
Finished	Oct 15 08:05:36 AM UTC 24
Peak memory	286720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3359988864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3359988864
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2673826311
Short name	T1219
Test name
Test status
Simulation time	120749100 ps
CPU time	20.52 seconds
Started	Oct 15 08:05:03 AM UTC 24
Finished	Oct 15 08:05:25 AM UTC 24
Peak memory	274548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673826311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.2673826311
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2220276555
Short name	T1218
Test name
Test status
Simulation time	33638400 ps
CPU time	17.17 seconds
Started	Oct 15 08:05:02 AM UTC 24
Finished	Oct 15 08:05:20 AM UTC 24
Peak memory	274180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220276555 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.2220276555
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3539822673
Short name	T1224
Test name
Test status
Simulation time	739763400 ps
CPU time	36.19 seconds
Started	Oct 15 08:05:08 AM UTC 24
Finished	Oct 15 08:05:46 AM UTC 24
Peak memory	274352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3539822673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl _same_csr_outstanding.3539822673
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3508449545
Short name	T1216
Test name
Test status
Simulation time	22818600 ps
CPU time	17.13 seconds
Started	Oct 15 08:04:57 AM UTC 24
Finished	Oct 15 08:05:15 AM UTC 24
Peak memory	274436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350 8449545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sh adow_reg_errors.3508449545
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.23968450
Short name	T1221
Test name
Test status
Simulation time	11592500 ps
CPU time	28.5 seconds
Started	Oct 15 08:05:02 AM UTC 24
Finished	Oct 15 08:05:32 AM UTC 24
Peak memory	274240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=23968450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_shadow_reg_errors_with_csr_rw.23968450
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2881802349
Short name	T1215
Test name
Test status
Simulation time	45960100 ps
CPU time	19.37 seconds
Started	Oct 15 08:04:53 AM UTC 24
Finished	Oct 15 08:05:13 AM UTC 24
Peak memory	276364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881802349 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.2881802349
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1461097402
Short name	T380
Test name
Test status
Simulation time	7303226900 ps
CPU time	1272.92 seconds
Started	Oct 15 08:04:57 AM UTC 24
Finished	Oct 15 08:26:25 AM UTC 24
Peak memory	276496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461097402 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.1461097402
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1973770684
Short name	T1231
Test name
Test status
Simulation time	37331200 ps
CPU time	24.86 seconds
Started	Oct 15 08:05:36 AM UTC 24
Finished	Oct 15 08:06:02 AM UTC 24
Peak memory	293056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1973770684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1973770684
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3335965518
Short name	T1229
Test name
Test status
Simulation time	98214300 ps
CPU time	25.72 seconds
Started	Oct 15 08:05:33 AM UTC 24
Finished	Oct 15 08:06:00 AM UTC 24
Peak memory	274368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335965518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.3335965518
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.449049015
Short name	T1227
Test name
Test status
Simulation time	32507200 ps
CPU time	22.06 seconds
Started	Oct 15 08:05:30 AM UTC 24
Finished	Oct 15 08:05:53 AM UTC 24
Peak memory	274376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449049015 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.449049015
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3953689681
Short name	T1228
Test name
Test status
Simulation time	237621700 ps
CPU time	21.01 seconds
Started	Oct 15 08:05:36 AM UTC 24
Finished	Oct 15 08:05:59 AM UTC 24
Peak memory	274480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3953689681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl _same_csr_outstanding.3953689681
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2451995335
Short name	T1225
Test name
Test status
Simulation time	26761400 ps
CPU time	24.32 seconds
Started	Oct 15 08:05:21 AM UTC 24
Finished	Oct 15 08:05:47 AM UTC 24
Peak memory	274244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245 1995335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh adow_reg_errors.2451995335
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4052207120
Short name	T1226
Test name
Test status
Simulation time	40801000 ps
CPU time	21.11 seconds
Started	Oct 15 08:05:25 AM UTC 24
Finished	Oct 15 08:05:48 AM UTC 24
Peak memory	274244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4052207120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f lash_ctrl_shadow_reg_errors_with_csr_rw.4052207120
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.929159876
Short name	T1223
Test name
Test status
Simulation time	67829400 ps
CPU time	22.06 seconds
Started	Oct 15 08:05:16 AM UTC 24
Finished	Oct 15 08:05:39 AM UTC 24
Peak memory	276360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929159876 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.929159876
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1390457973
Short name	T383
Test name
Test status
Simulation time	1992537700 ps
CPU time	76.76 seconds
Started	Oct 15 07:57:21 AM UTC 24
Finished	Oct 15 07:58:41 AM UTC 24
Peak memory	276404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390457973 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.1390457973
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1922151960
Short name	T265
Test name
Test status
Simulation time	2259696700 ps
CPU time	49.64 seconds
Started	Oct 15 07:57:18 AM UTC 24
Finished	Oct 15 07:58:09 AM UTC 24
Peak memory	276424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922151960 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.1922151960
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3253964456
Short name	T1135
Test name
Test status
Simulation time	34929900 ps
CPU time	43.89 seconds
Started	Oct 15 07:57:07 AM UTC 24
Finished	Oct 15 07:57:52 AM UTC 24
Peak memory	276400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253964456 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.3253964456
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1026390200
Short name	T133
Test name
Test status
Simulation time	169216900 ps
CPU time	32.9 seconds
Started	Oct 15 07:57:27 AM UTC 24
Finished	Oct 15 07:58:01 AM UTC 24
Peak memory	286720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1026390200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1026390200
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2752802140
Short name	T252
Test name
Test status
Simulation time	43801900 ps
CPU time	26.9 seconds
Started	Oct 15 07:57:10 AM UTC 24
Finished	Oct 15 07:57:38 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752802140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.2752802140
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3280141830
Short name	T246
Test name
Test status
Simulation time	48734500 ps
CPU time	20.88 seconds
Started	Oct 15 07:57:06 AM UTC 24
Finished	Oct 15 07:57:28 AM UTC 24
Peak memory	276372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280141830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.3280141830
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3854678765
Short name	T1134
Test name
Test status
Simulation time	57393400 ps
CPU time	15.74 seconds
Started	Oct 15 07:57:06 AM UTC 24
Finished	Oct 15 07:57:23 AM UTC 24
Peak memory	274560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854678765 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.3854678765
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3441651524
Short name	T253
Test name
Test status
Simulation time	103771300 ps
CPU time	31.29 seconds
Started	Oct 15 07:57:23 AM UTC 24
Finished	Oct 15 07:57:56 AM UTC 24
Peak memory	276608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3441651524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ same_csr_outstanding.3441651524
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2537402340
Short name	T1132
Test name
Test status
Simulation time	23868200 ps
CPU time	27.68 seconds
Started	Oct 15 07:56:39 AM UTC 24
Finished	Oct 15 07:57:08 AM UTC 24
Peak memory	274236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253 7402340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha dow_reg_errors.2537402340
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2325159867
Short name	T1133
Test name
Test status
Simulation time	45488400 ps
CPU time	24.51 seconds
Started	Oct 15 07:56:51 AM UTC 24
Finished	Oct 15 07:57:17 AM UTC 24
Peak memory	274240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2325159867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2325159867
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3791465910
Short name	T230
Test name
Test status
Simulation time	240751100 ps
CPU time	32.87 seconds
Started	Oct 15 07:56:31 AM UTC 24
Finished	Oct 15 07:57:05 AM UTC 24
Peak memory	276364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791465910 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3791465910
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.3175573290
Short name	T1232
Test name
Test status
Simulation time	34924900 ps
CPU time	23.25 seconds
Started	Oct 15 08:05:41 AM UTC 24
Finished	Oct 15 08:06:06 AM UTC 24
Peak memory	274372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175573290 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.3175573290
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1188833987
Short name	T1230
Test name
Test status
Simulation time	17812200 ps
CPU time	19.18 seconds
Started	Oct 15 08:05:41 AM UTC 24
Finished	Oct 15 08:06:01 AM UTC 24
Peak memory	274200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188833987 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.1188833987
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3907476485
Short name	T1237
Test name
Test status
Simulation time	86845800 ps
CPU time	25.55 seconds
Started	Oct 15 08:05:46 AM UTC 24
Finished	Oct 15 08:06:13 AM UTC 24
Peak memory	274196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907476485 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.3907476485
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2418090511
Short name	T1234
Test name
Test status
Simulation time	56670400 ps
CPU time	22.62 seconds
Started	Oct 15 08:05:46 AM UTC 24
Finished	Oct 15 08:06:10 AM UTC 24
Peak memory	274172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418090511 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.2418090511
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1553992452
Short name	T1235
Test name
Test status
Simulation time	15757000 ps
CPU time	21.8 seconds
Started	Oct 15 08:05:47 AM UTC 24
Finished	Oct 15 08:06:10 AM UTC 24
Peak memory	274172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553992452 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.1553992452
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3477615607
Short name	T1233
Test name
Test status
Simulation time	27717500 ps
CPU time	17.38 seconds
Started	Oct 15 08:05:48 AM UTC 24
Finished	Oct 15 08:06:07 AM UTC 24
Peak memory	274260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477615607 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.3477615607
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1358821423
Short name	T1236
Test name
Test status
Simulation time	48359900 ps
CPU time	17.45 seconds
Started	Oct 15 08:05:53 AM UTC 24
Finished	Oct 15 08:06:12 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358821423 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.1358821423
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.658874871
Short name	T1241
Test name
Test status
Simulation time	84181900 ps
CPU time	23.1 seconds
Started	Oct 15 08:06:00 AM UTC 24
Finished	Oct 15 08:06:24 AM UTC 24
Peak memory	274184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658874871 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.658874871
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.277383860
Short name	T1238
Test name
Test status
Simulation time	18064000 ps
CPU time	18.91 seconds
Started	Oct 15 08:06:01 AM UTC 24
Finished	Oct 15 08:06:21 AM UTC 24
Peak memory	274392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277383860 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.277383860
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2313652865
Short name	T1239
Test name
Test status
Simulation time	80492700 ps
CPU time	19.18 seconds
Started	Oct 15 08:06:02 AM UTC 24
Finished	Oct 15 08:06:22 AM UTC 24
Peak memory	274388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313652865 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.2313652865
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1425431727
Short name	T385
Test name
Test status
Simulation time	2628750500 ps
CPU time	46.67 seconds
Started	Oct 15 07:58:10 AM UTC 24
Finished	Oct 15 07:58:59 AM UTC 24
Peak memory	274632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425431727 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.1425431727
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3809503638
Short name	T1141
Test name
Test status
Simulation time	50716800 ps
CPU time	59.31 seconds
Started	Oct 15 07:58:00 AM UTC 24
Finished	Oct 15 07:59:01 AM UTC 24
Peak memory	276408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809503638 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.3809503638
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.337297821
Short name	T242
Test name
Test status
Simulation time	93390100 ps
CPU time	27.27 seconds
Started	Oct 15 07:58:13 AM UTC 24
Finished	Oct 15 07:58:42 AM UTC 24
Peak memory	291000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=337297821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.337297821
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1355428502
Short name	T254
Test name
Test status
Simulation time	189794000 ps
CPU time	19.15 seconds
Started	Oct 15 07:58:02 AM UTC 24
Finished	Oct 15 07:58:23 AM UTC 24
Peak memory	274360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355428502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.1355428502
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.667041576
Short name	T332
Test name
Test status
Simulation time	30208400 ps
CPU time	18.78 seconds
Started	Oct 15 07:57:53 AM UTC 24
Finished	Oct 15 07:58:13 AM UTC 24
Peak memory	274188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667041576 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.667041576
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1019176486
Short name	T247
Test name
Test status
Simulation time	33042100 ps
CPU time	24.76 seconds
Started	Oct 15 07:57:57 AM UTC 24
Finished	Oct 15 07:58:23 AM UTC 24
Peak memory	276560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019176486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.1019176486
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4191813456
Short name	T1138
Test name
Test status
Simulation time	18026800 ps
CPU time	16.61 seconds
Started	Oct 15 07:57:55 AM UTC 24
Finished	Oct 15 07:58:13 AM UTC 24
Peak memory	274368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191813456 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.4191813456
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.745769907
Short name	T300
Test name
Test status
Simulation time	777185800 ps
CPU time	46.06 seconds
Started	Oct 15 07:58:10 AM UTC 24
Finished	Oct 15 07:58:58 AM UTC 24
Peak memory	274360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 745769907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_s ame_csr_outstanding.745769907
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2767705264
Short name	T1137
Test name
Test status
Simulation time	14567000 ps
CPU time	29.34 seconds
Started	Oct 15 07:57:38 AM UTC 24
Finished	Oct 15 07:58:09 AM UTC 24
Peak memory	274436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276 7705264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha dow_reg_errors.2767705264
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1446582602
Short name	T1136
Test name
Test status
Simulation time	15274200 ps
CPU time	19.23 seconds
Started	Oct 15 07:57:42 AM UTC 24
Finished	Oct 15 07:58:02 AM UTC 24
Peak memory	274432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1446582602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1446582602
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2050693226
Short name	T231
Test name
Test status
Simulation time	584352300 ps
CPU time	28.4 seconds
Started	Oct 15 07:57:29 AM UTC 24
Finished	Oct 15 07:57:59 AM UTC 24
Peak memory	276368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050693226 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2050693226
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3338225520
Short name	T259
Test name
Test status
Simulation time	414706600 ps
CPU time	545.95 seconds
Started	Oct 15 07:57:32 AM UTC 24
Finished	Oct 15 08:06:45 AM UTC 24
Peak memory	276692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338225520 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.3338225520
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.627448197
Short name	T1240
Test name
Test status
Simulation time	15625100 ps
CPU time	18.33 seconds
Started	Oct 15 08:06:04 AM UTC 24
Finished	Oct 15 08:06:23 AM UTC 24
Peak memory	274392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627448197 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.627448197
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2758375927
Short name	T1242
Test name
Test status
Simulation time	53499100 ps
CPU time	17.35 seconds
Started	Oct 15 08:06:07 AM UTC 24
Finished	Oct 15 08:06:26 AM UTC 24
Peak memory	274180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758375927 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.2758375927
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1419115129
Short name	T1243
Test name
Test status
Simulation time	27428900 ps
CPU time	17.03 seconds
Started	Oct 15 08:06:08 AM UTC 24
Finished	Oct 15 08:06:26 AM UTC 24
Peak memory	274388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419115129 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.1419115129
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.435631460
Short name	T1244
Test name
Test status
Simulation time	25220000 ps
CPU time	15.77 seconds
Started	Oct 15 08:06:12 AM UTC 24
Finished	Oct 15 08:06:30 AM UTC 24
Peak memory	274456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435631460 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.435631460
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.620464639
Short name	T1247
Test name
Test status
Simulation time	44806100 ps
CPU time	23.47 seconds
Started	Oct 15 08:06:13 AM UTC 24
Finished	Oct 15 08:06:38 AM UTC 24
Peak memory	274184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620464639 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.620464639
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.946086193
Short name	T1248
Test name
Test status
Simulation time	15794900 ps
CPU time	25.27 seconds
Started	Oct 15 08:06:13 AM UTC 24
Finished	Oct 15 08:06:40 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946086193 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.946086193
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.179459435
Short name	T1246
Test name
Test status
Simulation time	59758800 ps
CPU time	21.98 seconds
Started	Oct 15 08:06:14 AM UTC 24
Finished	Oct 15 08:06:37 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179459435 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.179459435
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.983884865
Short name	T1245
Test name
Test status
Simulation time	40609500 ps
CPU time	16.03 seconds
Started	Oct 15 08:06:14 AM UTC 24
Finished	Oct 15 08:06:31 AM UTC 24
Peak memory	274196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983884865 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.983884865
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3220505835
Short name	T1254
Test name
Test status
Simulation time	17358000 ps
CPU time	22.26 seconds
Started	Oct 15 08:06:23 AM UTC 24
Finished	Oct 15 08:06:47 AM UTC 24
Peak memory	274172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220505835 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.3220505835
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2513757932
Short name	T1252
Test name
Test status
Simulation time	28958400 ps
CPU time	20.38 seconds
Started	Oct 15 08:06:23 AM UTC 24
Finished	Oct 15 08:06:45 AM UTC 24
Peak memory	274188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513757932 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.2513757932
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1880526596
Short name	T1148
Test name
Test status
Simulation time	415905800 ps
CPU time	81.88 seconds
Started	Oct 15 07:59:00 AM UTC 24
Finished	Oct 15 08:00:23 AM UTC 24
Peak memory	274368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880526596 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.1880526596
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3564055594
Short name	T388
Test name
Test status
Simulation time	2197112400 ps
CPU time	89.6 seconds
Started	Oct 15 07:58:59 AM UTC 24
Finished	Oct 15 08:00:30 AM UTC 24
Peak memory	276408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564055594 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.3564055594
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3250769011
Short name	T303
Test name
Test status
Simulation time	140829900 ps
CPU time	79.6 seconds
Started	Oct 15 07:58:49 AM UTC 24
Finished	Oct 15 08:00:11 AM UTC 24
Peak memory	276600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250769011 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.3250769011
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1919100206
Short name	T301
Test name
Test status
Simulation time	57717300 ps
CPU time	31.51 seconds
Started	Oct 15 07:59:04 AM UTC 24
Finished	Oct 15 07:59:37 AM UTC 24
Peak memory	276480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1919100206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1919100206
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4230554284
Short name	T384
Test name
Test status
Simulation time	57030200 ps
CPU time	20.72 seconds
Started	Oct 15 07:58:50 AM UTC 24
Finished	Oct 15 07:59:12 AM UTC 24
Peak memory	276404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230554284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.4230554284
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4160407810
Short name	T333
Test name
Test status
Simulation time	39461900 ps
CPU time	23.83 seconds
Started	Oct 15 07:58:38 AM UTC 24
Finished	Oct 15 07:59:03 AM UTC 24
Peak memory	274172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160407810 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.4160407810
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3106310443
Short name	T248
Test name
Test status
Simulation time	18430100 ps
CPU time	24.76 seconds
Started	Oct 15 07:58:43 AM UTC 24
Finished	Oct 15 07:59:09 AM UTC 24
Peak memory	276372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106310443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.3106310443
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.188114236
Short name	T1142
Test name
Test status
Simulation time	45695700 ps
CPU time	23.34 seconds
Started	Oct 15 07:58:41 AM UTC 24
Finished	Oct 15 07:59:06 AM UTC 24
Peak memory	274504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188114236 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.188114236
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1800963594
Short name	T1144
Test name
Test status
Simulation time	223908100 ps
CPU time	38.27 seconds
Started	Oct 15 07:59:02 AM UTC 24
Finished	Oct 15 07:59:42 AM UTC 24
Peak memory	276412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1800963594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ same_csr_outstanding.1800963594
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.725487113
Short name	T1139
Test name
Test status
Simulation time	20497500 ps
CPU time	24.82 seconds
Started	Oct 15 07:58:23 AM UTC 24
Finished	Oct 15 07:58:49 AM UTC 24
Peak memory	274480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725 487113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shad ow_reg_errors.725487113
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1274001464
Short name	T1140
Test name
Test status
Simulation time	16115700 ps
CPU time	24.52 seconds
Started	Oct 15 07:58:24 AM UTC 24
Finished	Oct 15 07:58:50 AM UTC 24
Peak memory	274220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1274001464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1274001464
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.64232652
Short name	T375
Test name
Test status
Simulation time	239039900 ps
CPU time	709.1 seconds
Started	Oct 15 07:58:16 AM UTC 24
Finished	Oct 15 08:10:14 AM UTC 24
Peak memory	276484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64232652 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.64232652
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.405940950
Short name	T1250
Test name
Test status
Simulation time	26339100 ps
CPU time	17.76 seconds
Started	Oct 15 08:06:24 AM UTC 24
Finished	Oct 15 08:06:42 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405940950 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.405940950
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1894029306
Short name	T1253
Test name
Test status
Simulation time	63925500 ps
CPU time	20.41 seconds
Started	Oct 15 08:06:25 AM UTC 24
Finished	Oct 15 08:06:46 AM UTC 24
Peak memory	273464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894029306 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.1894029306
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.4170374599
Short name	T1249
Test name
Test status
Simulation time	30370900 ps
CPU time	16.02 seconds
Started	Oct 15 08:06:25 AM UTC 24
Finished	Oct 15 08:06:42 AM UTC 24
Peak memory	274188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170374599 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.4170374599
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.748733741
Short name	T1251
Test name
Test status
Simulation time	21528300 ps
CPU time	15.75 seconds
Started	Oct 15 08:06:27 AM UTC 24
Finished	Oct 15 08:06:44 AM UTC 24
Peak memory	274176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748733741 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.748733741
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2959511601
Short name	T1255
Test name
Test status
Simulation time	129211900 ps
CPU time	25.37 seconds
Started	Oct 15 08:06:27 AM UTC 24
Finished	Oct 15 08:06:53 AM UTC 24
Peak memory	274196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959511601 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.2959511601
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.735512836
Short name	T1256
Test name
Test status
Simulation time	15559500 ps
CPU time	22.69 seconds
Started	Oct 15 08:06:31 AM UTC 24
Finished	Oct 15 08:06:55 AM UTC 24
Peak memory	274200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735512836 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.735512836
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2259335663
Short name	T1259
Test name
Test status
Simulation time	32029800 ps
CPU time	25.38 seconds
Started	Oct 15 08:06:32 AM UTC 24
Finished	Oct 15 08:06:59 AM UTC 24
Peak memory	274372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259335663 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.2259335663
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.1178976886
Short name	T1257
Test name
Test status
Simulation time	55208500 ps
CPU time	17.77 seconds
Started	Oct 15 08:06:38 AM UTC 24
Finished	Oct 15 08:06:57 AM UTC 24
Peak memory	274192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178976886 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.1178976886
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.3276461086
Short name	T1258
Test name
Test status
Simulation time	17323000 ps
CPU time	19.3 seconds
Started	Oct 15 08:06:38 AM UTC 24
Finished	Oct 15 08:06:59 AM UTC 24
Peak memory	274372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276461086 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.3276461086
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.3940472166
Short name	T1260
Test name
Test status
Simulation time	62150800 ps
CPU time	23.34 seconds
Started	Oct 15 08:06:40 AM UTC 24
Finished	Oct 15 08:07:05 AM UTC 24
Peak memory	274180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940472166 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.3940472166
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4268617381
Short name	T302
Test name
Test status
Simulation time	62058400 ps
CPU time	21.53 seconds
Started	Oct 15 07:59:37 AM UTC 24
Finished	Oct 15 07:59:59 AM UTC 24
Peak memory	286720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4268617381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4268617381
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.163082657
Short name	T387
Test name
Test status
Simulation time	347381600 ps
CPU time	29.27 seconds
Started	Oct 15 07:59:31 AM UTC 24
Finished	Oct 15 08:00:01 AM UTC 24
Peak memory	274564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163082657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.163082657
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2597709987
Short name	T336
Test name
Test status
Simulation time	14952900 ps
CPU time	24.01 seconds
Started	Oct 15 07:59:26 AM UTC 24
Finished	Oct 15 07:59:52 AM UTC 24
Peak memory	274244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597709987 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2597709987
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2962915614
Short name	T1149
Test name
Test status
Simulation time	544918300 ps
CPU time	54.95 seconds
Started	Oct 15 07:59:36 AM UTC 24
Finished	Oct 15 08:00:32 AM UTC 24
Peak memory	276592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2962915614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ same_csr_outstanding.2962915614
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.919331328
Short name	T1143
Test name
Test status
Simulation time	13100900 ps
CPU time	24.09 seconds
Started	Oct 15 07:59:10 AM UTC 24
Finished	Oct 15 07:59:36 AM UTC 24
Peak memory	274432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919 331328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shad ow_reg_errors.919331328
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1599841892
Short name	T1145
Test name
Test status
Simulation time	86529800 ps
CPU time	29.31 seconds
Started	Oct 15 07:59:13 AM UTC 24
Finished	Oct 15 07:59:44 AM UTC 24
Peak memory	274240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1599841892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1599841892
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1229629533
Short name	T270
Test name
Test status
Simulation time	55956200 ps
CPU time	28.84 seconds
Started	Oct 15 07:59:04 AM UTC 24
Finished	Oct 15 07:59:34 AM UTC 24
Peak memory	276348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229629533 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1229629533
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1523001392
Short name	T374
Test name
Test status
Simulation time	2031353300 ps
CPU time	1133.67 seconds
Started	Oct 15 07:59:07 AM UTC 24
Finished	Oct 15 08:18:15 AM UTC 24
Peak memory	276688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523001392 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.1523001392
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.142689126
Short name	T306
Test name
Test status
Simulation time	428245200 ps
CPU time	33.79 seconds
Started	Oct 15 08:00:09 AM UTC 24
Finished	Oct 15 08:00:44 AM UTC 24
Peak memory	286716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=142689126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.142689126
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.621281972
Short name	T304
Test name
Test status
Simulation time	38602500 ps
CPU time	24.74 seconds
Started	Oct 15 08:00:00 AM UTC 24
Finished	Oct 15 08:00:26 AM UTC 24
Peak memory	274364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621281972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.621281972
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2614470887
Short name	T335
Test name
Test status
Simulation time	53582200 ps
CPU time	24.46 seconds
Started	Oct 15 07:59:53 AM UTC 24
Finished	Oct 15 08:00:19 AM UTC 24
Peak memory	274372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614470887 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2614470887
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1211773036
Short name	T305
Test name
Test status
Simulation time	181276200 ps
CPU time	20.07 seconds
Started	Oct 15 08:00:02 AM UTC 24
Finished	Oct 15 08:00:27 AM UTC 24
Peak memory	276400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1211773036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ same_csr_outstanding.1211773036
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1988770573
Short name	T1147
Test name
Test status
Simulation time	19810300 ps
CPU time	28.41 seconds
Started	Oct 15 07:59:43 AM UTC 24
Finished	Oct 15 08:00:12 AM UTC 24
Peak memory	274436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198 8770573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha dow_reg_errors.1988770573
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.794358227
Short name	T1146
Test name
Test status
Simulation time	138094200 ps
CPU time	25.16 seconds
Started	Oct 15 07:59:45 AM UTC 24
Finished	Oct 15 08:00:11 AM UTC 24
Peak memory	274240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=794358227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_shadow_reg_errors_with_csr_rw.794358227
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1175601887
Short name	T243
Test name
Test status
Simulation time	98872900 ps
CPU time	28.92 seconds
Started	Oct 15 07:59:38 AM UTC 24
Finished	Oct 15 08:00:08 AM UTC 24
Peak memory	276372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175601887 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1175601887
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.613680846
Short name	T1154
Test name
Test status
Simulation time	120592200 ps
CPU time	27.25 seconds
Started	Oct 15 08:00:28 AM UTC 24
Finished	Oct 15 08:00:57 AM UTC 24
Peak memory	286716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=613680846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.613680846
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4108598099
Short name	T1153
Test name
Test status
Simulation time	39872200 ps
CPU time	22.13 seconds
Started	Oct 15 08:00:24 AM UTC 24
Finished	Oct 15 08:00:47 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108598099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.4108598099
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2456701905
Short name	T1152
Test name
Test status
Simulation time	15433300 ps
CPU time	22.61 seconds
Started	Oct 15 08:00:20 AM UTC 24
Finished	Oct 15 08:00:44 AM UTC 24
Peak memory	274388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456701905 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2456701905
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1486376768
Short name	T307
Test name
Test status
Simulation time	395228000 ps
CPU time	32.97 seconds
Started	Oct 15 08:00:27 AM UTC 24
Finished	Oct 15 08:01:02 AM UTC 24
Peak memory	276404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1486376768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ same_csr_outstanding.1486376768
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3034857487
Short name	T1151
Test name
Test status
Simulation time	37184600 ps
CPU time	27.72 seconds
Started	Oct 15 08:00:13 AM UTC 24
Finished	Oct 15 08:00:43 AM UTC 24
Peak memory	274500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303 4857487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha dow_reg_errors.3034857487
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.66189362
Short name	T1150
Test name
Test status
Simulation time	36133400 ps
CPU time	22.7 seconds
Started	Oct 15 08:00:19 AM UTC 24
Finished	Oct 15 08:00:43 AM UTC 24
Peak memory	274236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=66189362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_shadow_reg_errors_with_csr_rw.66189362
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2755260249
Short name	T267
Test name
Test status
Simulation time	38805000 ps
CPU time	27.5 seconds
Started	Oct 15 08:00:12 AM UTC 24
Finished	Oct 15 08:00:42 AM UTC 24
Peak memory	276368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755260249 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2755260249
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.486410241
Short name	T260
Test name
Test status
Simulation time	4194368100 ps
CPU time	485.22 seconds
Started	Oct 15 08:00:12 AM UTC 24
Finished	Oct 15 08:08:24 AM UTC 24
Peak memory	276488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486410241 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.486410241
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2089429932
Short name	T272
Test name
Test status
Simulation time	311778300 ps
CPU time	33.59 seconds
Started	Oct 15 08:00:45 AM UTC 24
Finished	Oct 15 08:01:20 AM UTC 24
Peak memory	286720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2089429932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2089429932
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2248530785
Short name	T1157
Test name
Test status
Simulation time	85020600 ps
CPU time	22.71 seconds
Started	Oct 15 08:00:44 AM UTC 24
Finished	Oct 15 08:01:08 AM UTC 24
Peak memory	274308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248530785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.2248530785
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.547584529
Short name	T334
Test name
Test status
Simulation time	31442600 ps
CPU time	16.41 seconds
Started	Oct 15 08:00:44 AM UTC 24
Finished	Oct 15 08:01:01 AM UTC 24
Peak memory	274180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547584529 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.547584529
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3310680166
Short name	T1156
Test name
Test status
Simulation time	826867000 ps
CPU time	19.57 seconds
Started	Oct 15 08:00:45 AM UTC 24
Finished	Oct 15 08:01:06 AM UTC 24
Peak memory	276400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3310680166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ same_csr_outstanding.3310680166
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2279456184
Short name	T1155
Test name
Test status
Simulation time	13638200 ps
CPU time	28.04 seconds
Started	Oct 15 08:00:33 AM UTC 24
Finished	Oct 15 08:01:02 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227 9456184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha dow_reg_errors.2279456184
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1621233533
Short name	T1158
Test name
Test status
Simulation time	34726800 ps
CPU time	25.22 seconds
Started	Oct 15 08:00:43 AM UTC 24
Finished	Oct 15 08:01:09 AM UTC 24
Peak memory	274212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1621233533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1621233533
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.238866307
Short name	T268
Test name
Test status
Simulation time	58519200 ps
CPU time	30.86 seconds
Started	Oct 15 08:00:32 AM UTC 24
Finished	Oct 15 08:01:04 AM UTC 24
Peak memory	276372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238866307 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.238866307
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3078473865
Short name	T378
Test name
Test status
Simulation time	1341756100 ps
CPU time	1005.22 seconds
Started	Oct 15 08:00:32 AM UTC 24
Finished	Oct 15 08:17:28 AM UTC 24
Peak memory	276752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078473865 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.3078473865
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.191039471
Short name	T1162
Test name
Test status
Simulation time	107208200 ps
CPU time	28.91 seconds
Started	Oct 15 08:01:06 AM UTC 24
Finished	Oct 15 08:01:37 AM UTC 24
Peak memory	276476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=191039471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.191039471
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4066302104
Short name	T1161
Test name
Test status
Simulation time	62593700 ps
CPU time	29 seconds
Started	Oct 15 08:01:05 AM UTC 24
Finished	Oct 15 08:01:35 AM UTC 24
Peak memory	274356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066302104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.4066302104
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1181560223
Short name	T1166
Test name
Test status
Simulation time	166280900 ps
CPU time	45.47 seconds
Started	Oct 15 08:01:05 AM UTC 24
Finished	Oct 15 08:01:52 AM UTC 24
Peak memory	274348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1181560223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ same_csr_outstanding.1181560223
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2141483318
Short name	T1160
Test name
Test status
Simulation time	26197700 ps
CPU time	28.65 seconds
Started	Oct 15 08:01:02 AM UTC 24
Finished	Oct 15 08:01:32 AM UTC 24
Peak memory	274436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214 1483318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha dow_reg_errors.2141483318
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.229209655
Short name	T1159
Test name
Test status
Simulation time	25204500 ps
CPU time	18.16 seconds
Started	Oct 15 08:01:02 AM UTC 24
Finished	Oct 15 08:01:22 AM UTC 24
Peak memory	274216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=229209655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_shadow_reg_errors_with_csr_rw.229209655
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.622436909
Short name	T379
Test name
Test status
Simulation time	373600200 ps
CPU time	1090.38 seconds
Started	Oct 15 08:00:57 AM UTC 24
Finished	Oct 15 08:19:20 AM UTC 24
Peak memory	276624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622436909 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.622436909
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.1158029578
Short name	T255
Test name
Test status
Simulation time	52769500 ps
CPU time	27.1 seconds
Started	Oct 15 08:22:08 AM UTC 24
Finished	Oct 15 08:22:37 AM UTC 24
Peak memory	272648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158029578 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.1158029578
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3457436874
Short name	T23
Test name
Test status
Simulation time	32252400 ps
CPU time	20.07 seconds
Started	Oct 15 08:21:53 AM UTC 24
Finished	Oct 15 08:22:14 AM UTC 24
Peak memory	284828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457436874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3457436874
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.354191537
Short name	T5
Test name
Test status
Simulation time	29170200 ps
CPU time	38.79 seconds
Started	Oct 15 08:21:22 AM UTC 24
Finished	Oct 15 08:22:02 AM UTC 24
Peak memory	285340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=354191537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct rl_disable.354191537
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.3406650408
Short name	T297
Test name
Test status
Simulation time	635643900 ps
CPU time	1156.62 seconds
Started	Oct 15 08:17:55 AM UTC 24
Finished	Oct 15 08:37:25 AM UTC 24
Peak memory	285160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406650408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3406650408
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.875433068
Short name	T110
Test name
Test status
Simulation time	994582500 ps
CPU time	52.14 seconds
Started	Oct 15 08:21:58 AM UTC 24
Finished	Oct 15 08:22:52 AM UTC 24
Peak memory	275028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8754330 68 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fs _sup.875433068
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.2953790858
Short name	T163
Test name
Test status
Simulation time	108583595400 ps
CPU time	3426.47 seconds
Started	Oct 15 08:17:34 AM UTC 24
Finished	Oct 15 09:15:18 AM UTC 24
Peak memory	277628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953790858 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.2953790858
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2761391273
Short name	T313
Test name
Test status
Simulation time	27561600 ps
CPU time	51.53 seconds
Started	Oct 15 08:22:34 AM UTC 24
Finished	Oct 15 08:23:27 AM UTC 24
Peak memory	281160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276139127 3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho st_addr_infection.2761391273
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3008128612
Short name	T10
Test name
Test status
Simulation time	261194100 ps
CPU time	166.18 seconds
Started	Oct 15 08:17:03 AM UTC 24
Finished	Oct 15 08:19:52 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008128612 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3008128612
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.3130485095
Short name	T28
Test name
Test status
Simulation time	170183466800 ps
CPU time	870.69 seconds
Started	Oct 15 08:17:10 AM UTC 24
Finished	Oct 15 08:31:51 AM UTC 24
Peak memory	272824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130485095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.3130485095
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3213835480
Short name	T203
Test name
Test status
Simulation time	2849228300 ps
CPU time	558.98 seconds
Started	Oct 15 08:20:32 AM UTC 24
Finished	Oct 15 08:29:59 AM UTC 24
Peak memory	332636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3213835480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr ity.3213835480
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3259722748
Short name	T52
Test name
Test status
Simulation time	1738286400 ps
CPU time	225.84 seconds
Started	Oct 15 08:20:38 AM UTC 24
Finished	Oct 15 08:24:28 AM UTC 24
Peak memory	301696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259722748 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.3259722748
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.4030871073
Short name	T45
Test name
Test status
Simulation time	78764491800 ps
CPU time	212.16 seconds
Started	Oct 15 08:20:55 AM UTC 24
Finished	Oct 15 08:24:31 AM UTC 24
Peak memory	275092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030871073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.4030871073
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.3976914117
Short name	T138
Test name
Test status
Simulation time	46988300 ps
CPU time	20.16 seconds
Started	Oct 15 08:22:20 AM UTC 24
Finished	Oct 15 08:22:42 AM UTC 24
Peak memory	272912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3976914117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_lcmgr_intg.3976914117
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2874501101
Short name	T26
Test name
Test status
Simulation time	3944362600 ps
CPU time	117.41 seconds
Started	Oct 15 08:18:20 AM UTC 24
Finished	Oct 15 08:20:20 AM UTC 24
Peak memory	270708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874501101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2874501101
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.1808803186
Short name	T60
Test name
Test status
Simulation time	1539634900 ps
CPU time	206.36 seconds
Started	Oct 15 08:20:21 AM UTC 24
Finished	Oct 15 08:23:50 AM UTC 24
Peak memory	291516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1808803186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.1808803186
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2314338414
Short name	T64
Test name
Test status
Simulation time	194593800 ps
CPU time	25.4 seconds
Started	Oct 15 08:22:08 AM UTC 24
Finished	Oct 15 08:22:35 AM UTC 24
Peak memory	292892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314338414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2314338414
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.287700211
Short name	T59
Test name
Test status
Simulation time	114450600 ps
CPU time	283 seconds
Started	Oct 15 08:17:03 AM UTC 24
Finished	Oct 15 08:21:50 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287700211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.287700211
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.500085504
Short name	T148
Test name
Test status
Simulation time	146210300 ps
CPU time	21.85 seconds
Started	Oct 15 08:20:58 AM UTC 24
Finished	Oct 15 08:21:21 AM UTC 24
Peak memory	274904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500085504 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.500085504
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.3758438699
Short name	T171
Test name
Test status
Simulation time	173863100 ps
CPU time	1062.69 seconds
Started	Oct 15 08:17:01 AM UTC 24
Finished	Oct 15 08:34:55 AM UTC 24
Peak memory	296116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758438699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3758438699
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.57533282
Short name	T20
Test name
Test status
Simulation time	5511492000 ps
CPU time	185.97 seconds
Started	Oct 15 08:17:03 AM UTC 24
Finished	Oct 15 08:20:12 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57533282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.57533282
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.965400185
Short name	T216
Test name
Test status
Simulation time	146484900 ps
CPU time	65.83 seconds
Started	Oct 15 08:22:27 AM UTC 24
Finished	Oct 15 08:23:34 AM UTC 24
Peak memory	285392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965400185 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.965400185
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.2564533186
Short name	T16
Test name
Test status
Simulation time	41455200 ps
CPU time	25.79 seconds
Started	Oct 15 08:18:31 AM UTC 24
Finished	Oct 15 08:18:58 AM UTC 24
Peak memory	268944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564533186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.2564533186
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.210061485
Short name	T70
Test name
Test status
Simulation time	30554300 ps
CPU time	39.55 seconds
Started	Oct 15 08:19:56 AM UTC 24
Finished	Oct 15 08:20:37 AM UTC 24
Peak memory	275200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=210061485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_read_word_sweep_derr.210061485
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.3767536671
Short name	T17
Test name
Test status
Simulation time	133520200 ps
CPU time	41.36 seconds
Started	Oct 15 08:19:09 AM UTC 24
Finished	Oct 15 08:19:52 AM UTC 24
Peak memory	275092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767536671 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.3767536671
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2084835346
Short name	T67
Test name
Test status
Simulation time	525028200 ps
CPU time	155.76 seconds
Started	Oct 15 08:18:57 AM UTC 24
Finished	Oct 15 08:21:36 AM UTC 24
Peak memory	301772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2084835346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.2084835346
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.232336290
Short name	T40
Test name
Test status
Simulation time	42779100 ps
CPU time	34.47 seconds
Started	Oct 15 08:21:18 AM UTC 24
Finished	Oct 15 08:21:54 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=232336290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctr l_rw_evict_all_en.232336290
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.4246164988
Short name	T104
Test name
Test status
Simulation time	1561575300 ps
CPU time	218.76 seconds
Started	Oct 15 08:19:42 AM UTC 24
Finished	Oct 15 08:23:24 AM UTC 24
Peak memory	291604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4246164988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.4246164988
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.1144065921
Short name	T76
Test name
Test status
Simulation time	731283700 ps
CPU time	64.97 seconds
Started	Oct 15 08:19:53 AM UTC 24
Finished	Oct 15 08:21:00 AM UTC 24
Peak memory	275140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114 4065921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_address.1144065921
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.333387439
Short name	T1
Test name
Test status
Simulation time	15802300 ps
CPU time	31.52 seconds
Started	Oct 15 08:17:00 AM UTC 24
Finished	Oct 15 08:17:33 AM UTC 24
Peak memory	270880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333387439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.333387439
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.4142222960
Short name	T2
Test name
Test status
Simulation time	39889800 ps
CPU time	49.82 seconds
Started	Oct 15 08:17:03 AM UTC 24
Finished	Oct 15 08:17:54 AM UTC 24
Peak memory	270684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142222960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4142222960
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.1103510052
Short name	T88
Test name
Test status
Simulation time	29261769600 ps
CPU time	207.47 seconds
Started	Oct 15 08:18:27 AM UTC 24
Finished	Oct 15 08:21:58 AM UTC 24
Peak memory	275232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1103510052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.1103510052
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.4203720627
Short name	T9
Test name
Test status
Simulation time	45221700 ps
CPU time	26.98 seconds
Started	Oct 15 08:18:28 AM UTC 24
Finished	Oct 15 08:18:56 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203720627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.4203720627
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2498734867
Short name	T21
Test name
Test status
Simulation time	23584600 ps
CPU time	24.02 seconds
Started	Oct 15 08:26:32 AM UTC 24
Finished	Oct 15 08:26:57 AM UTC 24
Peak memory	273036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2498734867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2498734867
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2884821376
Short name	T121
Test name
Test status
Simulation time	194394700 ps
CPU time	21.58 seconds
Started	Oct 15 08:26:55 AM UTC 24
Finished	Oct 15 08:27:18 AM UTC 24
Peak memory	268944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884821376 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2884821376
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.4152108760
Short name	T72
Test name
Test status
Simulation time	358207900 ps
CPU time	301.17 seconds
Started	Oct 15 08:22:49 AM UTC 24
Finished	Oct 15 08:27:54 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152108760 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.4152108760
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.3124069172
Short name	T294
Test name
Test status
Simulation time	51719184700 ps
CPU time	2698.64 seconds
Started	Oct 15 08:23:36 AM UTC 24
Finished	Oct 15 09:09:02 AM UTC 24
Peak memory	275640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124069172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.3124069172
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.1215987877
Short name	T298
Test name
Test status
Simulation time	567080400 ps
CPU time	969.08 seconds
Started	Oct 15 08:23:32 AM UTC 24
Finished	Oct 15 08:39:52 AM UTC 24
Peak memory	285288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215987877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1215987877
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.2154801575
Short name	T58
Test name
Test status
Simulation time	1441306800 ps
CPU time	38.18 seconds
Started	Oct 15 08:23:15 AM UTC 24
Finished	Oct 15 08:23:55 AM UTC 24
Peak memory	272980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 54801575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc h_code.2154801575
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3990722539
Short name	T283
Test name
Test status
Simulation time	340320300 ps
CPU time	43.53 seconds
Started	Oct 15 08:26:34 AM UTC 24
Finished	Oct 15 08:27:19 AM UTC 24
Peak memory	275000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990722 539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f s_sup.3990722539
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.475801514
Short name	T162
Test name
Test status
Simulation time	216085910700 ps
CPU time	2947.12 seconds
Started	Oct 15 08:23:25 AM UTC 24
Finished	Oct 15 09:13:06 AM UTC 24
Peak memory	287884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475801514 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.475801514
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.227529267
Short name	T312
Test name
Test status
Simulation time	36235000 ps
CPU time	33.15 seconds
Started	Oct 15 08:26:55 AM UTC 24
Finished	Oct 15 08:27:29 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227529267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hos t_addr_infection.227529267
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.834350489
Short name	T227
Test name
Test status
Simulation time	82743600 ps
CPU time	127.23 seconds
Started	Oct 15 08:22:44 AM UTC 24
Finished	Oct 15 08:24:54 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834350489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.834350489
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3834904758
Short name	T32
Test name
Test status
Simulation time	10012289200 ps
CPU time	138.37 seconds
Started	Oct 15 08:26:54 AM UTC 24
Finished	Oct 15 08:29:14 AM UTC 24
Peak memory	336800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3834904758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3834904758
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.2628967647
Short name	T181
Test name
Test status
Simulation time	25724600 ps
CPU time	22.81 seconds
Started	Oct 15 08:26:53 AM UTC 24
Finished	Oct 15 08:27:17 AM UTC 24
Peak memory	275152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2628967647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2628967647
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.1567377383
Short name	T29
Test name
Test status
Simulation time	40121644700 ps
CPU time	793.05 seconds
Started	Oct 15 08:22:53 AM UTC 24
Finished	Oct 15 08:36:15 AM UTC 24
Peak memory	274744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567377383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.1567377383
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3727950207
Short name	T125
Test name
Test status
Simulation time	6019633800 ps
CPU time	166.51 seconds
Started	Oct 15 08:22:47 AM UTC 24
Finished	Oct 15 08:25:37 AM UTC 24
Peak memory	272804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727950207 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.3727950207
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3851751253
Short name	T448
Test name
Test status
Simulation time	3064061700 ps
CPU time	593.56 seconds
Started	Oct 15 08:24:58 AM UTC 24
Finished	Oct 15 08:34:59 AM UTC 24
Peak memory	326364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3851751253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr ity.3851751253
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3265113646
Short name	T54
Test name
Test status
Simulation time	48882295600 ps
CPU time	518.56 seconds
Started	Oct 15 08:25:17 AM UTC 24
Finished	Oct 15 08:34:03 AM UTC 24
Peak memory	303804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3265113646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_intr_rd_slow_flash.3265113646
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.4282151548
Short name	T46
Test name
Test status
Simulation time	2418402200 ps
CPU time	91.04 seconds
Started	Oct 15 08:25:08 AM UTC 24
Finished	Oct 15 08:26:41 AM UTC 24
Peak memory	275148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282151548 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.4282151548
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3574277056
Short name	T84
Test name
Test status
Simulation time	19394913100 ps
CPU time	239.72 seconds
Started	Oct 15 08:25:38 AM UTC 24
Finished	Oct 15 08:29:41 AM UTC 24
Peak memory	270916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574277056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3574277056
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.42854273
Short name	T61
Test name
Test status
Simulation time	7700503900 ps
CPU time	64.27 seconds
Started	Oct 15 08:23:39 AM UTC 24
Finished	Oct 15 08:24:45 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42854273 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.42854273
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.991208881
Short name	T182
Test name
Test status
Simulation time	25355500 ps
CPU time	23.81 seconds
Started	Oct 15 08:26:48 AM UTC 24
Finished	Oct 15 08:27:13 AM UTC 24
Peak memory	270892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=991208881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_lcmgr_intg.991208881
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.2724033046
Short name	T71
Test name
Test status
Simulation time	19032493400 ps
CPU time	94.94 seconds
Started	Oct 15 08:23:39 AM UTC 24
Finished	Oct 15 08:25:16 AM UTC 24
Peak memory	270772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724033046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2724033046
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.30639629
Short name	T86
Test name
Test status
Simulation time	5624658700 ps
CPU time	530.81 seconds
Started	Oct 15 08:23:11 AM UTC 24
Finished	Oct 15 08:32:09 AM UTC 24
Peak memory	283280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=30639629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_mp_regions.30639629
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.2761251585
Short name	T33
Test name
Test status
Simulation time	43171400 ps
CPU time	217.68 seconds
Started	Oct 15 08:22:58 AM UTC 24
Finished	Oct 15 08:26:39 AM UTC 24
Peak memory	270832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761251585 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.2761251585
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.424899973
Short name	T74
Test name
Test status
Simulation time	15738600 ps
CPU time	21.07 seconds
Started	Oct 15 08:26:42 AM UTC 24
Finished	Oct 15 08:27:04 AM UTC 24
Peak memory	293068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424899973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.424899973
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2222322968
Short name	T234
Test name
Test status
Simulation time	122871600 ps
CPU time	198.08 seconds
Started	Oct 15 08:22:47 AM UTC 24
Finished	Oct 15 08:26:09 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222322968 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2222322968
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.818100782
Short name	T101
Test name
Test status
Simulation time	737209400 ps
CPU time	29.57 seconds
Started	Oct 15 08:26:38 AM UTC 24
Finished	Oct 15 08:27:09 AM UTC 24
Peak memory	275416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=818100782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.818100782
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.1361777513
Short name	T217
Test name
Test status
Simulation time	26593600 ps
CPU time	25.12 seconds
Started	Oct 15 08:26:40 AM UTC 24
Finished	Oct 15 08:27:06 AM UTC 24
Peak memory	273244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1361777513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1361777513
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.53335729
Short name	T397
Test name
Test status
Simulation time	37224300 ps
CPU time	25.38 seconds
Started	Oct 15 08:25:41 AM UTC 24
Finished	Oct 15 08:26:07 AM UTC 24
Peak memory	275100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53335729 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.53335729
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2404858845
Short name	T460
Test name
Test status
Simulation time	90782100 ps
CPU time	880.74 seconds
Started	Oct 15 08:22:44 AM UTC 24
Finished	Oct 15 08:37:35 AM UTC 24
Peak memory	293332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404858845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2404858845
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1756943856
Short name	T353
Test name
Test status
Simulation time	548018000 ps
CPU time	46.47 seconds
Started	Oct 15 08:26:10 AM UTC 24
Finished	Oct 15 08:26:58 AM UTC 24
Peak memory	287528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175694385 6 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.1756943856
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.2345998992
Short name	T228
Test name
Test status
Simulation time	82417900 ps
CPU time	47.35 seconds
Started	Oct 15 08:26:05 AM UTC 24
Finished	Oct 15 08:26:54 AM UTC 24
Peak memory	285396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345998992 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.2345998992
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.769052628
Short name	T309
Test name
Test status
Simulation time	89853700 ps
CPU time	34.81 seconds
Started	Oct 15 08:24:31 AM UTC 24
Finished	Oct 15 08:25:08 AM UTC 24
Peak memory	275072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=769052628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_read_word_sweep_derr.769052628
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3827740763
Short name	T401
Test name
Test status
Simulation time	84627600 ps
CPU time	29.81 seconds
Started	Oct 15 08:23:56 AM UTC 24
Finished	Oct 15 08:24:27 AM UTC 24
Peak memory	275076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827740763 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.3827740763
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.3475228348
Short name	T108
Test name
Test status
Simulation time	39763190000 ps
CPU time	966.85 seconds
Started	Oct 15 08:26:47 AM UTC 24
Finished	Oct 15 08:43:05 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3475228348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_rma_err.3475228348
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2650814771
Short name	T241
Test name
Test status
Simulation time	2160567400 ps
CPU time	138.37 seconds
Started	Oct 15 08:23:47 AM UTC 24
Finished	Oct 15 08:26:08 AM UTC 24
Peak memory	308032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2650814771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.2650814771
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1067219357
Short name	T215
Test name
Test status
Simulation time	2388442100 ps
CPU time	150.95 seconds
Started	Oct 15 08:24:46 AM UTC 24
Finished	Oct 15 08:27:19 AM UTC 24
Peak memory	291664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067219357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1067219357
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.713843433
Short name	T124
Test name
Test status
Simulation time	747498400 ps
CPU time	174.46 seconds
Started	Oct 15 08:24:08 AM UTC 24
Finished	Oct 15 08:27:06 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=713843433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ ctrl_ro_serr.713843433
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.1844266443
Short name	T175
Test name
Test status
Simulation time	3319012700 ps
CPU time	238.34 seconds
Started	Oct 15 08:24:48 AM UTC 24
Finished	Oct 15 08:28:50 AM UTC 24
Peak memory	291516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1844266443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.flash_ctrl_rw_derr.1844266443
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.670419801
Short name	T43
Test name
Test status
Simulation time	30763700 ps
CPU time	41.33 seconds
Started	Oct 15 08:25:50 AM UTC 24
Finished	Oct 15 08:26:33 AM UTC 24
Peak memory	287560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670419801 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.670419801
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.3524037638
Short name	T405
Test name
Test status
Simulation time	1808609300 ps
CPU time	214.4 seconds
Started	Oct 15 08:24:23 AM UTC 24
Finished	Oct 15 08:28:01 AM UTC 24
Peak memory	305860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3524037638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.3524037638
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3749099413
Short name	T13
Test name
Test status
Simulation time	8521785100 ps
CPU time	6272.1 seconds
Started	Oct 15 08:26:07 AM UTC 24
Finished	Oct 15 10:11:47 AM UTC 24
Peak memory	318232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749099413 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3749099413
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.2150635340
Short name	T48
Test name
Test status
Simulation time	1440753300 ps
CPU time	77.04 seconds
Started	Oct 15 08:26:08 AM UTC 24
Finished	Oct 15 08:27:27 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150635340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2150635340
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1765569963
Short name	T400
Test name
Test status
Simulation time	1899826500 ps
CPU time	92.94 seconds
Started	Oct 15 08:24:29 AM UTC 24
Finished	Oct 15 08:26:04 AM UTC 24
Peak memory	275284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176 5569963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser r_address.1765569963
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3394552506
Short name	T403
Test name
Test status
Simulation time	3389172200 ps
CPU time	97.1 seconds
Started	Oct 15 08:24:28 AM UTC 24
Finished	Oct 15 08:26:07 AM UTC 24
Peak memory	285380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 94552506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se rr_counter.3394552506
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.3524415157
Short name	T235
Test name
Test status
Simulation time	41732900 ps
CPU time	236.38 seconds
Started	Oct 15 08:22:38 AM UTC 24
Finished	Oct 15 08:26:37 AM UTC 24
Peak memory	289364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524415157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3524415157
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.2125275459
Short name	T311
Test name
Test status
Simulation time	14117500 ps
CPU time	27.32 seconds
Started	Oct 15 08:22:42 AM UTC 24
Finished	Oct 15 08:23:10 AM UTC 24
Peak memory	270876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125275459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2125275459
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.1604132054
Short name	T149
Test name
Test status
Simulation time	3197592000 ps
CPU time	1110.29 seconds
Started	Oct 15 08:26:08 AM UTC 24
Finished	Oct 15 08:44:50 AM UTC 24
Peak memory	301480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604132054 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.1604132054
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3859409645
Short name	T308
Test name
Test status
Simulation time	26205200 ps
CPU time	29.57 seconds
Started	Oct 15 08:22:44 AM UTC 24
Finished	Oct 15 08:23:15 AM UTC 24
Peak memory	272728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859409645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3859409645
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.1029700891
Short name	T404
Test name
Test status
Simulation time	2332620300 ps
CPU time	178.96 seconds
Started	Oct 15 08:23:40 AM UTC 24
Finished	Oct 15 08:26:42 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1029700891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.1029700891
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.976658928
Short name	T598
Test name
Test status
Simulation time	122966900 ps
CPU time	28.8 seconds
Started	Oct 15 09:03:57 AM UTC 24
Finished	Oct 15 09:04:28 AM UTC 24
Peak memory	268812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976658928 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.976658928
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.374202383
Short name	T594
Test name
Test status
Simulation time	14625100 ps
CPU time	28.41 seconds
Started	Oct 15 09:03:28 AM UTC 24
Finished	Oct 15 09:03:58 AM UTC 24
Peak memory	284704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374202383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.374202383
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2523230712
Short name	T597
Test name
Test status
Simulation time	11852200 ps
CPU time	45.16 seconds
Started	Oct 15 09:03:28 AM UTC 24
Finished	Oct 15 09:04:15 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2523230712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ ctrl_disable.2523230712
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.4160156641
Short name	T609
Test name
Test status
Simulation time	10020729400 ps
CPU time	138.27 seconds
Started	Oct 15 09:03:48 AM UTC 24
Finished	Oct 15 09:06:09 AM UTC 24
Peak memory	285412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4160156641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.4160156641
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.3433090785
Short name	T684
Test name
Test status
Simulation time	160188534300 ps
CPU time	823.22 seconds
Started	Oct 15 09:01:31 AM UTC 24
Finished	Oct 15 09:15:25 AM UTC 24
Peak memory	274808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433090785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res et.3433090785
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3596557912
Short name	T586
Test name
Test status
Simulation time	2731648500 ps
CPU time	91.35 seconds
Started	Oct 15 09:01:29 AM UTC 24
Finished	Oct 15 09:03:02 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596557912 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.3596557912
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4281558607
Short name	T602
Test name
Test status
Simulation time	13658192800 ps
CPU time	141.62 seconds
Started	Oct 15 09:02:37 AM UTC 24
Finished	Oct 15 09:05:01 AM UTC 24
Peak memory	303668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4281558607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_intr_rd_slow_flash.4281558607
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.3336503779
Short name	T588
Test name
Test status
Simulation time	3703574900 ps
CPU time	105.38 seconds
Started	Oct 15 09:01:39 AM UTC 24
Finished	Oct 15 09:03:27 AM UTC 24
Peak memory	270800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336503779 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3336503779
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3729908277
Short name	T595
Test name
Test status
Simulation time	27422500 ps
CPU time	23.35 seconds
Started	Oct 15 09:03:33 AM UTC 24
Finished	Oct 15 09:03:58 AM UTC 24
Peak memory	270884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3729908277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_lcmgr_intg.3729908277
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.4143362461
Short name	T100
Test name
Test status
Simulation time	41163100 ps
CPU time	200.72 seconds
Started	Oct 15 09:01:37 AM UTC 24
Finished	Oct 15 09:05:01 AM UTC 24
Peak memory	274956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143362461 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.4143362461
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.4183965875
Short name	T221
Test name
Test status
Simulation time	2859102300 ps
CPU time	601.51 seconds
Started	Oct 15 09:01:28 AM UTC 24
Finished	Oct 15 09:11:37 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183965875 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.4183965875
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.2230092649
Short name	T590
Test name
Test status
Simulation time	68951600 ps
CPU time	23.54 seconds
Started	Oct 15 09:03:02 AM UTC 24
Finished	Oct 15 09:03:28 AM UTC 24
Peak memory	270792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230092649 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.2230092649
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.748834178
Short name	T651
Test name
Test status
Simulation time	139651400 ps
CPU time	613.67 seconds
Started	Oct 15 09:01:26 AM UTC 24
Finished	Oct 15 09:11:46 AM UTC 24
Peak memory	287192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748834178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.748834178
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.3045261187
Short name	T592
Test name
Test status
Simulation time	1265826600 ps
CPU time	122.9 seconds
Started	Oct 15 09:01:43 AM UTC 24
Finished	Oct 15 09:03:48 AM UTC 24
Peak memory	303720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3045261187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.3045261187
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3945794906
Short name	T593
Test name
Test status
Simulation time	49758100 ps
CPU time	51.41 seconds
Started	Oct 15 09:03:04 AM UTC 24
Finished	Oct 15 09:03:57 AM UTC 24
Peak memory	287428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945794906 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.3945794906
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.1794251067
Short name	T596
Test name
Test status
Simulation time	102045900 ps
CPU time	56.89 seconds
Started	Oct 15 09:03:08 AM UTC 24
Finished	Oct 15 09:04:06 AM UTC 24
Peak memory	287452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1794251067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_rw_evict_all_en.1794251067
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.2704863759
Short name	T599
Test name
Test status
Simulation time	62349300 ps
CPU time	189.56 seconds
Started	Oct 15 09:01:17 AM UTC 24
Finished	Oct 15 09:04:29 AM UTC 24
Peak memory	287320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704863759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2704863759
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.874793484
Short name	T608
Test name
Test status
Simulation time	11327411100 ps
CPU time	246.63 seconds
Started	Oct 15 09:01:40 AM UTC 24
Finished	Oct 15 09:05:51 AM UTC 24
Peak memory	275028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =874793484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.874793484
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.2769446545
Short name	T617
Test name
Test status
Simulation time	143780100 ps
CPU time	20.33 seconds
Started	Oct 15 09:06:24 AM UTC 24
Finished	Oct 15 09:06:46 AM UTC 24
Peak memory	275076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769446545 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.2769446545
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.3980417336
Short name	T610
Test name
Test status
Simulation time	47825300 ps
CPU time	26.85 seconds
Started	Oct 15 09:05:52 AM UTC 24
Finished	Oct 15 09:06:20 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980417336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3980417336
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.242298783
Short name	T623
Test name
Test status
Simulation time	10019832100 ps
CPU time	111.56 seconds
Started	Oct 15 09:06:21 AM UTC 24
Finished	Oct 15 09:08:15 AM UTC 24
Peak memory	316076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=242298783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.242298783
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.1594159660
Short name	T615
Test name
Test status
Simulation time	15479200 ps
CPU time	22.86 seconds
Started	Oct 15 09:06:15 AM UTC 24
Finished	Oct 15 09:06:40 AM UTC 24
Peak memory	269144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1594159660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1594159660
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1066829388
Short name	T188
Test name
Test status
Simulation time	80139037800 ps
CPU time	798.6 seconds
Started	Oct 15 09:04:16 AM UTC 24
Finished	Oct 15 09:17:44 AM UTC 24
Peak memory	274748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066829388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res et.1066829388
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.2113982757
Short name	T606
Test name
Test status
Simulation time	22249320900 ps
CPU time	98.2 seconds
Started	Oct 15 09:04:07 AM UTC 24
Finished	Oct 15 09:05:47 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113982757 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.2113982757
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1815754016
Short name	T349
Test name
Test status
Simulation time	6892142300 ps
CPU time	178.7 seconds
Started	Oct 15 09:05:02 AM UTC 24
Finished	Oct 15 09:08:03 AM UTC 24
Peak memory	293532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815754016 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.1815754016
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3781151591
Short name	T634
Test name
Test status
Simulation time	97875998600 ps
CPU time	258.96 seconds
Started	Oct 15 09:05:03 AM UTC 24
Finished	Oct 15 09:09:26 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3781151591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_intr_rd_slow_flash.3781151591
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1638044009
Short name	T603
Test name
Test status
Simulation time	7851665100 ps
CPU time	61.91 seconds
Started	Oct 15 09:04:30 AM UTC 24
Finished	Oct 15 09:05:34 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638044009 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1638044009
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.3807353625
Short name	T613
Test name
Test status
Simulation time	37385100 ps
CPU time	22.71 seconds
Started	Oct 15 09:06:10 AM UTC 24
Finished	Oct 15 09:06:34 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3807353625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_lcmgr_intg.3807353625
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3333241714
Short name	T616
Test name
Test status
Simulation time	7443925700 ps
CPU time	129.7 seconds
Started	Oct 15 09:04:28 AM UTC 24
Finished	Oct 15 09:06:40 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3333241714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.3333241714
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.1640369584
Short name	T99
Test name
Test status
Simulation time	161047500 ps
CPU time	210.6 seconds
Started	Oct 15 09:04:16 AM UTC 24
Finished	Oct 15 09:07:50 AM UTC 24
Peak memory	270776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640369584 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.1640369584
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.227981296
Short name	T667
Test name
Test status
Simulation time	1563963500 ps
CPU time	566.23 seconds
Started	Oct 15 09:04:06 AM UTC 24
Finished	Oct 15 09:13:39 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227981296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.227981296
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.3169333551
Short name	T605
Test name
Test status
Simulation time	37742700 ps
CPU time	23.46 seconds
Started	Oct 15 09:05:16 AM UTC 24
Finished	Oct 15 09:05:41 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169333551 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.3169333551
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1521396444
Short name	T621
Test name
Test status
Simulation time	88363500 ps
CPU time	221.03 seconds
Started	Oct 15 09:03:59 AM UTC 24
Finished	Oct 15 09:07:43 AM UTC 24
Peak memory	279124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521396444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1521396444
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.322610826
Short name	T614
Test name
Test status
Simulation time	238186400 ps
CPU time	54.69 seconds
Started	Oct 15 09:05:42 AM UTC 24
Finished	Oct 15 09:06:38 AM UTC 24
Peak memory	287444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322610826 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.322610826
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2012586202
Short name	T611
Test name
Test status
Simulation time	1048463600 ps
CPU time	101.36 seconds
Started	Oct 15 09:04:41 AM UTC 24
Finished	Oct 15 09:06:25 AM UTC 24
Peak memory	303764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2012586202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.2012586202
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.485537549
Short name	T668
Test name
Test status
Simulation time	3811812400 ps
CPU time	521.18 seconds
Started	Oct 15 09:04:59 AM UTC 24
Finished	Oct 15 09:13:47 AM UTC 24
Peak memory	332432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485537549 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.485537549
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.3118783048
Short name	T612
Test name
Test status
Simulation time	72676800 ps
CPU time	51.33 seconds
Started	Oct 15 09:05:35 AM UTC 24
Finished	Oct 15 09:06:28 AM UTC 24
Peak memory	287624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118783048 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.3118783048
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.296841417
Short name	T361
Test name
Test status
Simulation time	56047700 ps
CPU time	46.03 seconds
Started	Oct 15 09:05:35 AM UTC 24
Finished	Oct 15 09:06:23 AM UTC 24
Peak memory	287420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=296841417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ct rl_rw_evict_all_en.296841417
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2886886820
Short name	T418
Test name
Test status
Simulation time	4005448200 ps
CPU time	87.09 seconds
Started	Oct 15 09:05:50 AM UTC 24
Finished	Oct 15 09:07:19 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886886820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2886886820
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.1162086800
Short name	T607
Test name
Test status
Simulation time	33176100 ps
CPU time	108.01 seconds
Started	Oct 15 09:03:59 AM UTC 24
Finished	Oct 15 09:05:49 AM UTC 24
Peak memory	287192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162086800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1162086800
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.1499267879
Short name	T620
Test name
Test status
Simulation time	29227497500 ps
CPU time	166.23 seconds
Started	Oct 15 09:04:33 AM UTC 24
Finished	Oct 15 09:07:22 AM UTC 24
Peak memory	271072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1499267879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.1499267879
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.3001233437
Short name	T632
Test name
Test status
Simulation time	46668900 ps
CPU time	18.4 seconds
Started	Oct 15 09:08:41 AM UTC 24
Finished	Oct 15 09:09:01 AM UTC 24
Peak memory	268808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001233437 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.3001233437
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.3993911550
Short name	T628
Test name
Test status
Simulation time	44400100 ps
CPU time	20.97 seconds
Started	Oct 15 09:08:27 AM UTC 24
Finished	Oct 15 09:08:49 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993911550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.3993911550
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2613468936
Short name	T626
Test name
Test status
Simulation time	11474300 ps
CPU time	34.34 seconds
Started	Oct 15 09:08:04 AM UTC 24
Finished	Oct 15 09:08:40 AM UTC 24
Peak memory	285340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2613468936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ ctrl_disable.2613468936
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1176936423
Short name	T629
Test name
Test status
Simulation time	133542300 ps
CPU time	22.51 seconds
Started	Oct 15 09:08:30 AM UTC 24
Finished	Oct 15 09:08:54 AM UTC 24
Peak memory	270836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1176936423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1176936423
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.4014768219
Short name	T741
Test name
Test status
Simulation time	160195402100 ps
CPU time	818.37 seconds
Started	Oct 15 09:06:41 AM UTC 24
Finished	Oct 15 09:20:29 AM UTC 24
Peak memory	274872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014768219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res et.4014768219
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.145897600
Short name	T646
Test name
Test status
Simulation time	16353070500 ps
CPU time	290.33 seconds
Started	Oct 15 09:06:39 AM UTC 24
Finished	Oct 15 09:11:33 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145897600 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.145897600
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.2023241332
Short name	T641
Test name
Test status
Simulation time	6891227200 ps
CPU time	213.69 seconds
Started	Oct 15 09:07:23 AM UTC 24
Finished	Oct 15 09:11:00 AM UTC 24
Peak memory	301820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023241332 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.2023241332
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.3724060555
Short name	T624
Test name
Test status
Simulation time	871907200 ps
CPU time	91.84 seconds
Started	Oct 15 09:06:52 AM UTC 24
Finished	Oct 15 09:08:26 AM UTC 24
Peak memory	274476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724060555 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3724060555
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1413103993
Short name	T631
Test name
Test status
Simulation time	15366900 ps
CPU time	27.24 seconds
Started	Oct 15 09:08:29 AM UTC 24
Finished	Oct 15 09:08:58 AM UTC 24
Peak memory	271020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1413103993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_lcmgr_intg.1413103993
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.3251799684
Short name	T636
Test name
Test status
Simulation time	2692004600 ps
CPU time	197.49 seconds
Started	Oct 15 09:06:47 AM UTC 24
Finished	Oct 15 09:10:08 AM UTC 24
Peak memory	275080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3251799684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3251799684
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2802214016
Short name	T633
Test name
Test status
Simulation time	163168100 ps
CPU time	150.07 seconds
Started	Oct 15 09:06:41 AM UTC 24
Finished	Oct 15 09:09:14 AM UTC 24
Peak memory	270988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802214016 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.2802214016
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.1119823616
Short name	T671
Test name
Test status
Simulation time	144222300 ps
CPU time	480.15 seconds
Started	Oct 15 09:06:35 AM UTC 24
Finished	Oct 15 09:14:41 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119823616 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1119823616
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.1725338511
Short name	T649
Test name
Test status
Simulation time	9487366300 ps
CPU time	223.49 seconds
Started	Oct 15 09:07:51 AM UTC 24
Finished	Oct 15 09:11:38 AM UTC 24
Peak memory	272964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725338511 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.1725338511
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.362062414
Short name	T927
Test name
Test status
Simulation time	794856000 ps
CPU time	1465.39 seconds
Started	Oct 15 09:06:29 AM UTC 24
Finished	Oct 15 09:31:10 AM UTC 24
Peak memory	295384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362062414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.362062414
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2301117946
Short name	T630
Test name
Test status
Simulation time	100940100 ps
CPU time	50.4 seconds
Started	Oct 15 09:08:03 AM UTC 24
Finished	Oct 15 09:08:55 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301117946 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2301117946
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.1805384310
Short name	T635
Test name
Test status
Simulation time	632479400 ps
CPU time	149.28 seconds
Started	Oct 15 09:06:57 AM UTC 24
Finished	Oct 15 09:09:29 AM UTC 24
Peak memory	291536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1805384310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.1805384310
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.283269423
Short name	T681
Test name
Test status
Simulation time	35897495100 ps
CPU time	470.7 seconds
Started	Oct 15 09:07:20 AM UTC 24
Finished	Oct 15 09:15:16 AM UTC 24
Peak memory	320140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283269423 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.283269423
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2543963716
Short name	T419
Test name
Test status
Simulation time	1023619700 ps
CPU time	77.41 seconds
Started	Oct 15 09:08:17 AM UTC 24
Finished	Oct 15 09:09:36 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543963716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2543963716
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1452351296
Short name	T622
Test name
Test status
Simulation time	38208200 ps
CPU time	85.85 seconds
Started	Oct 15 09:06:25 AM UTC 24
Finished	Oct 15 09:07:53 AM UTC 24
Peak memory	276952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452351296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1452351296
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.2397139908
Short name	T637
Test name
Test status
Simulation time	2101369700 ps
CPU time	200.22 seconds
Started	Oct 15 09:06:52 AM UTC 24
Finished	Oct 15 09:10:16 AM UTC 24
Peak memory	272972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2397139908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.2397139908
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.1298025542
Short name	T650
Test name
Test status
Simulation time	63951900 ps
CPU time	19.12 seconds
Started	Oct 15 09:11:21 AM UTC 24
Finished	Oct 15 09:11:41 AM UTC 24
Peak memory	275140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298025542 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.1298025542
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1917584324
Short name	T111
Test name
Test status
Simulation time	14903400 ps
CPU time	18.95 seconds
Started	Oct 15 09:11:01 AM UTC 24
Finished	Oct 15 09:11:21 AM UTC 24
Peak memory	284828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917584324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1917584324
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.3934728033
Short name	T407
Test name
Test status
Simulation time	13076500 ps
CPU time	38.12 seconds
Started	Oct 15 09:10:49 AM UTC 24
Finished	Oct 15 09:11:29 AM UTC 24
Peak memory	285276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3934728033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ ctrl_disable.3934728033
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3019092470
Short name	T289
Test name
Test status
Simulation time	10019871500 ps
CPU time	170.96 seconds
Started	Oct 15 09:11:16 AM UTC 24
Finished	Oct 15 09:14:10 AM UTC 24
Peak memory	295448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3019092470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3019092470
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3377427255
Short name	T647
Test name
Test status
Simulation time	47361400 ps
CPU time	27.19 seconds
Started	Oct 15 09:11:07 AM UTC 24
Finished	Oct 15 09:11:35 AM UTC 24
Peak memory	274940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3377427255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3377427255
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1964517340
Short name	T816
Test name
Test status
Simulation time	160172219200 ps
CPU time	999.86 seconds
Started	Oct 15 09:08:59 AM UTC 24
Finished	Oct 15 09:25:51 AM UTC 24
Peak memory	274736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964517340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res et.1964517340
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.917642554
Short name	T654
Test name
Test status
Simulation time	30497201300 ps
CPU time	195.54 seconds
Started	Oct 15 09:08:57 AM UTC 24
Finished	Oct 15 09:12:16 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917642554 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.917642554
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.2002919105
Short name	T652
Test name
Test status
Simulation time	726203100 ps
CPU time	130.14 seconds
Started	Oct 15 09:09:37 AM UTC 24
Finished	Oct 15 09:11:50 AM UTC 24
Peak memory	293532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002919105 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.2002919105
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1090480706
Short name	T656
Test name
Test status
Simulation time	5559599000 ps
CPU time	149.49 seconds
Started	Oct 15 09:10:10 AM UTC 24
Finished	Oct 15 09:12:42 AM UTC 24
Peak memory	303796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1090480706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_intr_rd_slow_flash.1090480706
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3600628629
Short name	T638
Test name
Test status
Simulation time	5910108400 ps
CPU time	74.82 seconds
Started	Oct 15 09:09:14 AM UTC 24
Finished	Oct 15 09:10:30 AM UTC 24
Peak memory	270796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600628629 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3600628629
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1441014275
Short name	T645
Test name
Test status
Simulation time	15834900 ps
CPU time	25.63 seconds
Started	Oct 15 09:11:03 AM UTC 24
Finished	Oct 15 09:11:30 AM UTC 24
Peak memory	274988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1441014275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_lcmgr_intg.1441014275
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.2025075283
Short name	T146
Test name
Test status
Simulation time	53682111200 ps
CPU time	870.47 seconds
Started	Oct 15 09:09:02 AM UTC 24
Finished	Oct 15 09:23:42 AM UTC 24
Peak memory	283144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2025075283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.2025075283
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.489310620
Short name	T183
Test name
Test status
Simulation time	134428700 ps
CPU time	153.45 seconds
Started	Oct 15 09:09:02 AM UTC 24
Finished	Oct 15 09:11:38 AM UTC 24
Peak memory	274928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489310620 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.489310620
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.416162126
Short name	T678
Test name
Test status
Simulation time	1382175200 ps
CPU time	370.22 seconds
Started	Oct 15 09:08:55 AM UTC 24
Finished	Oct 15 09:15:10 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416162126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.416162126
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.4021071684
Short name	T639
Test name
Test status
Simulation time	38393900 ps
CPU time	26.93 seconds
Started	Oct 15 09:10:14 AM UTC 24
Finished	Oct 15 09:10:42 AM UTC 24
Peak memory	274952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021071684 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.4021071684
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.4261630088
Short name	T653
Test name
Test status
Simulation time	25313900 ps
CPU time	197.27 seconds
Started	Oct 15 09:08:50 AM UTC 24
Finished	Oct 15 09:12:10 AM UTC 24
Peak memory	278956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261630088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.4261630088
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.3229760603
Short name	T644
Test name
Test status
Simulation time	274508100 ps
CPU time	35.72 seconds
Started	Oct 15 09:10:43 AM UTC 24
Finished	Oct 15 09:11:21 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229760603 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.3229760603
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1495749346
Short name	T643
Test name
Test status
Simulation time	2164165000 ps
CPU time	106.54 seconds
Started	Oct 15 09:09:27 AM UTC 24
Finished	Oct 15 09:11:16 AM UTC 24
Peak memory	303720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1495749346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1495749346
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2029576564
Short name	T693
Test name
Test status
Simulation time	16479050200 ps
CPU time	406.64 seconds
Started	Oct 15 09:09:29 AM UTC 24
Finished	Oct 15 09:16:21 AM UTC 24
Peak memory	320176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029576564 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.2029576564
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.876273077
Short name	T640
Test name
Test status
Simulation time	68942800 ps
CPU time	38.81 seconds
Started	Oct 15 09:10:17 AM UTC 24
Finished	Oct 15 09:10:57 AM UTC 24
Peak memory	287632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876273077 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.876273077
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3041466659
Short name	T648
Test name
Test status
Simulation time	83055900 ps
CPU time	165.64 seconds
Started	Oct 15 09:08:50 AM UTC 24
Finished	Oct 15 09:11:38 AM UTC 24
Peak memory	287076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041466659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3041466659
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.4006887203
Short name	T669
Test name
Test status
Simulation time	2545593600 ps
CPU time	268.51 seconds
Started	Oct 15 09:09:15 AM UTC 24
Finished	Oct 15 09:13:47 AM UTC 24
Peak memory	275040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4006887203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.4006887203
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.386889911
Short name	T666
Test name
Test status
Simulation time	34867900 ps
CPU time	19.63 seconds
Started	Oct 15 09:13:18 AM UTC 24
Finished	Oct 15 09:13:39 AM UTC 24
Peak memory	268996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386889911 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.386889911
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.2746920426
Short name	T112
Test name
Test status
Simulation time	15452600 ps
CPU time	22.25 seconds
Started	Oct 15 09:13:00 AM UTC 24
Finished	Oct 15 09:13:24 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746920426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2746920426
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.427942054
Short name	T673
Test name
Test status
Simulation time	10039450300 ps
CPU time	86.8 seconds
Started	Oct 15 09:13:15 AM UTC 24
Finished	Oct 15 09:14:44 AM UTC 24
Peak memory	287400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=427942054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.427942054
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.1094083501
Short name	T665
Test name
Test status
Simulation time	45100300 ps
CPU time	20.77 seconds
Started	Oct 15 09:13:14 AM UTC 24
Finished	Oct 15 09:13:36 AM UTC 24
Peak memory	275152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1094083501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1094083501
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.2726122674
Short name	T871
Test name
Test status
Simulation time	50130776900 ps
CPU time	1021.35 seconds
Started	Oct 15 09:11:35 AM UTC 24
Finished	Oct 15 09:28:48 AM UTC 24
Peak memory	274928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726122674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res et.2726122674
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.1057600137
Short name	T670
Test name
Test status
Simulation time	67850935400 ps
CPU time	182.89 seconds
Started	Oct 15 09:11:30 AM UTC 24
Finished	Oct 15 09:14:36 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057600137 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.1057600137
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1387904477
Short name	T675
Test name
Test status
Simulation time	1704544500 ps
CPU time	181.09 seconds
Started	Oct 15 09:11:47 AM UTC 24
Finished	Oct 15 09:14:51 AM UTC 24
Peak memory	301812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387904477 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.1387904477
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1622018059
Short name	T691
Test name
Test status
Simulation time	11716191300 ps
CPU time	248.25 seconds
Started	Oct 15 09:11:50 AM UTC 24
Finished	Oct 15 09:16:03 AM UTC 24
Peak memory	301640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1622018059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_intr_rd_slow_flash.1622018059
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.3984572755
Short name	T660
Test name
Test status
Simulation time	1746195900 ps
CPU time	105.94 seconds
Started	Oct 15 09:11:39 AM UTC 24
Finished	Oct 15 09:13:27 AM UTC 24
Peak memory	270992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984572755 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3984572755
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1173045761
Short name	T664
Test name
Test status
Simulation time	38865400 ps
CPU time	18.65 seconds
Started	Oct 15 09:13:14 AM UTC 24
Finished	Oct 15 09:13:34 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1173045761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_lcmgr_intg.1173045761
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.3658107349
Short name	T674
Test name
Test status
Simulation time	4874496700 ps
CPU time	189.52 seconds
Started	Oct 15 09:11:38 AM UTC 24
Finished	Oct 15 09:14:50 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3658107349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.3658107349
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.644162148
Short name	T763
Test name
Test status
Simulation time	5510485600 ps
CPU time	631.14 seconds
Started	Oct 15 09:11:30 AM UTC 24
Finished	Oct 15 09:22:09 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644162148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.644162148
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.2036117306
Short name	T655
Test name
Test status
Simulation time	40835400 ps
CPU time	17.51 seconds
Started	Oct 15 09:12:10 AM UTC 24
Finished	Oct 15 09:12:29 AM UTC 24
Peak memory	275016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036117306 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.2036117306
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.4133584438
Short name	T996
Test name
Test status
Simulation time	146226400 ps
CPU time	1334.96 seconds
Started	Oct 15 09:11:27 AM UTC 24
Finished	Oct 15 09:33:56 AM UTC 24
Peak memory	295380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133584438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.4133584438
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.1337929866
Short name	T663
Test name
Test status
Simulation time	587789900 ps
CPU time	110.22 seconds
Started	Oct 15 09:11:39 AM UTC 24
Finished	Oct 15 09:13:31 AM UTC 24
Peak memory	301732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1337929866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.1337929866
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.3257306
Short name	T658
Test name
Test status
Simulation time	66257600 ps
CPU time	47.14 seconds
Started	Oct 15 09:12:17 AM UTC 24
Finished	Oct 15 09:13:05 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257306 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.3257306
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.3417983107
Short name	T659
Test name
Test status
Simulation time	41473700 ps
CPU time	41.44 seconds
Started	Oct 15 09:12:28 AM UTC 24
Finished	Oct 15 09:13:11 AM UTC 24
Peak memory	287460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3417983107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c trl_rw_evict_all_en.3417983107
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.2919356729
Short name	T672
Test name
Test status
Simulation time	1679103700 ps
CPU time	104.87 seconds
Started	Oct 15 09:12:56 AM UTC 24
Finished	Oct 15 09:14:43 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919356729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.2919356729
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.494083574
Short name	T661
Test name
Test status
Simulation time	30959800 ps
CPU time	124.45 seconds
Started	Oct 15 09:11:22 AM UTC 24
Finished	Oct 15 09:13:29 AM UTC 24
Peak memory	289240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494083574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.494083574
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.2655563871
Short name	T690
Test name
Test status
Simulation time	4734645200 ps
CPU time	245.78 seconds
Started	Oct 15 09:11:39 AM UTC 24
Finished	Oct 15 09:15:48 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2655563871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.2655563871
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.570917152
Short name	T686
Test name
Test status
Simulation time	126511100 ps
CPU time	24.09 seconds
Started	Oct 15 09:15:00 AM UTC 24
Finished	Oct 15 09:15:26 AM UTC 24
Peak memory	268812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570917152 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.570917152
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.1899753669
Short name	T682
Test name
Test status
Simulation time	139631500 ps
CPU time	29.18 seconds
Started	Oct 15 09:14:47 AM UTC 24
Finished	Oct 15 09:15:18 AM UTC 24
Peak memory	294944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899753669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1899753669
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.3220864505
Short name	T680
Test name
Test status
Simulation time	37006000 ps
CPU time	26.73 seconds
Started	Oct 15 09:14:44 AM UTC 24
Finished	Oct 15 09:15:12 AM UTC 24
Peak memory	285252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3220864505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ ctrl_disable.3220864505
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3004022405
Short name	T701
Test name
Test status
Simulation time	10019018400 ps
CPU time	112.46 seconds
Started	Oct 15 09:15:00 AM UTC 24
Finished	Oct 15 09:16:55 AM UTC 24
Peak memory	295656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3004022405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3004022405
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.552493937
Short name	T679
Test name
Test status
Simulation time	15486200 ps
CPU time	17.5 seconds
Started	Oct 15 09:14:52 AM UTC 24
Finished	Oct 15 09:15:11 AM UTC 24
Peak memory	269140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=552493937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.flash_ctrl_hw_read_seed_err.552493937
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.2844732020
Short name	T172
Test name
Test status
Simulation time	40125030600 ps
CPU time	795.18 seconds
Started	Oct 15 09:13:31 AM UTC 24
Finished	Oct 15 09:26:56 AM UTC 24
Peak memory	274808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844732020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res et.2844732020
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.3280897964
Short name	T692
Test name
Test status
Simulation time	8411220800 ps
CPU time	156.77 seconds
Started	Oct 15 09:13:30 AM UTC 24
Finished	Oct 15 09:16:10 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280897964 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.3280897964
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.914769334
Short name	T351
Test name
Test status
Simulation time	2010265900 ps
CPU time	203.11 seconds
Started	Oct 15 09:13:48 AM UTC 24
Finished	Oct 15 09:17:15 AM UTC 24
Peak memory	301688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914769334 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.914769334
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2644996943
Short name	T722
Test name
Test status
Simulation time	12619943300 ps
CPU time	266.95 seconds
Started	Oct 15 09:14:11 AM UTC 24
Finished	Oct 15 09:18:41 AM UTC 24
Peak memory	301772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2644996943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_intr_rd_slow_flash.2644996943
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.2698196994
Short name	T685
Test name
Test status
Simulation time	3626068700 ps
CPU time	105.78 seconds
Started	Oct 15 09:13:37 AM UTC 24
Finished	Oct 15 09:15:25 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698196994 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2698196994
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.31749759
Short name	T143
Test name
Test status
Simulation time	14635464400 ps
CPU time	351.58 seconds
Started	Oct 15 09:13:35 AM UTC 24
Finished	Oct 15 09:19:31 AM UTC 24
Peak memory	283172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=31749759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 15.flash_ctrl_mp_regions.31749759
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.3397678689
Short name	T178
Test name
Test status
Simulation time	311413500 ps
CPU time	232.03 seconds
Started	Oct 15 09:13:32 AM UTC 24
Finished	Oct 15 09:17:28 AM UTC 24
Peak memory	271244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397678689 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.3397678689
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.651732642
Short name	T698
Test name
Test status
Simulation time	40963700 ps
CPU time	186.98 seconds
Started	Oct 15 09:13:28 AM UTC 24
Finished	Oct 15 09:16:38 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651732642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.651732642
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1633399096
Short name	T676
Test name
Test status
Simulation time	61869000 ps
CPU time	24.32 seconds
Started	Oct 15 09:14:34 AM UTC 24
Finished	Oct 15 09:14:59 AM UTC 24
Peak memory	270864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633399096 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.1633399096
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.770788606
Short name	T874
Test name
Test status
Simulation time	289901400 ps
CPU time	920.47 seconds
Started	Oct 15 09:13:27 AM UTC 24
Finished	Oct 15 09:28:58 AM UTC 24
Peak memory	293336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770788606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.770788606
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.696249614
Short name	T688
Test name
Test status
Simulation time	1272199700 ps
CPU time	53.41 seconds
Started	Oct 15 09:14:42 AM UTC 24
Finished	Oct 15 09:15:37 AM UTC 24
Peak memory	285424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696249614 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.696249614
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.302084407
Short name	T689
Test name
Test status
Simulation time	2281977100 ps
CPU time	117.18 seconds
Started	Oct 15 09:13:40 AM UTC 24
Finished	Oct 15 09:15:40 AM UTC 24
Peak memory	307868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=302084407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.302084407
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1515533032
Short name	T759
Test name
Test status
Simulation time	62145317800 ps
CPU time	485.14 seconds
Started	Oct 15 09:13:47 AM UTC 24
Finished	Oct 15 09:21:59 AM UTC 24
Peak memory	320208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515533032 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.1515533032
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3944415689
Short name	T687
Test name
Test status
Simulation time	29135400 ps
CPU time	49.45 seconds
Started	Oct 15 09:14:39 AM UTC 24
Finished	Oct 15 09:15:30 AM UTC 24
Peak memory	287564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944415689 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.3944415689
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.2633955464
Short name	T683
Test name
Test status
Simulation time	60930400 ps
CPU time	40.33 seconds
Started	Oct 15 09:14:40 AM UTC 24
Finished	Oct 15 09:15:22 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2633955464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_rw_evict_all_en.2633955464
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.3347293453
Short name	T695
Test name
Test status
Simulation time	2376069700 ps
CPU time	98.82 seconds
Started	Oct 15 09:14:45 AM UTC 24
Finished	Oct 15 09:16:27 AM UTC 24
Peak memory	272936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347293453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3347293453
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.4179209899
Short name	T694
Test name
Test status
Simulation time	261076300 ps
CPU time	174.34 seconds
Started	Oct 15 09:13:24 AM UTC 24
Finished	Oct 15 09:16:22 AM UTC 24
Peak memory	287188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179209899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.4179209899
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.3491721711
Short name	T704
Test name
Test status
Simulation time	42514040100 ps
CPU time	208.96 seconds
Started	Oct 15 09:13:40 AM UTC 24
Finished	Oct 15 09:17:12 AM UTC 24
Peak memory	270944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3491721711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.3491721711
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.1247732891
Short name	T705
Test name
Test status
Simulation time	31146700 ps
CPU time	26.08 seconds
Started	Oct 15 09:16:50 AM UTC 24
Finished	Oct 15 09:17:17 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247732891 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.1247732891
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.24668702
Short name	T700
Test name
Test status
Simulation time	23340900 ps
CPU time	20.94 seconds
Started	Oct 15 09:16:27 AM UTC 24
Finished	Oct 15 09:16:49 AM UTC 24
Peak memory	295068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24668702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.24668702
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2527216020
Short name	T410
Test name
Test status
Simulation time	10834000 ps
CPU time	43.19 seconds
Started	Oct 15 09:16:22 AM UTC 24
Finished	Oct 15 09:17:07 AM UTC 24
Peak memory	285468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2527216020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ ctrl_disable.2527216020
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2332041562
Short name	T712
Test name
Test status
Simulation time	10019780000 ps
CPU time	81.77 seconds
Started	Oct 15 09:16:38 AM UTC 24
Finished	Oct 15 09:18:02 AM UTC 24
Peak memory	289508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2332041562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2332041562
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.2836751876
Short name	T702
Test name
Test status
Simulation time	30119800 ps
CPU time	21.16 seconds
Started	Oct 15 09:16:36 AM UTC 24
Finished	Oct 15 09:16:59 AM UTC 24
Peak memory	271076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2836751876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2836751876
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2267752373
Short name	T869
Test name
Test status
Simulation time	240209030200 ps
CPU time	793.03 seconds
Started	Oct 15 09:15:18 AM UTC 24
Finished	Oct 15 09:28:40 AM UTC 24
Peak memory	274868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267752373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res et.2267752373
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.2980897166
Short name	T706
Test name
Test status
Simulation time	3341160700 ps
CPU time	128 seconds
Started	Oct 15 09:15:14 AM UTC 24
Finished	Oct 15 09:17:24 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980897166 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.2980897166
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.1332273481
Short name	T707
Test name
Test status
Simulation time	1040889600 ps
CPU time	113.05 seconds
Started	Oct 15 09:15:30 AM UTC 24
Finished	Oct 15 09:17:26 AM UTC 24
Peak memory	305852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332273481 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.1332273481
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2810288290
Short name	T727
Test name
Test status
Simulation time	16140633800 ps
CPU time	190.72 seconds
Started	Oct 15 09:15:38 AM UTC 24
Finished	Oct 15 09:18:52 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2810288290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_intr_rd_slow_flash.2810288290
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.77861676
Short name	T699
Test name
Test status
Simulation time	3491308200 ps
CPU time	79.21 seconds
Started	Oct 15 09:15:28 AM UTC 24
Finished	Oct 15 09:16:49 AM UTC 24
Peak memory	274892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77861676 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.77861676
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.1130146171
Short name	T703
Test name
Test status
Simulation time	15854900 ps
CPU time	28.56 seconds
Started	Oct 15 09:16:36 AM UTC 24
Finished	Oct 15 09:17:06 AM UTC 24
Peak memory	272912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1130146171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_lcmgr_intg.1130146171
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.3101803693
Short name	T144
Test name
Test status
Simulation time	16570909100 ps
CPU time	416.03 seconds
Started	Oct 15 09:15:27 AM UTC 24
Finished	Oct 15 09:22:28 AM UTC 24
Peak memory	283172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3101803693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.3101803693
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.199965351
Short name	T184
Test name
Test status
Simulation time	82326300 ps
CPU time	208.82 seconds
Started	Oct 15 09:15:27 AM UTC 24
Finished	Oct 15 09:18:59 AM UTC 24
Peak memory	270832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199965351 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.199965351
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.1715004829
Short name	T717
Test name
Test status
Simulation time	35605700 ps
CPU time	191.77 seconds
Started	Oct 15 09:15:11 AM UTC 24
Finished	Oct 15 09:18:26 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715004829 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.1715004829
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.1101388006
Short name	T716
Test name
Test status
Simulation time	4354984900 ps
CPU time	158.33 seconds
Started	Oct 15 09:15:40 AM UTC 24
Finished	Oct 15 09:18:21 AM UTC 24
Peak memory	270924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101388006 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.1101388006
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.2013555471
Short name	T147
Test name
Test status
Simulation time	1497564600 ps
CPU time	585.47 seconds
Started	Oct 15 09:15:11 AM UTC 24
Finished	Oct 15 09:25:04 AM UTC 24
Peak memory	293460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013555471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2013555471
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.1755816124
Short name	T325
Test name
Test status
Simulation time	308437800 ps
CPU time	47.16 seconds
Started	Oct 15 09:16:11 AM UTC 24
Finished	Oct 15 09:17:00 AM UTC 24
Peak memory	287564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755816124 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.1755816124
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3273399904
Short name	T709
Test name
Test status
Simulation time	653915700 ps
CPU time	128.85 seconds
Started	Oct 15 09:15:28 AM UTC 24
Finished	Oct 15 09:17:39 AM UTC 24
Peak memory	291520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3273399904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.3273399904
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.3944030627
Short name	T793
Test name
Test status
Simulation time	3853758400 ps
CPU time	540.8 seconds
Started	Oct 15 09:15:28 AM UTC 24
Finished	Oct 15 09:24:36 AM UTC 24
Peak memory	324288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944030627 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.3944030627
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.2677935020
Short name	T696
Test name
Test status
Simulation time	108086200 ps
CPU time	44.09 seconds
Started	Oct 15 09:15:50 AM UTC 24
Finished	Oct 15 09:16:35 AM UTC 24
Peak memory	285544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677935020 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.2677935020
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.3653677690
Short name	T363
Test name
Test status
Simulation time	34668200 ps
CPU time	58 seconds
Started	Oct 15 09:16:04 AM UTC 24
Finished	Oct 15 09:17:03 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3653677690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c trl_rw_evict_all_en.3653677690
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3245516009
Short name	T710
Test name
Test status
Simulation time	619974900 ps
CPU time	74.57 seconds
Started	Oct 15 09:16:23 AM UTC 24
Finished	Oct 15 09:17:40 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245516009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3245516009
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.1249793238
Short name	T697
Test name
Test status
Simulation time	39919600 ps
CPU time	84.34 seconds
Started	Oct 15 09:15:09 AM UTC 24
Finished	Oct 15 09:16:36 AM UTC 24
Peak memory	285144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249793238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1249793238
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.941481379
Short name	T725
Test name
Test status
Simulation time	5186387000 ps
CPU time	199.38 seconds
Started	Oct 15 09:15:28 AM UTC 24
Finished	Oct 15 09:18:51 AM UTC 24
Peak memory	270932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =941481379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.941481379
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.3801233038
Short name	T720
Test name
Test status
Simulation time	41498500 ps
CPU time	15.97 seconds
Started	Oct 15 09:18:17 AM UTC 24
Finished	Oct 15 09:18:34 AM UTC 24
Peak memory	268800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801233038 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.3801233038
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2250361100
Short name	T713
Test name
Test status
Simulation time	35975000 ps
CPU time	17.61 seconds
Started	Oct 15 09:17:56 AM UTC 24
Finished	Oct 15 09:18:15 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250361100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2250361100
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1926819046
Short name	T715
Test name
Test status
Simulation time	11537400 ps
CPU time	35.9 seconds
Started	Oct 15 09:17:41 AM UTC 24
Finished	Oct 15 09:18:18 AM UTC 24
Peak memory	285252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1926819046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ ctrl_disable.1926819046
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1144008026
Short name	T743
Test name
Test status
Simulation time	10012310600 ps
CPU time	139.33 seconds
Started	Oct 15 09:18:15 AM UTC 24
Finished	Oct 15 09:20:37 AM UTC 24
Peak memory	393764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1144008026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1144008026
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.2957244543
Short name	T719
Test name
Test status
Simulation time	25778600 ps
CPU time	26 seconds
Started	Oct 15 09:18:03 AM UTC 24
Finished	Oct 15 09:18:30 AM UTC 24
Peak memory	274964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2957244543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.2957244543
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.362071943
Short name	T922
Test name
Test status
Simulation time	40123763900 ps
CPU time	825.15 seconds
Started	Oct 15 09:17:04 AM UTC 24
Finished	Oct 15 09:30:58 AM UTC 24
Peak memory	274812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362071943 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_reset.362071943
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.3141256670
Short name	T730
Test name
Test status
Simulation time	3866595500 ps
CPU time	130.61 seconds
Started	Oct 15 09:17:00 AM UTC 24
Finished	Oct 15 09:19:13 AM UTC 24
Peak memory	272996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141256670 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.3141256670
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.3706648314
Short name	T749
Test name
Test status
Simulation time	8175502100 ps
CPU time	231.19 seconds
Started	Oct 15 09:17:27 AM UTC 24
Finished	Oct 15 09:21:22 AM UTC 24
Peak memory	301692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706648314 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.3706648314
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1853876505
Short name	T756
Test name
Test status
Simulation time	12864808900 ps
CPU time	262.44 seconds
Started	Oct 15 09:17:29 AM UTC 24
Finished	Oct 15 09:21:55 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1853876505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_intr_rd_slow_flash.1853876505
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.427540138
Short name	T726
Test name
Test status
Simulation time	3968456300 ps
CPU time	95.47 seconds
Started	Oct 15 09:17:13 AM UTC 24
Finished	Oct 15 09:18:51 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427540138 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.427540138
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.2456147765
Short name	T718
Test name
Test status
Simulation time	19869000 ps
CPU time	27.9 seconds
Started	Oct 15 09:18:00 AM UTC 24
Finished	Oct 15 09:18:29 AM UTC 24
Peak memory	270868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2456147765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_lcmgr_intg.2456147765
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.3150645111
Short name	T978
Test name
Test status
Simulation time	34440445600 ps
CPU time	967.94 seconds
Started	Oct 15 09:17:08 AM UTC 24
Finished	Oct 15 09:33:28 AM UTC 24
Peak memory	283152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3150645111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.3150645111
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.2965342883
Short name	T194
Test name
Test status
Simulation time	67877300 ps
CPU time	172.06 seconds
Started	Oct 15 09:17:07 AM UTC 24
Finished	Oct 15 09:20:02 AM UTC 24
Peak memory	274956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965342883 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.2965342883
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.447281366
Short name	T777
Test name
Test status
Simulation time	329694600 ps
CPU time	396.22 seconds
Started	Oct 15 09:17:00 AM UTC 24
Finished	Oct 15 09:23:41 AM UTC 24
Peak memory	274764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447281366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.447281366
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.2140445880
Short name	T711
Test name
Test status
Simulation time	81431600 ps
CPU time	24.65 seconds
Started	Oct 15 09:17:29 AM UTC 24
Finished	Oct 15 09:17:55 AM UTC 24
Peak memory	270812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140445880 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.2140445880
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.758354670
Short name	T775
Test name
Test status
Simulation time	76961800 ps
CPU time	381.24 seconds
Started	Oct 15 09:16:56 AM UTC 24
Finished	Oct 15 09:23:22 AM UTC 24
Peak memory	289240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758354670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.758354670
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.2459701799
Short name	T724
Test name
Test status
Simulation time	293703900 ps
CPU time	65.19 seconds
Started	Oct 15 09:17:41 AM UTC 24
Finished	Oct 15 09:18:48 AM UTC 24
Peak memory	287624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459701799 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.2459701799
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.844917563
Short name	T794
Test name
Test status
Simulation time	7256884600 ps
CPU time	434.05 seconds
Started	Oct 15 09:17:25 AM UTC 24
Finished	Oct 15 09:24:44 AM UTC 24
Peak memory	320204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844917563 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.844917563
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.3283223608
Short name	T714
Test name
Test status
Simulation time	48267000 ps
CPU time	44.99 seconds
Started	Oct 15 09:17:30 AM UTC 24
Finished	Oct 15 09:18:17 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283223608 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.3283223608
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.2924258908
Short name	T729
Test name
Test status
Simulation time	3549939000 ps
CPU time	84.94 seconds
Started	Oct 15 09:17:45 AM UTC 24
Finished	Oct 15 09:19:12 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924258908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2924258908
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.1436012965
Short name	T723
Test name
Test status
Simulation time	33203800 ps
CPU time	111.21 seconds
Started	Oct 15 09:16:50 AM UTC 24
Finished	Oct 15 09:18:43 AM UTC 24
Peak memory	287184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436012965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1436012965
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.2929009473
Short name	T732
Test name
Test status
Simulation time	1869547600 ps
CPU time	136.29 seconds
Started	Oct 15 09:17:16 AM UTC 24
Finished	Oct 15 09:19:34 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2929009473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.2929009473
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1325440023
Short name	T735
Test name
Test status
Simulation time	103982000 ps
CPU time	16.43 seconds
Started	Oct 15 09:19:44 AM UTC 24
Finished	Oct 15 09:20:01 AM UTC 24
Peak memory	268868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325440023 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.1325440023
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.3307366976
Short name	T734
Test name
Test status
Simulation time	58081700 ps
CPU time	26.01 seconds
Started	Oct 15 09:19:33 AM UTC 24
Finished	Oct 15 09:20:01 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307366976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3307366976
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.4240394366
Short name	T413
Test name
Test status
Simulation time	13408000 ps
CPU time	29.4 seconds
Started	Oct 15 09:19:12 AM UTC 24
Finished	Oct 15 09:19:43 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4240394366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ ctrl_disable.4240394366
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1211914143
Short name	T744
Test name
Test status
Simulation time	10031572000 ps
CPU time	58.67 seconds
Started	Oct 15 09:19:42 AM UTC 24
Finished	Oct 15 09:20:42 AM UTC 24
Peak memory	291360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1211914143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1211914143
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.1721005494
Short name	T737
Test name
Test status
Simulation time	47539300 ps
CPU time	28.52 seconds
Started	Oct 15 09:19:35 AM UTC 24
Finished	Oct 15 09:20:05 AM UTC 24
Peak memory	268948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1721005494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1721005494
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.3783099639
Short name	T1013
Test name
Test status
Simulation time	40124301800 ps
CPU time	954.4 seconds
Started	Oct 15 09:18:27 AM UTC 24
Finished	Oct 15 09:34:33 AM UTC 24
Peak memory	274800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783099639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res et.3783099639
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.3701026762
Short name	T739
Test name
Test status
Simulation time	2873663300 ps
CPU time	121.16 seconds
Started	Oct 15 09:18:23 AM UTC 24
Finished	Oct 15 09:20:26 AM UTC 24
Peak memory	272804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701026762 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.3701026762
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.1520292164
Short name	T776
Test name
Test status
Simulation time	1937834400 ps
CPU time	271.51 seconds
Started	Oct 15 09:18:48 AM UTC 24
Finished	Oct 15 09:23:24 AM UTC 24
Peak memory	293496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520292164 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.1520292164
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.908107668
Short name	T751
Test name
Test status
Simulation time	12234951500 ps
CPU time	164.08 seconds
Started	Oct 15 09:18:52 AM UTC 24
Finished	Oct 15 09:21:39 AM UTC 24
Peak memory	303796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=908107668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 18.flash_ctrl_intr_rd_slow_flash.908107668
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.2897471715
Short name	T738
Test name
Test status
Simulation time	862072600 ps
CPU time	90.12 seconds
Started	Oct 15 09:18:35 AM UTC 24
Finished	Oct 15 09:20:08 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897471715 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2897471715
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.1440712024
Short name	T736
Test name
Test status
Simulation time	25828100 ps
CPU time	27.18 seconds
Started	Oct 15 09:19:33 AM UTC 24
Finished	Oct 15 09:20:02 AM UTC 24
Peak memory	274956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1440712024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_lcmgr_intg.1440712024
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.1385014984
Short name	T145
Test name
Test status
Simulation time	9547494000 ps
CPU time	295.65 seconds
Started	Oct 15 09:18:31 AM UTC 24
Finished	Oct 15 09:23:31 AM UTC 24
Peak memory	283144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1385014984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.1385014984
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.48587934
Short name	T746
Test name
Test status
Simulation time	66772800 ps
CPU time	151.2 seconds
Started	Oct 15 09:18:30 AM UTC 24
Finished	Oct 15 09:21:04 AM UTC 24
Peak memory	271028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48587934 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.48587934
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.1524712196
Short name	T837
Test name
Test status
Simulation time	1376280000 ps
CPU time	521.22 seconds
Started	Oct 15 09:18:23 AM UTC 24
Finished	Oct 15 09:27:10 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524712196 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1524712196
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.3527281878
Short name	T728
Test name
Test status
Simulation time	20423200 ps
CPU time	17.28 seconds
Started	Oct 15 09:18:52 AM UTC 24
Finished	Oct 15 09:19:10 AM UTC 24
Peak memory	270800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527281878 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.3527281878
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.2804596132
Short name	T867
Test name
Test status
Simulation time	737178800 ps
CPU time	598.75 seconds
Started	Oct 15 09:18:21 AM UTC 24
Finished	Oct 15 09:28:26 AM UTC 24
Peak memory	291284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804596132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.2804596132
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.539813022
Short name	T321
Test name
Test status
Simulation time	217619300 ps
CPU time	55.41 seconds
Started	Oct 15 09:19:11 AM UTC 24
Finished	Oct 15 09:20:08 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539813022 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.539813022
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.4212625609
Short name	T740
Test name
Test status
Simulation time	2011870800 ps
CPU time	98.41 seconds
Started	Oct 15 09:18:48 AM UTC 24
Finished	Oct 15 09:20:29 AM UTC 24
Peak memory	301696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4212625609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.4212625609
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3076719118
Short name	T817
Test name
Test status
Simulation time	3574074000 ps
CPU time	418.46 seconds
Started	Oct 15 09:18:48 AM UTC 24
Finished	Oct 15 09:25:52 AM UTC 24
Peak memory	320152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076719118 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.3076719118
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.2876914990
Short name	T731
Test name
Test status
Simulation time	30633800 ps
CPU time	37.28 seconds
Started	Oct 15 09:18:53 AM UTC 24
Finished	Oct 15 09:19:32 AM UTC 24
Peak memory	287560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876914990 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.2876914990
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.1000552402
Short name	T733
Test name
Test status
Simulation time	43939800 ps
CPU time	43.36 seconds
Started	Oct 15 09:19:00 AM UTC 24
Finished	Oct 15 09:19:45 AM UTC 24
Peak memory	287452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1000552402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c trl_rw_evict_all_en.1000552402
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.594294319
Short name	T745
Test name
Test status
Simulation time	4516052600 ps
CPU time	87.99 seconds
Started	Oct 15 09:19:15 AM UTC 24
Finished	Oct 15 09:20:45 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594294319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.594294319
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.223779921
Short name	T742
Test name
Test status
Simulation time	101566600 ps
CPU time	129.52 seconds
Started	Oct 15 09:18:18 AM UTC 24
Finished	Oct 15 09:20:31 AM UTC 24
Peak memory	287184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223779921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.223779921
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.48940642
Short name	T762
Test name
Test status
Simulation time	19304279800 ps
CPU time	197.61 seconds
Started	Oct 15 09:18:48 AM UTC 24
Finished	Oct 15 09:22:09 AM UTC 24
Peak memory	275028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =48940642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.48940642
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.2650591300
Short name	T765
Test name
Test status
Simulation time	106771000 ps
CPU time	21.66 seconds
Started	Oct 15 09:21:50 AM UTC 24
Finished	Oct 15 09:22:13 AM UTC 24
Peak memory	274964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650591300 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.2650591300
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.2675324863
Short name	T758
Test name
Test status
Simulation time	68994200 ps
CPU time	16.52 seconds
Started	Oct 15 09:21:39 AM UTC 24
Finished	Oct 15 09:21:57 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675324863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2675324863
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.433948201
Short name	T754
Test name
Test status
Simulation time	11974500 ps
CPU time	34.51 seconds
Started	Oct 15 09:21:14 AM UTC 24
Finished	Oct 15 09:21:50 AM UTC 24
Peak memory	285344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=433948201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c trl_disable.433948201
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3355981959
Short name	T783
Test name
Test status
Simulation time	10012237500 ps
CPU time	134.12 seconds
Started	Oct 15 09:21:42 AM UTC 24
Finished	Oct 15 09:23:59 AM UTC 24
Peak memory	367144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3355981959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3355981959
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.3419898751
Short name	T761
Test name
Test status
Simulation time	153697100 ps
CPU time	24.36 seconds
Started	Oct 15 09:21:41 AM UTC 24
Finished	Oct 15 09:22:07 AM UTC 24
Peak memory	269036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3419898751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3419898751
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.560476946
Short name	T977
Test name
Test status
Simulation time	40128982100 ps
CPU time	789.38 seconds
Started	Oct 15 09:20:03 AM UTC 24
Finished	Oct 15 09:33:22 AM UTC 24
Peak memory	274744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560476946 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_reset.560476946
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.3551915557
Short name	T750
Test name
Test status
Simulation time	4680628400 ps
CPU time	91.77 seconds
Started	Oct 15 09:20:03 AM UTC 24
Finished	Oct 15 09:21:38 AM UTC 24
Peak memory	272800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551915557 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.3551915557
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.3672662676
Short name	T781
Test name
Test status
Simulation time	1988631500 ps
CPU time	190.16 seconds
Started	Oct 15 09:20:32 AM UTC 24
Finished	Oct 15 09:23:45 AM UTC 24
Peak memory	301692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672662676 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.3672662676
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.974390809
Short name	T834
Test name
Test status
Simulation time	11347578600 ps
CPU time	381.25 seconds
Started	Oct 15 09:20:38 AM UTC 24
Finished	Oct 15 09:27:04 AM UTC 24
Peak memory	301708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=974390809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 19.flash_ctrl_intr_rd_slow_flash.974390809
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3220590022
Short name	T757
Test name
Test status
Simulation time	1579572200 ps
CPU time	103.94 seconds
Started	Oct 15 09:20:09 AM UTC 24
Finished	Oct 15 09:21:55 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220590022 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3220590022
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.1626049270
Short name	T760
Test name
Test status
Simulation time	54495400 ps
CPU time	21.11 seconds
Started	Oct 15 09:21:40 AM UTC 24
Finished	Oct 15 09:22:03 AM UTC 24
Peak memory	272908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1626049270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_lcmgr_intg.1626049270
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1147572818
Short name	T822
Test name
Test status
Simulation time	4944730300 ps
CPU time	360.58 seconds
Started	Oct 15 09:20:09 AM UTC 24
Finished	Oct 15 09:26:14 AM UTC 24
Peak memory	283164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1147572818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1147572818
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.641435281
Short name	T771
Test name
Test status
Simulation time	40104700 ps
CPU time	169.03 seconds
Started	Oct 15 09:20:06 AM UTC 24
Finished	Oct 15 09:22:58 AM UTC 24
Peak memory	270856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641435281 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.641435281
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.2709746457
Short name	T796
Test name
Test status
Simulation time	182244200 ps
CPU time	289.79 seconds
Started	Oct 15 09:20:02 AM UTC 24
Finished	Oct 15 09:24:56 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709746457 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2709746457
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.956193502
Short name	T747
Test name
Test status
Simulation time	24629300 ps
CPU time	26.16 seconds
Started	Oct 15 09:20:43 AM UTC 24
Finished	Oct 15 09:21:10 AM UTC 24
Peak memory	270868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956193502 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.956193502
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.3446741818
Short name	T807
Test name
Test status
Simulation time	635742800 ps
CPU time	326.97 seconds
Started	Oct 15 09:20:02 AM UTC 24
Finished	Oct 15 09:25:34 AM UTC 24
Peak memory	291284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446741818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3446741818
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2036231956
Short name	T764
Test name
Test status
Simulation time	199370900 ps
CPU time	57.74 seconds
Started	Oct 15 09:21:11 AM UTC 24
Finished	Oct 15 09:22:11 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036231956 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.2036231956
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1926631078
Short name	T766
Test name
Test status
Simulation time	5198593900 ps
CPU time	107.66 seconds
Started	Oct 15 09:20:29 AM UTC 24
Finished	Oct 15 09:22:19 AM UTC 24
Peak memory	301716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1926631078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.1926631078
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.2273846976
Short name	T119
Test name
Test status
Simulation time	3758611300 ps
CPU time	519.16 seconds
Started	Oct 15 09:20:30 AM UTC 24
Finished	Oct 15 09:29:15 AM UTC 24
Peak memory	320164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273846976 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.2273846976
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.4283384585
Short name	T752
Test name
Test status
Simulation time	57119000 ps
CPU time	54.06 seconds
Started	Oct 15 09:20:45 AM UTC 24
Finished	Oct 15 09:21:41 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283384585 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.4283384585
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.3004878445
Short name	T753
Test name
Test status
Simulation time	29325100 ps
CPU time	34.51 seconds
Started	Oct 15 09:21:05 AM UTC 24
Finished	Oct 15 09:21:41 AM UTC 24
Peak memory	287568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3004878445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c trl_rw_evict_all_en.3004878445
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.413831850
Short name	T768
Test name
Test status
Simulation time	4037812200 ps
CPU time	64.88 seconds
Started	Oct 15 09:21:23 AM UTC 24
Finished	Oct 15 09:22:29 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413831850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.413831850
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.378533429
Short name	T786
Test name
Test status
Simulation time	30014300 ps
CPU time	261.86 seconds
Started	Oct 15 09:19:46 AM UTC 24
Finished	Oct 15 09:24:11 AM UTC 24
Peak memory	289232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378533429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.378533429
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.299711686
Short name	T22
Test name
Test status
Simulation time	40352200 ps
CPU time	25.67 seconds
Started	Oct 15 08:30:45 AM UTC 24
Finished	Oct 15 08:31:12 AM UTC 24
Peak memory	273036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=299711686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.299711686
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2031104385
Short name	T122
Test name
Test status
Simulation time	62617600 ps
CPU time	23.59 seconds
Started	Oct 15 08:31:22 AM UTC 24
Finished	Oct 15 08:31:47 AM UTC 24
Peak memory	275072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031104385 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2031104385
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.1359442904
Short name	T167
Test name
Test status
Simulation time	20082000 ps
CPU time	28.03 seconds
Started	Oct 15 08:31:07 AM UTC 24
Finished	Oct 15 08:31:37 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359442904 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.1359442904
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.989445754
Short name	T25
Test name
Test status
Simulation time	15843600 ps
CPU time	21.58 seconds
Started	Oct 15 08:30:35 AM UTC 24
Finished	Oct 15 08:30:58 AM UTC 24
Peak memory	294932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989445754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.989445754
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.386661365
Short name	T281
Test name
Test status
Simulation time	2831271700 ps
CPU time	242.3 seconds
Started	Oct 15 08:29:16 AM UTC 24
Finished	Oct 15 08:33:22 AM UTC 24
Peak memory	291532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=386661365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_derr_detect.386661365
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.543812689
Short name	T106
Test name
Test status
Simulation time	24858300 ps
CPU time	35.74 seconds
Started	Oct 15 08:30:21 AM UTC 24
Finished	Oct 15 08:30:59 AM UTC 24
Peak memory	285508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=543812689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_disable.543812689
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.4272752486
Short name	T73
Test name
Test status
Simulation time	4749284100 ps
CPU time	574.83 seconds
Started	Oct 15 08:27:18 AM UTC 24
Finished	Oct 15 08:36:59 AM UTC 24
Peak memory	274976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272752486 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4272752486
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.1165123986
Short name	T434
Test name
Test status
Simulation time	20803861400 ps
CPU time	2806.41 seconds
Started	Oct 15 08:27:46 AM UTC 24
Finished	Oct 15 09:15:00 AM UTC 24
Peak memory	277684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165123986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1165123986
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.2123499196
Short name	T116
Test name
Test status
Simulation time	576550000 ps
CPU time	2560.22 seconds
Started	Oct 15 08:27:41 AM UTC 24
Finished	Oct 15 09:10:49 AM UTC 24
Peak memory	277748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 23499196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _error_prog_type.2123499196
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.3312230334
Short name	T299
Test name
Test status
Simulation time	1905314600 ps
CPU time	1269.21 seconds
Started	Oct 15 08:27:41 AM UTC 24
Finished	Oct 15 08:49:04 AM UTC 24
Peak memory	285164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312230334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3312230334
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.545565677
Short name	T65
Test name
Test status
Simulation time	869607200 ps
CPU time	24.59 seconds
Started	Oct 15 08:27:29 AM UTC 24
Finished	Oct 15 08:27:55 AM UTC 24
Peak memory	274904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54 5565677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch _code.545565677
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.1055693761
Short name	T169
Test name
Test status
Simulation time	314937600 ps
CPU time	49.39 seconds
Started	Oct 15 08:30:54 AM UTC 24
Finished	Oct 15 08:31:45 AM UTC 24
Peak memory	275000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055693 761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f s_sup.1055693761
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.980835930
Short name	T1010
Test name
Test status
Simulation time	48914578300 ps
CPU time	3974.08 seconds
Started	Oct 15 08:27:30 AM UTC 24
Finished	Oct 15 09:34:27 AM UTC 24
Peak memory	277580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980835930 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.980835930
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3760860322
Short name	T439
Test name
Test status
Simulation time	40721500 ps
CPU time	36.64 seconds
Started	Oct 15 08:31:17 AM UTC 24
Finished	Oct 15 08:31:56 AM UTC 24
Peak memory	277068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376086032 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho st_addr_infection.3760860322
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3222853362
Short name	T748
Test name
Test status
Simulation time	1757032810200 ps
CPU time	3198.91 seconds
Started	Oct 15 08:27:21 AM UTC 24
Finished	Oct 15 09:21:13 AM UTC 24
Peak memory	277700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222853362 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.3222853362
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.39423101
Short name	T237
Test name
Test status
Simulation time	63403900 ps
CPU time	203.5 seconds
Started	Oct 15 08:27:07 AM UTC 24
Finished	Oct 15 08:30:34 AM UTC 24
Peak memory	273040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39423101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.39423101
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3355839162
Short name	T177
Test name
Test status
Simulation time	10019994800 ps
CPU time	127.25 seconds
Started	Oct 15 08:31:13 AM UTC 24
Finished	Oct 15 08:33:23 AM UTC 24
Peak memory	307772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3355839162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3355839162
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3400447804
Short name	T168
Test name
Test status
Simulation time	46705100 ps
CPU time	25.05 seconds
Started	Oct 15 08:31:13 AM UTC 24
Finished	Oct 15 08:31:40 AM UTC 24
Peak memory	275288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3400447804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3400447804
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.3951093007
Short name	T136
Test name
Test status
Simulation time	167231401100 ps
CPU time	1777.71 seconds
Started	Oct 15 08:27:19 AM UTC 24
Finished	Oct 15 08:57:15 AM UTC 24
Peak memory	277592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951093007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.3951093007
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2682927578
Short name	T137
Test name
Test status
Simulation time	80141736000 ps
CPU time	853.48 seconds
Started	Oct 15 08:27:21 AM UTC 24
Finished	Oct 15 08:41:44 AM UTC 24
Peak memory	274744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682927578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.2682927578
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.4023645952
Short name	T126
Test name
Test status
Simulation time	1043281000 ps
CPU time	53.12 seconds
Started	Oct 15 08:27:13 AM UTC 24
Finished	Oct 15 08:28:08 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023645952 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.4023645952
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3664324737
Short name	T459
Test name
Test status
Simulation time	32811895600 ps
CPU time	475.12 seconds
Started	Oct 15 08:29:19 AM UTC 24
Finished	Oct 15 08:37:20 AM UTC 24
Peak memory	342940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3664324737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr ity.3664324737
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2074760951
Short name	T346
Test name
Test status
Simulation time	9220514700 ps
CPU time	271.17 seconds
Started	Oct 15 08:29:37 AM UTC 24
Finished	Oct 15 08:34:13 AM UTC 24
Peak memory	301724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074760951 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.2074760951
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3846270211
Short name	T442
Test name
Test status
Simulation time	70071512900 ps
CPU time	186.08 seconds
Started	Oct 15 08:29:49 AM UTC 24
Finished	Oct 15 08:32:58 AM UTC 24
Peak memory	303696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3846270211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_intr_rd_slow_flash.3846270211
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.4019825507
Short name	T402
Test name
Test status
Simulation time	4888331600 ps
CPU time	85.41 seconds
Started	Oct 15 08:29:42 AM UTC 24
Finished	Oct 15 08:31:10 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019825507 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.4019825507
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2255405202
Short name	T443
Test name
Test status
Simulation time	65802363000 ps
CPU time	189.04 seconds
Started	Oct 15 08:29:53 AM UTC 24
Finished	Oct 15 08:33:05 AM UTC 24
Peak memory	275092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255405202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2255405202
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1575490996
Short name	T91
Test name
Test status
Simulation time	16922153500 ps
CPU time	135.26 seconds
Started	Oct 15 08:27:47 AM UTC 24
Finished	Oct 15 08:30:05 AM UTC 24
Peak memory	272852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575490996 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1575490996
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3823714527
Short name	T166
Test name
Test status
Simulation time	69911700 ps
CPU time	24.47 seconds
Started	Oct 15 08:31:10 AM UTC 24
Finished	Oct 15 08:31:36 AM UTC 24
Peak memory	270864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3823714527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_lcmgr_intg.3823714527
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.3962137822
Short name	T85
Test name
Test status
Simulation time	5577391000 ps
CPU time	83.75 seconds
Started	Oct 15 08:27:52 AM UTC 24
Finished	Oct 15 08:29:18 AM UTC 24
Peak memory	270708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962137822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3962137822
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.3172378319
Short name	T38
Test name
Test status
Simulation time	8175197100 ps
CPU time	220.25 seconds
Started	Oct 15 08:27:28 AM UTC 24
Finished	Oct 15 08:31:12 AM UTC 24
Peak memory	283152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3172378319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.3172378319
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3645045203
Short name	T96
Test name
Test status
Simulation time	72273900 ps
CPU time	178.78 seconds
Started	Oct 15 08:27:21 AM UTC 24
Finished	Oct 15 08:30:23 AM UTC 24
Peak memory	270644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645045203 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.3645045203
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.1149135419
Short name	T296
Test name
Test status
Simulation time	1939957300 ps
CPU time	181.59 seconds
Started	Oct 15 08:29:18 AM UTC 24
Finished	Oct 15 08:32:22 AM UTC 24
Peak memory	291516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1149135419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1149135419
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1391455636
Short name	T236
Test name
Test status
Simulation time	64199300 ps
CPU time	76.46 seconds
Started	Oct 15 08:27:10 AM UTC 24
Finished	Oct 15 08:28:29 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391455636 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1391455636
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.231293404
Short name	T165
Test name
Test status
Simulation time	38633100 ps
CPU time	22.4 seconds
Started	Oct 15 08:30:59 AM UTC 24
Finished	Oct 15 08:31:23 AM UTC 24
Peak memory	273256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=231293404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.231293404
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1225366070
Short name	T95
Test name
Test status
Simulation time	19080800 ps
CPU time	24.35 seconds
Started	Oct 15 08:29:55 AM UTC 24
Finished	Oct 15 08:30:21 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225366070 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.1225366070
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2068694883
Short name	T87
Test name
Test status
Simulation time	10821810800 ps
CPU time	613.06 seconds
Started	Oct 15 08:27:05 AM UTC 24
Finished	Oct 15 08:37:26 AM UTC 24
Peak memory	293324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068694883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2068694883
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.2359189798
Short name	T36
Test name
Test status
Simulation time	1456074100 ps
CPU time	197.99 seconds
Started	Oct 15 08:27:09 AM UTC 24
Finished	Oct 15 08:30:30 AM UTC 24
Peak memory	272972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359189798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2359189798
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2344017635
Short name	T164
Test name
Test status
Simulation time	216631500 ps
CPU time	42.15 seconds
Started	Oct 15 08:30:37 AM UTC 24
Finished	Oct 15 08:31:21 AM UTC 24
Peak memory	287300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234401763 5 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.2344017635
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2237463833
Short name	T170
Test name
Test status
Simulation time	284433500 ps
CPU time	59.48 seconds
Started	Oct 15 08:30:05 AM UTC 24
Finished	Oct 15 08:31:07 AM UTC 24
Peak memory	285424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237463833 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.2237463833
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.641764515
Short name	T200
Test name
Test status
Simulation time	75260400 ps
CPU time	39.89 seconds
Started	Oct 15 08:28:35 AM UTC 24
Finished	Oct 15 08:29:17 AM UTC 24
Peak memory	275200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=641764515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_read_word_sweep_derr.641764515
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3171465843
Short name	T399
Test name
Test status
Simulation time	85287700 ps
CPU time	26.93 seconds
Started	Oct 15 08:28:01 AM UTC 24
Finished	Oct 15 08:28:30 AM UTC 24
Peak memory	275068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171465843 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.3171465843
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.784427584
Short name	T179
Test name
Test status
Simulation time	89652707000 ps
CPU time	1469.62 seconds
Started	Oct 15 08:31:09 AM UTC 24
Finished	Oct 15 08:55:56 AM UTC 24
Peak memory	520640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=784427584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.f lash_ctrl_rma_err.784427584
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2469848355
Short name	T204
Test name
Test status
Simulation time	580358700 ps
CPU time	121.93 seconds
Started	Oct 15 08:27:55 AM UTC 24
Finished	Oct 15 08:29:59 AM UTC 24
Peak memory	301708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2469848355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.2469848355
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3640768403
Short name	T438
Test name
Test status
Simulation time	1125624700 ps
CPU time	145.36 seconds
Started	Oct 15 08:28:09 AM UTC 24
Finished	Oct 15 08:30:38 AM UTC 24
Peak memory	291540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3640768403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_ro_serr.3640768403
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4239560478
Short name	T224
Test name
Test status
Simulation time	54295031800 ps
CPU time	479.67 seconds
Started	Oct 15 08:27:56 AM UTC 24
Finished	Oct 15 08:36:02 AM UTC 24
Peak memory	320188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239560478 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.4239560478
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.711312566
Short name	T212
Test name
Test status
Simulation time	4460731700 ps
CPU time	282.39 seconds
Started	Oct 15 08:28:51 AM UTC 24
Finished	Oct 15 08:33:37 AM UTC 24
Peak memory	301796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=711312566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_rw_derr.711312566
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.3738855170
Short name	T310
Test name
Test status
Simulation time	78213600 ps
CPU time	42.51 seconds
Started	Oct 15 08:30:00 AM UTC 24
Finished	Oct 15 08:30:44 AM UTC 24
Peak memory	287444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738855170 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.3738855170
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.1746836843
Short name	T398
Test name
Test status
Simulation time	5810594300 ps
CPU time	228.39 seconds
Started	Oct 15 08:28:15 AM UTC 24
Finished	Oct 15 08:32:07 AM UTC 24
Peak memory	301764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1746836843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.1746836843
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.2727094603
Short name	T14
Test name
Test status
Simulation time	19350731000 ps
CPU time	6555.84 seconds
Started	Oct 15 08:30:24 AM UTC 24
Finished	Oct 15 10:20:51 AM UTC 24
Peak memory	316036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727094603 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2727094603
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.1020600151
Short name	T174
Test name
Test status
Simulation time	1654348200 ps
CPU time	96.14 seconds
Started	Oct 15 08:30:25 AM UTC 24
Finished	Oct 15 08:32:03 AM UTC 24
Peak memory	274924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020600151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1020600151
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.485044068
Short name	T202
Test name
Test status
Simulation time	2176076200 ps
CPU time	82.26 seconds
Started	Oct 15 08:28:30 AM UTC 24
Finished	Oct 15 08:29:54 AM UTC 24
Peak memory	275352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485 044068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr _address.485044068
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.2769326569
Short name	T201
Test name
Test status
Simulation time	607056400 ps
CPU time	77.45 seconds
Started	Oct 15 08:28:29 AM UTC 24
Finished	Oct 15 08:29:48 AM UTC 24
Peak memory	285380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 69326569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se rr_counter.2769326569
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3129897898
Short name	T39
Test name
Test status
Simulation time	6693486200 ps
CPU time	266.52 seconds
Started	Oct 15 08:26:58 AM UTC 24
Finished	Oct 15 08:31:29 AM UTC 24
Peak memory	291276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129897898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3129897898
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.208977193
Short name	T437
Test name
Test status
Simulation time	29550000 ps
CPU time	44.66 seconds
Started	Oct 15 08:26:59 AM UTC 24
Finished	Oct 15 08:27:45 AM UTC 24
Peak memory	270688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208977193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.208977193
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.3862954630
Short name	T500
Test name
Test status
Simulation time	636524200 ps
CPU time	990.74 seconds
Started	Oct 15 08:30:32 AM UTC 24
Finished	Oct 15 08:47:13 AM UTC 24
Peak memory	295336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862954630 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.3862954630
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3144360654
Short name	T436
Test name
Test status
Simulation time	23761600 ps
CPU time	31.12 seconds
Started	Oct 15 08:27:06 AM UTC 24
Finished	Oct 15 08:27:38 AM UTC 24
Peak memory	270688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144360654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3144360654
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.3197901751
Short name	T433
Test name
Test status
Simulation time	2002349800 ps
CPU time	146.57 seconds
Started	Oct 15 08:27:55 AM UTC 24
Finished	Oct 15 08:30:24 AM UTC 24
Peak memory	275020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3197901751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.3197901751
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.935382354
Short name	T19
Test name
Test status
Simulation time	156492700 ps
CPU time	28.6 seconds
Started	Oct 15 08:30:39 AM UTC 24
Finished	Oct 15 08:31:08 AM UTC 24
Peak memory	270932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935382354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_wr_intg.935382354
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.854446290
Short name	T770
Test name
Test status
Simulation time	113431400 ps
CPU time	22.97 seconds
Started	Oct 15 09:22:20 AM UTC 24
Finished	Oct 15 09:22:45 AM UTC 24
Peak memory	268804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854446290 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.854446290
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.4040427707
Short name	T769
Test name
Test status
Simulation time	28694600 ps
CPU time	26.99 seconds
Started	Oct 15 09:22:14 AM UTC 24
Finished	Oct 15 09:22:42 AM UTC 24
Peak memory	284768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040427707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.4040427707
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.1413007853
Short name	T411
Test name
Test status
Simulation time	21838100 ps
CPU time	28.42 seconds
Started	Oct 15 09:22:10 AM UTC 24
Finished	Oct 15 09:22:40 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1413007853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ ctrl_disable.1413007853
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.2811373137
Short name	T772
Test name
Test status
Simulation time	4614022400 ps
CPU time	63.16 seconds
Started	Oct 15 09:21:56 AM UTC 24
Finished	Oct 15 09:23:01 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811373137 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.2811373137
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.565485393
Short name	T785
Test name
Test status
Simulation time	798306500 ps
CPU time	129.94 seconds
Started	Oct 15 09:21:58 AM UTC 24
Finished	Oct 15 09:24:11 AM UTC 24
Peak memory	306008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565485393 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.565485393
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1994314202
Short name	T373
Test name
Test status
Simulation time	11812647200 ps
CPU time	265.51 seconds
Started	Oct 15 09:21:59 AM UTC 24
Finished	Oct 15 09:26:29 AM UTC 24
Peak memory	301620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1994314202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.flash_ctrl_intr_rd_slow_flash.1994314202
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.2411050668
Short name	T190
Test name
Test status
Simulation time	72152900 ps
CPU time	201.03 seconds
Started	Oct 15 09:21:56 AM UTC 24
Finished	Oct 15 09:25:20 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411050668 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.2411050668
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.3785672033
Short name	T767
Test name
Test status
Simulation time	22414800 ps
CPU time	24.07 seconds
Started	Oct 15 09:22:03 AM UTC 24
Finished	Oct 15 09:22:29 AM UTC 24
Peak memory	275168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785672033 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.3785672033
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.1031877285
Short name	T773
Test name
Test status
Simulation time	308418400 ps
CPU time	52.16 seconds
Started	Oct 15 09:22:09 AM UTC 24
Finished	Oct 15 09:23:02 AM UTC 24
Peak memory	285544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031877285 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.1031877285
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3289944814
Short name	T365
Test name
Test status
Simulation time	44793400 ps
CPU time	35.83 seconds
Started	Oct 15 09:22:10 AM UTC 24
Finished	Oct 15 09:22:47 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3289944814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c trl_rw_evict_all_en.3289944814
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3487002985
Short name	T778
Test name
Test status
Simulation time	790805800 ps
CPU time	88.21 seconds
Started	Oct 15 09:22:12 AM UTC 24
Finished	Oct 15 09:23:42 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487002985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3487002985
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.2317207628
Short name	T789
Test name
Test status
Simulation time	20663400 ps
CPU time	148.19 seconds
Started	Oct 15 09:21:54 AM UTC 24
Finished	Oct 15 09:24:25 AM UTC 24
Peak memory	287184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317207628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2317207628
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.3657412678
Short name	T779
Test name
Test status
Simulation time	182793700 ps
CPU time	19.4 seconds
Started	Oct 15 09:23:23 AM UTC 24
Finished	Oct 15 09:23:44 AM UTC 24
Peak memory	268932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657412678 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.3657412678
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.864668616
Short name	T780
Test name
Test status
Simulation time	15329900 ps
CPU time	31.18 seconds
Started	Oct 15 09:23:12 AM UTC 24
Finished	Oct 15 09:23:45 AM UTC 24
Peak memory	294944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864668616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.864668616
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.3439014406
Short name	T408
Test name
Test status
Simulation time	10768200 ps
CPU time	30.89 seconds
Started	Oct 15 09:23:02 AM UTC 24
Finished	Oct 15 09:23:34 AM UTC 24
Peak memory	285272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3439014406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ ctrl_disable.3439014406
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.4094396998
Short name	T324
Test name
Test status
Simulation time	1933992800 ps
CPU time	103.97 seconds
Started	Oct 15 09:22:30 AM UTC 24
Finished	Oct 15 09:24:16 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094396998 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.4094396998
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.623642535
Short name	T818
Test name
Test status
Simulation time	1726438900 ps
CPU time	196.03 seconds
Started	Oct 15 09:22:40 AM UTC 24
Finished	Oct 15 09:25:59 AM UTC 24
Peak memory	293504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623642535 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.623642535
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1037045631
Short name	T804
Test name
Test status
Simulation time	38631049900 ps
CPU time	157.73 seconds
Started	Oct 15 09:22:43 AM UTC 24
Finished	Oct 15 09:25:24 AM UTC 24
Peak memory	303668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1037045631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.flash_ctrl_intr_rd_slow_flash.1037045631
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.4201982256
Short name	T805
Test name
Test status
Simulation time	145940300 ps
CPU time	171.77 seconds
Started	Oct 15 09:22:30 AM UTC 24
Finished	Oct 15 09:25:25 AM UTC 24
Peak memory	272952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201982256 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.4201982256
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.3589534089
Short name	T774
Test name
Test status
Simulation time	19484800 ps
CPU time	24.44 seconds
Started	Oct 15 09:22:45 AM UTC 24
Finished	Oct 15 09:23:11 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589534089 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.3589534089
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.204956783
Short name	T782
Test name
Test status
Simulation time	75273500 ps
CPU time	58.84 seconds
Started	Oct 15 09:22:48 AM UTC 24
Finished	Oct 15 09:23:48 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204956783 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.204956783
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3483632957
Short name	T791
Test name
Test status
Simulation time	1603588600 ps
CPU time	80.87 seconds
Started	Oct 15 09:23:03 AM UTC 24
Finished	Oct 15 09:24:26 AM UTC 24
Peak memory	275112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483632957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3483632957
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2451207142
Short name	T800
Test name
Test status
Simulation time	37055000 ps
CPU time	157.92 seconds
Started	Oct 15 09:22:30 AM UTC 24
Finished	Oct 15 09:25:10 AM UTC 24
Peak memory	289236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451207142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2451207142
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.4109599578
Short name	T792
Test name
Test status
Simulation time	262267700 ps
CPU time	24.87 seconds
Started	Oct 15 09:24:00 AM UTC 24
Finished	Oct 15 09:24:27 AM UTC 24
Peak memory	268800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109599578 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.4109599578
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.778415194
Short name	T787
Test name
Test status
Simulation time	16877600 ps
CPU time	25.42 seconds
Started	Oct 15 09:23:49 AM UTC 24
Finished	Oct 15 09:24:16 AM UTC 24
Peak memory	284768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778415194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.778415194
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.3138902885
Short name	T788
Test name
Test status
Simulation time	53438200 ps
CPU time	35.59 seconds
Started	Oct 15 09:23:46 AM UTC 24
Finished	Oct 15 09:24:23 AM UTC 24
Peak memory	285336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3138902885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ ctrl_disable.3138902885
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.2071275793
Short name	T806
Test name
Test status
Simulation time	8577058800 ps
CPU time	116.88 seconds
Started	Oct 15 09:23:32 AM UTC 24
Finished	Oct 15 09:25:31 AM UTC 24
Peak memory	272796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071275793 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.2071275793
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.1569794997
Short name	T815
Test name
Test status
Simulation time	820442800 ps
CPU time	128.16 seconds
Started	Oct 15 09:23:38 AM UTC 24
Finished	Oct 15 09:25:48 AM UTC 24
Peak memory	303964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569794997 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.1569794997
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.964866549
Short name	T821
Test name
Test status
Simulation time	5709137500 ps
CPU time	148.48 seconds
Started	Oct 15 09:23:42 AM UTC 24
Finished	Oct 15 09:26:13 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=964866549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 22.flash_ctrl_intr_rd_slow_flash.964866549
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.1474280431
Short name	T784
Test name
Test status
Simulation time	37395500 ps
CPU time	22.75 seconds
Started	Oct 15 09:23:44 AM UTC 24
Finished	Oct 15 09:24:08 AM UTC 24
Peak memory	274908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474280431 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.1474280431
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.224187715
Short name	T790
Test name
Test status
Simulation time	88480300 ps
CPU time	40.16 seconds
Started	Oct 15 09:23:44 AM UTC 24
Finished	Oct 15 09:24:25 AM UTC 24
Peak memory	287472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224187715 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.224187715
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.77942347
Short name	T802
Test name
Test status
Simulation time	7953406900 ps
CPU time	88.4 seconds
Started	Oct 15 09:23:46 AM UTC 24
Finished	Oct 15 09:25:16 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77942347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.77942347
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.2645058651
Short name	T810
Test name
Test status
Simulation time	30997800 ps
CPU time	134.91 seconds
Started	Oct 15 09:23:24 AM UTC 24
Finished	Oct 15 09:25:42 AM UTC 24
Peak memory	287188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645058651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2645058651
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.2513048129
Short name	T797
Test name
Test status
Simulation time	31520500 ps
CPU time	17.74 seconds
Started	Oct 15 09:24:38 AM UTC 24
Finished	Oct 15 09:24:57 AM UTC 24
Peak memory	270852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513048129 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.2513048129
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.599564085
Short name	T798
Test name
Test status
Simulation time	16379400 ps
CPU time	23.73 seconds
Started	Oct 15 09:24:37 AM UTC 24
Finished	Oct 15 09:25:02 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599564085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.599564085
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.4196618073
Short name	T799
Test name
Test status
Simulation time	29031300 ps
CPU time	36.14 seconds
Started	Oct 15 09:24:26 AM UTC 24
Finished	Oct 15 09:25:04 AM UTC 24
Peak memory	285312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4196618073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ ctrl_disable.4196618073
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3416496464
Short name	T801
Test name
Test status
Simulation time	4762955100 ps
CPU time	61.15 seconds
Started	Oct 15 09:24:12 AM UTC 24
Finished	Oct 15 09:25:14 AM UTC 24
Peak memory	272800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416496464 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.3416496464
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.488991958
Short name	T845
Test name
Test status
Simulation time	1954453300 ps
CPU time	188.36 seconds
Started	Oct 15 09:24:17 AM UTC 24
Finished	Oct 15 09:27:28 AM UTC 24
Peak memory	301848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488991958 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.488991958
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3561897066
Short name	T844
Test name
Test status
Simulation time	24101205600 ps
CPU time	184.74 seconds
Started	Oct 15 09:24:17 AM UTC 24
Finished	Oct 15 09:27:25 AM UTC 24
Peak memory	305776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3561897066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.flash_ctrl_intr_rd_slow_flash.3561897066
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3139446730
Short name	T847
Test name
Test status
Simulation time	46588800 ps
CPU time	193.33 seconds
Started	Oct 15 09:24:13 AM UTC 24
Finished	Oct 15 09:27:29 AM UTC 24
Peak memory	273164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139446730 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.3139446730
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.2447791249
Short name	T795
Test name
Test status
Simulation time	33179100 ps
CPU time	28.04 seconds
Started	Oct 15 09:24:24 AM UTC 24
Finished	Oct 15 09:24:53 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447791249 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.2447791249
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.2717459768
Short name	T803
Test name
Test status
Simulation time	29480500 ps
CPU time	50.72 seconds
Started	Oct 15 09:24:25 AM UTC 24
Finished	Oct 15 09:25:18 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717459768 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.2717459768
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.2349464042
Short name	T369
Test name
Test status
Simulation time	79646500 ps
CPU time	47.8 seconds
Started	Oct 15 09:24:26 AM UTC 24
Finished	Oct 15 09:25:16 AM UTC 24
Peak memory	285384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2349464042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c trl_rw_evict_all_en.2349464042
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.2611995051
Short name	T811
Test name
Test status
Simulation time	2571769600 ps
CPU time	73.73 seconds
Started	Oct 15 09:24:27 AM UTC 24
Finished	Oct 15 09:25:43 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611995051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2611995051
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.3500612125
Short name	T829
Test name
Test status
Simulation time	71303300 ps
CPU time	152.55 seconds
Started	Oct 15 09:24:08 AM UTC 24
Finished	Oct 15 09:26:44 AM UTC 24
Peak memory	278996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500612125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3500612125
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.2066496951
Short name	T808
Test name
Test status
Simulation time	271819300 ps
CPU time	17.04 seconds
Started	Oct 15 09:25:19 AM UTC 24
Finished	Oct 15 09:25:37 AM UTC 24
Peak memory	268820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066496951 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.2066496951
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.2104508241
Short name	T812
Test name
Test status
Simulation time	37817600 ps
CPU time	25.23 seconds
Started	Oct 15 09:25:17 AM UTC 24
Finished	Oct 15 09:25:44 AM UTC 24
Peak memory	294936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104508241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2104508241
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.1356100474
Short name	T849
Test name
Test status
Simulation time	8055711000 ps
CPU time	159.31 seconds
Started	Oct 15 09:24:54 AM UTC 24
Finished	Oct 15 09:27:36 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356100474 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.1356100474
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.287790935
Short name	T851
Test name
Test status
Simulation time	1594390600 ps
CPU time	166.33 seconds
Started	Oct 15 09:24:57 AM UTC 24
Finished	Oct 15 09:27:46 AM UTC 24
Peak memory	306048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287790935 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.287790935
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.25355655
Short name	T948
Test name
Test status
Simulation time	51061465200 ps
CPU time	422.82 seconds
Started	Oct 15 09:25:02 AM UTC 24
Finished	Oct 15 09:32:11 AM UTC 24
Peak memory	301648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=25355655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.flash_ctrl_intr_rd_slow_flash.25355655
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.3601267650
Short name	T842
Test name
Test status
Simulation time	126082300 ps
CPU time	143.79 seconds
Started	Oct 15 09:24:57 AM UTC 24
Finished	Oct 15 09:27:23 AM UTC 24
Peak memory	270480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601267650 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.3601267650
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.3426918340
Short name	T854
Test name
Test status
Simulation time	3958971400 ps
CPU time	168.57 seconds
Started	Oct 15 09:25:04 AM UTC 24
Finished	Oct 15 09:27:56 AM UTC 24
Peak memory	275168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426918340 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.3426918340
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.3454742879
Short name	T813
Test name
Test status
Simulation time	44943900 ps
CPU time	37.46 seconds
Started	Oct 15 09:25:06 AM UTC 24
Finished	Oct 15 09:25:44 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454742879 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.3454742879
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3970260395
Short name	T814
Test name
Test status
Simulation time	29598700 ps
CPU time	33.76 seconds
Started	Oct 15 09:25:11 AM UTC 24
Finished	Oct 15 09:25:46 AM UTC 24
Peak memory	285520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3970260395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_rw_evict_all_en.3970260395
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.528037625
Short name	T831
Test name
Test status
Simulation time	1832549600 ps
CPU time	89.92 seconds
Started	Oct 15 09:25:17 AM UTC 24
Finished	Oct 15 09:26:49 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528037625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.528037625
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.3935138608
Short name	T836
Test name
Test status
Simulation time	77413100 ps
CPU time	138.78 seconds
Started	Oct 15 09:24:45 AM UTC 24
Finished	Oct 15 09:27:06 AM UTC 24
Peak memory	287184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935138608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3935138608
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.1019978885
Short name	T823
Test name
Test status
Simulation time	127800400 ps
CPU time	28.32 seconds
Started	Oct 15 09:25:47 AM UTC 24
Finished	Oct 15 09:26:16 AM UTC 24
Peak memory	268948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019978885 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.1019978885
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.3136337931
Short name	T820
Test name
Test status
Simulation time	22762400 ps
CPU time	14.75 seconds
Started	Oct 15 09:25:46 AM UTC 24
Finished	Oct 15 09:26:01 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136337931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.3136337931
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.2147856482
Short name	T130
Test name
Test status
Simulation time	10126500 ps
CPU time	22.53 seconds
Started	Oct 15 09:25:44 AM UTC 24
Finished	Oct 15 09:26:08 AM UTC 24
Peak memory	285532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2147856482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ ctrl_disable.2147856482
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.4086501161
Short name	T841
Test name
Test status
Simulation time	10214103900 ps
CPU time	110.69 seconds
Started	Oct 15 09:25:24 AM UTC 24
Finished	Oct 15 09:27:18 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086501161 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.4086501161
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3567097102
Short name	T865
Test name
Test status
Simulation time	1744842800 ps
CPU time	168.12 seconds
Started	Oct 15 09:25:32 AM UTC 24
Finished	Oct 15 09:28:23 AM UTC 24
Peak memory	301724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567097102 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.3567097102
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.812218425
Short name	T911
Test name
Test status
Simulation time	12489045000 ps
CPU time	291.08 seconds
Started	Oct 15 09:25:35 AM UTC 24
Finished	Oct 15 09:30:30 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=812218425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 25.flash_ctrl_intr_rd_slow_flash.812218425
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.3893869397
Short name	T862
Test name
Test status
Simulation time	229726000 ps
CPU time	170.99 seconds
Started	Oct 15 09:25:25 AM UTC 24
Finished	Oct 15 09:28:19 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893869397 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.3893869397
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.4049837579
Short name	T819
Test name
Test status
Simulation time	18169600 ps
CPU time	20.79 seconds
Started	Oct 15 09:25:38 AM UTC 24
Finished	Oct 15 09:26:00 AM UTC 24
Peak memory	275040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049837579 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.4049837579
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.3654209024
Short name	T824
Test name
Test status
Simulation time	43378600 ps
CPU time	36.67 seconds
Started	Oct 15 09:25:41 AM UTC 24
Finished	Oct 15 09:26:19 AM UTC 24
Peak memory	287428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654209024 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.3654209024
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.1356107197
Short name	T366
Test name
Test status
Simulation time	56442900 ps
CPU time	50.59 seconds
Started	Oct 15 09:25:42 AM UTC 24
Finished	Oct 15 09:26:34 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1356107197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c trl_rw_evict_all_en.1356107197
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1963765273
Short name	T825
Test name
Test status
Simulation time	41622800 ps
CPU time	57.27 seconds
Started	Oct 15 09:25:21 AM UTC 24
Finished	Oct 15 09:26:20 AM UTC 24
Peak memory	285140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963765273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1963765273
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.3833539338
Short name	T827
Test name
Test status
Simulation time	172198800 ps
CPU time	20.61 seconds
Started	Oct 15 09:26:20 AM UTC 24
Finished	Oct 15 09:26:42 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833539338 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.3833539338
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1670555795
Short name	T832
Test name
Test status
Simulation time	37101300 ps
CPU time	30.24 seconds
Started	Oct 15 09:26:17 AM UTC 24
Finished	Oct 15 09:26:49 AM UTC 24
Peak memory	284764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670555795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1670555795
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.4127236443
Short name	T830
Test name
Test status
Simulation time	14782400 ps
CPU time	31.61 seconds
Started	Oct 15 09:26:14 AM UTC 24
Finished	Oct 15 09:26:47 AM UTC 24
Peak memory	285252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4127236443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ ctrl_disable.4127236443
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.1310862260
Short name	T858
Test name
Test status
Simulation time	18745238000 ps
CPU time	132.01 seconds
Started	Oct 15 09:25:52 AM UTC 24
Finished	Oct 15 09:28:06 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310862260 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.1310862260
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.3541392881
Short name	T855
Test name
Test status
Simulation time	1283160500 ps
CPU time	124.75 seconds
Started	Oct 15 09:25:55 AM UTC 24
Finished	Oct 15 09:28:03 AM UTC 24
Peak memory	301780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541392881 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.3541392881
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1873360310
Short name	T863
Test name
Test status
Simulation time	5859038300 ps
CPU time	137.92 seconds
Started	Oct 15 09:26:00 AM UTC 24
Finished	Oct 15 09:28:21 AM UTC 24
Peak memory	303668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1873360310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.flash_ctrl_intr_rd_slow_flash.1873360310
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.2781339029
Short name	T856
Test name
Test status
Simulation time	144626200 ps
CPU time	129.26 seconds
Started	Oct 15 09:25:53 AM UTC 24
Finished	Oct 15 09:28:04 AM UTC 24
Peak memory	271032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781339029 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.2781339029
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.2796332590
Short name	T826
Test name
Test status
Simulation time	1798291100 ps
CPU time	29.68 seconds
Started	Oct 15 09:26:01 AM UTC 24
Finished	Oct 15 09:26:32 AM UTC 24
Peak memory	270940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796332590 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.2796332590
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.3966456102
Short name	T828
Test name
Test status
Simulation time	69137000 ps
CPU time	37.87 seconds
Started	Oct 15 09:26:02 AM UTC 24
Finished	Oct 15 09:26:42 AM UTC 24
Peak memory	287560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966456102 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.3966456102
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.820001427
Short name	T833
Test name
Test status
Simulation time	38898400 ps
CPU time	46.64 seconds
Started	Oct 15 09:26:09 AM UTC 24
Finished	Oct 15 09:26:57 AM UTC 24
Peak memory	285540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=820001427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ct rl_rw_evict_all_en.820001427
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.2966019743
Short name	T843
Test name
Test status
Simulation time	2196524500 ps
CPU time	66.67 seconds
Started	Oct 15 09:26:15 AM UTC 24
Finished	Oct 15 09:27:24 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966019743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2966019743
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.3363073070
Short name	T913
Test name
Test status
Simulation time	78165900 ps
CPU time	282.81 seconds
Started	Oct 15 09:25:49 AM UTC 24
Finished	Oct 15 09:30:36 AM UTC 24
Peak memory	291280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363073070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3363073070
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.1104452081
Short name	T840
Test name
Test status
Simulation time	139965300 ps
CPU time	19.32 seconds
Started	Oct 15 09:26:57 AM UTC 24
Finished	Oct 15 09:27:18 AM UTC 24
Peak memory	268816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104452081 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.1104452081
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.378789352
Short name	T839
Test name
Test status
Simulation time	46097600 ps
CPU time	21.63 seconds
Started	Oct 15 09:26:50 AM UTC 24
Finished	Oct 15 09:27:13 AM UTC 24
Peak memory	284768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378789352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.378789352
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.3626187542
Short name	T866
Test name
Test status
Simulation time	4244633800 ps
CPU time	120.63 seconds
Started	Oct 15 09:26:21 AM UTC 24
Finished	Oct 15 09:28:24 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626187542 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.3626187542
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.795252379
Short name	T877
Test name
Test status
Simulation time	2211031000 ps
CPU time	151.87 seconds
Started	Oct 15 09:26:33 AM UTC 24
Finished	Oct 15 09:29:08 AM UTC 24
Peak memory	303808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795252379 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.795252379
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1952841107
Short name	T875
Test name
Test status
Simulation time	22021921600 ps
CPU time	146.53 seconds
Started	Oct 15 09:26:35 AM UTC 24
Finished	Oct 15 09:29:04 AM UTC 24
Peak memory	303696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1952841107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.flash_ctrl_intr_rd_slow_flash.1952841107
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.770738014
Short name	T885
Test name
Test status
Simulation time	182042000 ps
CPU time	169.7 seconds
Started	Oct 15 09:26:30 AM UTC 24
Finished	Oct 15 09:29:22 AM UTC 24
Peak memory	270964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770738014 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.770738014
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.4007610135
Short name	T835
Test name
Test status
Simulation time	19051200 ps
CPU time	22.65 seconds
Started	Oct 15 09:26:42 AM UTC 24
Finished	Oct 15 09:27:06 AM UTC 24
Peak memory	274904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007610135 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.4007610135
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.3397597900
Short name	T848
Test name
Test status
Simulation time	37186700 ps
CPU time	50.25 seconds
Started	Oct 15 09:26:43 AM UTC 24
Finished	Oct 15 09:27:35 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397597900 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.3397597900
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.3937522603
Short name	T846
Test name
Test status
Simulation time	53754300 ps
CPU time	42.93 seconds
Started	Oct 15 09:26:45 AM UTC 24
Finished	Oct 15 09:27:29 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3937522603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c trl_rw_evict_all_en.3937522603
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.1321061886
Short name	T853
Test name
Test status
Simulation time	19206900 ps
CPU time	87.97 seconds
Started	Oct 15 09:26:20 AM UTC 24
Finished	Oct 15 09:27:50 AM UTC 24
Peak memory	285144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321061886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1321061886
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.2353116155
Short name	T850
Test name
Test status
Simulation time	33405100 ps
CPU time	16.72 seconds
Started	Oct 15 09:27:25 AM UTC 24
Finished	Oct 15 09:27:44 AM UTC 24
Peak memory	268800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353116155 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.2353116155
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.1235241450
Short name	T852
Test name
Test status
Simulation time	60556200 ps
CPU time	23.5 seconds
Started	Oct 15 09:27:24 AM UTC 24
Finished	Oct 15 09:27:49 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235241450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1235241450
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.1661647197
Short name	T414
Test name
Test status
Simulation time	30643500 ps
CPU time	26.11 seconds
Started	Oct 15 09:27:18 AM UTC 24
Finished	Oct 15 09:27:46 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1661647197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ ctrl_disable.1661647197
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.624195182
Short name	T883
Test name
Test status
Simulation time	17548531600 ps
CPU time	132.62 seconds
Started	Oct 15 09:27:05 AM UTC 24
Finished	Oct 15 09:29:20 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624195182 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.624195182
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.3001650925
Short name	T887
Test name
Test status
Simulation time	911031500 ps
CPU time	140.24 seconds
Started	Oct 15 09:27:07 AM UTC 24
Finished	Oct 15 09:29:30 AM UTC 24
Peak memory	303808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001650925 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.3001650925
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1379012741
Short name	T942
Test name
Test status
Simulation time	25128067200 ps
CPU time	280.82 seconds
Started	Oct 15 09:27:07 AM UTC 24
Finished	Oct 15 09:31:52 AM UTC 24
Peak memory	303672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1379012741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.flash_ctrl_intr_rd_slow_flash.1379012741
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.3152442129
Short name	T892
Test name
Test status
Simulation time	109526500 ps
CPU time	161.93 seconds
Started	Oct 15 09:27:07 AM UTC 24
Finished	Oct 15 09:29:52 AM UTC 24
Peak memory	270648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152442129 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.3152442129
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.526065952
Short name	T860
Test name
Test status
Simulation time	40804000 ps
CPU time	60.76 seconds
Started	Oct 15 09:27:12 AM UTC 24
Finished	Oct 15 09:28:14 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526065952 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.526065952
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.4111006213
Short name	T857
Test name
Test status
Simulation time	26781800 ps
CPU time	48.82 seconds
Started	Oct 15 09:27:14 AM UTC 24
Finished	Oct 15 09:28:05 AM UTC 24
Peak memory	287632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4111006213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c trl_rw_evict_all_en.4111006213
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.208117392
Short name	T912
Test name
Test status
Simulation time	209814200 ps
CPU time	211.93 seconds
Started	Oct 15 09:26:58 AM UTC 24
Finished	Oct 15 09:30:33 AM UTC 24
Peak memory	289240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208117392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.208117392
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.2293986043
Short name	T861
Test name
Test status
Simulation time	79869200 ps
CPU time	23.4 seconds
Started	Oct 15 09:27:51 AM UTC 24
Finished	Oct 15 09:28:16 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293986043 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.2293986043
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.3442105650
Short name	T859
Test name
Test status
Simulation time	21894700 ps
CPU time	21.25 seconds
Started	Oct 15 09:27:50 AM UTC 24
Finished	Oct 15 09:28:13 AM UTC 24
Peak memory	294936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442105650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3442105650
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.909758104
Short name	T864
Test name
Test status
Simulation time	143651300 ps
CPU time	33.06 seconds
Started	Oct 15 09:27:47 AM UTC 24
Finished	Oct 15 09:28:21 AM UTC 24
Peak memory	285248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=909758104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c trl_disable.909758104
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.3540264632
Short name	T882
Test name
Test status
Simulation time	21883862900 ps
CPU time	107.96 seconds
Started	Oct 15 09:27:29 AM UTC 24
Finished	Oct 15 09:29:19 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540264632 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.3540264632
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.3930206481
Short name	T923
Test name
Test status
Simulation time	2791049000 ps
CPU time	208.92 seconds
Started	Oct 15 09:27:30 AM UTC 24
Finished	Oct 15 09:31:03 AM UTC 24
Peak memory	301692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930206481 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.3930206481
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4178419901
Short name	T921
Test name
Test status
Simulation time	22805736700 ps
CPU time	203.24 seconds
Started	Oct 15 09:27:31 AM UTC 24
Finished	Oct 15 09:30:58 AM UTC 24
Peak memory	303796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4178419901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.flash_ctrl_intr_rd_slow_flash.4178419901
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.2921520495
Short name	T901
Test name
Test status
Simulation time	80606900 ps
CPU time	157.99 seconds
Started	Oct 15 09:27:30 AM UTC 24
Finished	Oct 15 09:30:12 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921520495 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.2921520495
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.1156861582
Short name	T926
Test name
Test status
Simulation time	8276311600 ps
CPU time	209.86 seconds
Started	Oct 15 09:27:36 AM UTC 24
Finished	Oct 15 09:31:09 AM UTC 24
Peak memory	275040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156861582 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.1156861582
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.264473248
Short name	T868
Test name
Test status
Simulation time	77034800 ps
CPU time	51.31 seconds
Started	Oct 15 09:27:37 AM UTC 24
Finished	Oct 15 09:28:30 AM UTC 24
Peak memory	285384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264473248 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.264473248
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.1774870263
Short name	T431
Test name
Test status
Simulation time	1688722300 ps
CPU time	78.28 seconds
Started	Oct 15 09:27:48 AM UTC 24
Finished	Oct 15 09:29:08 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774870263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1774870263
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.1695031595
Short name	T935
Test name
Test status
Simulation time	65511300 ps
CPU time	251.33 seconds
Started	Oct 15 09:27:26 AM UTC 24
Finished	Oct 15 09:31:41 AM UTC 24
Peak memory	291288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695031595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1695031595
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.2408120215
Short name	T319
Test name
Test status
Simulation time	33107100 ps
CPU time	23.7 seconds
Started	Oct 15 08:36:35 AM UTC 24
Finished	Oct 15 08:37:00 AM UTC 24
Peak memory	268816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408120215 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2408120215
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.3124882767
Short name	T455
Test name
Test status
Simulation time	35740200 ps
CPU time	22.77 seconds
Started	Oct 15 08:36:13 AM UTC 24
Finished	Oct 15 08:36:37 AM UTC 24
Peak memory	272960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124882767 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.3124882767
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.1472063984
Short name	T318
Test name
Test status
Simulation time	28303100 ps
CPU time	24.43 seconds
Started	Oct 15 08:36:06 AM UTC 24
Finished	Oct 15 08:36:32 AM UTC 24
Peak memory	294936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472063984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1472063984
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1622873400
Short name	T314
Test name
Test status
Simulation time	670374400 ps
CPU time	215.7 seconds
Started	Oct 15 08:34:08 AM UTC 24
Finished	Oct 15 08:37:46 AM UTC 24
Peak memory	285376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1622873400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.1622873400
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2575820529
Short name	T196
Test name
Test status
Simulation time	52777500 ps
CPU time	35.79 seconds
Started	Oct 15 08:35:29 AM UTC 24
Finished	Oct 15 08:36:06 AM UTC 24
Peak memory	285248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2575820529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_disable.2575820529
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.3827688830
Short name	T258
Test name
Test status
Simulation time	8505198900 ps
CPU time	491.64 seconds
Started	Oct 15 08:31:46 AM UTC 24
Finished	Oct 15 08:40:04 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827688830 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.3827688830
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.3174247464
Short name	T295
Test name
Test status
Simulation time	9433335000 ps
CPU time	2518.88 seconds
Started	Oct 15 08:32:23 AM UTC 24
Finished	Oct 15 09:14:47 AM UTC 24
Peak memory	275832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174247464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.3174247464
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.3341105724
Short name	T117
Test name
Test status
Simulation time	897882400 ps
CPU time	3323.42 seconds
Started	Oct 15 08:32:16 AM UTC 24
Finished	Oct 15 09:28:14 AM UTC 24
Peak memory	277744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 41105724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _error_prog_type.3341105724
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.3429139321
Short name	T520
Test name
Test status
Simulation time	807030900 ps
CPU time	1116.36 seconds
Started	Oct 15 08:32:19 AM UTC 24
Finished	Oct 15 08:51:07 AM UTC 24
Peak memory	285160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429139321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3429139321
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.1791243810
Short name	T282
Test name
Test status
Simulation time	798916500 ps
CPU time	39.27 seconds
Started	Oct 15 08:36:06 AM UTC 24
Finished	Oct 15 08:36:47 AM UTC 24
Peak memory	274996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791243 810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f s_sup.1791243810
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.113785389
Short name	T142
Test name
Test status
Simulation time	190955190600 ps
CPU time	2517.45 seconds
Started	Oct 15 08:32:10 AM UTC 24
Finished	Oct 15 09:14:34 AM UTC 24
Peak memory	277612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113785389 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.113785389
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.1320157969
Short name	T657
Test name
Test status
Simulation time	577926611500 ps
CPU time	2430.31 seconds
Started	Oct 15 08:31:57 AM UTC 24
Finished	Oct 15 09:12:55 AM UTC 24
Peak memory	277696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320157969 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.1320157969
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.270697888
Short name	T445
Test name
Test status
Simulation time	92504900 ps
CPU time	147.07 seconds
Started	Oct 15 08:31:29 AM UTC 24
Finished	Oct 15 08:33:59 AM UTC 24
Peak memory	274900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270697888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.270697888
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1859724210
Short name	T287
Test name
Test status
Simulation time	10039582300 ps
CPU time	64.95 seconds
Started	Oct 15 08:36:32 AM UTC 24
Finished	Oct 15 08:37:39 AM UTC 24
Peak memory	277344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1859724210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1859724210
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3335831019
Short name	T456
Test name
Test status
Simulation time	15657600 ps
CPU time	20.61 seconds
Started	Oct 15 08:36:27 AM UTC 24
Finished	Oct 15 08:36:49 AM UTC 24
Peak memory	269028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3335831019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.3335831019
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.3983777343
Short name	T150
Test name
Test status
Simulation time	40118513800 ps
CPU time	773.99 seconds
Started	Oct 15 08:31:48 AM UTC 24
Finished	Oct 15 08:44:51 AM UTC 24
Peak memory	274816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983777343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.3983777343
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.2506457379
Short name	T435
Test name
Test status
Simulation time	2657183900 ps
CPU time	65.85 seconds
Started	Oct 15 08:31:41 AM UTC 24
Finished	Oct 15 08:32:48 AM UTC 24
Peak memory	274856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506457379 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.2506457379
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2400903675
Short name	T487
Test name
Test status
Simulation time	9200619700 ps
CPU time	602.75 seconds
Started	Oct 15 08:34:15 AM UTC 24
Finished	Oct 15 08:44:26 AM UTC 24
Peak memory	340824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2400903675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr ity.2400903675
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.839395972
Short name	T343
Test name
Test status
Simulation time	1209887600 ps
CPU time	157.21 seconds
Started	Oct 15 08:34:33 AM UTC 24
Finished	Oct 15 08:37:13 AM UTC 24
Peak memory	305856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839395972 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.839395972
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1970953349
Short name	T342
Test name
Test status
Simulation time	12322905900 ps
CPU time	401.35 seconds
Started	Oct 15 08:34:55 AM UTC 24
Finished	Oct 15 08:41:41 AM UTC 24
Peak memory	293644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1970953349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_intr_rd_slow_flash.1970953349
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.494856843
Short name	T451
Test name
Test status
Simulation time	11073610700 ps
CPU time	87.87 seconds
Started	Oct 15 08:34:35 AM UTC 24
Finished	Oct 15 08:36:05 AM UTC 24
Peak memory	270940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494856843 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.494856843
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1800571344
Short name	T471
Test name
Test status
Simulation time	25408975800 ps
CPU time	350.2 seconds
Started	Oct 15 08:34:56 AM UTC 24
Finished	Oct 15 08:40:51 AM UTC 24
Peak memory	270912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800571344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1800571344
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.3953762033
Short name	T158
Test name
Test status
Simulation time	3384139700 ps
CPU time	79.11 seconds
Started	Oct 15 08:32:30 AM UTC 24
Finished	Oct 15 08:33:51 AM UTC 24
Peak memory	272852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953762033 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3953762033
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.4051780891
Short name	T292
Test name
Test status
Simulation time	15746500 ps
CPU time	23.61 seconds
Started	Oct 15 08:36:15 AM UTC 24
Finished	Oct 15 08:36:40 AM UTC 24
Peak memory	274984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4051780891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_lcmgr_intg.4051780891
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1292902926
Short name	T462
Test name
Test status
Simulation time	12342581600 ps
CPU time	270.27 seconds
Started	Oct 15 08:34:14 AM UTC 24
Finished	Oct 15 08:38:48 AM UTC 24
Peak memory	291532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1292902926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1292902926
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.2463173708
Short name	T479
Test name
Test status
Simulation time	300779200 ps
CPU time	616.83 seconds
Started	Oct 15 08:31:38 AM UTC 24
Finished	Oct 15 08:42:02 AM UTC 24
Peak memory	275036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463173708 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2463173708
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.1236577062
Short name	T450
Test name
Test status
Simulation time	103376700 ps
CPU time	20.21 seconds
Started	Oct 15 08:35:00 AM UTC 24
Finished	Oct 15 08:35:21 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236577062 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.1236577062
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1133862751
Short name	T256
Test name
Test status
Simulation time	3169561800 ps
CPU time	403.42 seconds
Started	Oct 15 08:31:26 AM UTC 24
Finished	Oct 15 08:38:15 AM UTC 24
Peak memory	291284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133862751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1133862751
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.1348106713
Short name	T449
Test name
Test status
Simulation time	102660100 ps
CPU time	214.54 seconds
Started	Oct 15 08:31:37 AM UTC 24
Finished	Oct 15 08:35:15 AM UTC 24
Peak memory	272840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348106713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1348106713
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.4275722549
Short name	T219
Test name
Test status
Simulation time	135616000 ps
CPU time	43.6 seconds
Started	Oct 15 08:35:22 AM UTC 24
Finished	Oct 15 08:36:07 AM UTC 24
Peak memory	287568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275722549 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.4275722549
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3548673444
Short name	T446
Test name
Test status
Simulation time	31855100 ps
CPU time	39.73 seconds
Started	Oct 15 08:33:52 AM UTC 24
Finished	Oct 15 08:34:33 AM UTC 24
Peak memory	275204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3548673444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_read_word_sweep_derr.3548673444
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.4071577300
Short name	T444
Test name
Test status
Simulation time	23020100 ps
CPU time	24.79 seconds
Started	Oct 15 08:33:23 AM UTC 24
Finished	Oct 15 08:33:49 AM UTC 24
Peak memory	275268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071577300 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.4071577300
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2946844426
Short name	T213
Test name
Test status
Simulation time	457081100 ps
CPU time	146.53 seconds
Started	Oct 15 08:32:59 AM UTC 24
Finished	Oct 15 08:35:29 AM UTC 24
Peak memory	291536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2946844426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.2946844426
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3942072691
Short name	T454
Test name
Test status
Simulation time	2532106400 ps
CPU time	152.29 seconds
Started	Oct 15 08:34:00 AM UTC 24
Finished	Oct 15 08:36:35 AM UTC 24
Peak memory	291520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942072691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3942072691
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.678338858
Short name	T229
Test name
Test status
Simulation time	1253710200 ps
CPU time	127.56 seconds
Started	Oct 15 08:33:24 AM UTC 24
Finished	Oct 15 08:35:33 AM UTC 24
Peak memory	305872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=678338858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ ctrl_ro_serr.678338858
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.819033496
Short name	T226
Test name
Test status
Simulation time	7790960300 ps
CPU time	418.09 seconds
Started	Oct 15 08:33:06 AM UTC 24
Finished	Oct 15 08:40:09 AM UTC 24
Peak memory	320196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819033496 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.819033496
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.2653950669
Short name	T222
Test name
Test status
Simulation time	951819700 ps
CPU time	168.7 seconds
Started	Oct 15 08:34:03 AM UTC 24
Finished	Oct 15 08:36:55 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2653950669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.flash_ctrl_rw_derr.2653950669
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.3640080779
Short name	T57
Test name
Test status
Simulation time	27133000 ps
CPU time	40.92 seconds
Started	Oct 15 08:35:00 AM UTC 24
Finished	Oct 15 08:35:42 AM UTC 24
Peak memory	287572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640080779 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.3640080779
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2632558480
Short name	T367
Test name
Test status
Simulation time	75875900 ps
CPU time	49.01 seconds
Started	Oct 15 08:35:15 AM UTC 24
Finished	Oct 15 08:36:06 AM UTC 24
Peak memory	287464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2632558480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct rl_rw_evict_all_en.2632558480
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.593874247
Short name	T453
Test name
Test status
Simulation time	3428247000 ps
CPU time	161.98 seconds
Started	Oct 15 08:33:28 AM UTC 24
Finished	Oct 15 08:36:12 AM UTC 24
Peak memory	305988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=593874247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.593874247
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1899600728
Short name	T396
Test name
Test status
Simulation time	385861300 ps
CPU time	82.93 seconds
Started	Oct 15 08:35:44 AM UTC 24
Finished	Oct 15 08:37:08 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899600728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1899600728
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.3521536660
Short name	T447
Test name
Test status
Simulation time	1002233400 ps
CPU time	63.27 seconds
Started	Oct 15 08:33:49 AM UTC 24
Finished	Oct 15 08:34:54 AM UTC 24
Peak memory	275140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352 1536660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser r_address.3521536660
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3591437066
Short name	T209
Test name
Test status
Simulation time	455050400 ps
CPU time	79.88 seconds
Started	Oct 15 08:33:38 AM UTC 24
Finished	Oct 15 08:35:00 AM UTC 24
Peak memory	275140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 91437066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se rr_counter.3591437066
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.636276878
Short name	T320
Test name
Test status
Simulation time	99959200 ps
CPU time	122.62 seconds
Started	Oct 15 08:31:22 AM UTC 24
Finished	Oct 15 08:33:27 AM UTC 24
Peak memory	287188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636276878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.636276878
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.2151325336
Short name	T440
Test name
Test status
Simulation time	54598800 ps
CPU time	48.23 seconds
Started	Oct 15 08:31:25 AM UTC 24
Finished	Oct 15 08:32:15 AM UTC 24
Peak memory	270688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151325336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2151325336
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2381443346
Short name	T556
Test name
Test status
Simulation time	3316179100 ps
CPU time	1281.48 seconds
Started	Oct 15 08:36:03 AM UTC 24
Finished	Oct 15 08:57:38 AM UTC 24
Peak memory	291232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381443346 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.2381443346
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.1098018351
Short name	T441
Test name
Test status
Simulation time	87499200 ps
CPU time	48.11 seconds
Started	Oct 15 08:31:28 AM UTC 24
Finished	Oct 15 08:32:18 AM UTC 24
Peak memory	272736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098018351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1098018351
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3330490115
Short name	T452
Test name
Test status
Simulation time	5299198100 ps
CPU time	192.56 seconds
Started	Oct 15 08:32:49 AM UTC 24
Finished	Oct 15 08:36:05 AM UTC 24
Peak memory	270928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3330490115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.3330490115
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.233669712
Short name	T872
Test name
Test status
Simulation time	116989100 ps
CPU time	25.07 seconds
Started	Oct 15 09:28:22 AM UTC 24
Finished	Oct 15 09:28:49 AM UTC 24
Peak memory	268812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233669712 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.233669712
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.4222822448
Short name	T870
Test name
Test status
Simulation time	62173900 ps
CPU time	26 seconds
Started	Oct 15 09:28:20 AM UTC 24
Finished	Oct 15 09:28:47 AM UTC 24
Peak memory	284764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222822448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.4222822448
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.367129059
Short name	T881
Test name
Test status
Simulation time	8567801700 ps
CPU time	73.66 seconds
Started	Oct 15 09:28:03 AM UTC 24
Finished	Oct 15 09:29:19 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367129059 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.367129059
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.1473275667
Short name	T902
Test name
Test status
Simulation time	2252848700 ps
CPU time	125.92 seconds
Started	Oct 15 09:28:05 AM UTC 24
Finished	Oct 15 09:30:14 AM UTC 24
Peak memory	305856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473275667 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.1473275667
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.14646110
Short name	T909
Test name
Test status
Simulation time	5833154200 ps
CPU time	139.79 seconds
Started	Oct 15 09:28:08 AM UTC 24
Finished	Oct 15 09:30:30 AM UTC 24
Peak memory	303868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=14646110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.flash_ctrl_intr_rd_slow_flash.14646110
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.2344997062
Short name	T910
Test name
Test status
Simulation time	39759800 ps
CPU time	142.29 seconds
Started	Oct 15 09:28:05 AM UTC 24
Finished	Oct 15 09:30:30 AM UTC 24
Peak memory	271116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344997062 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.2344997062
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.1519693030
Short name	T876
Test name
Test status
Simulation time	43318300 ps
CPU time	49.74 seconds
Started	Oct 15 09:28:14 AM UTC 24
Finished	Oct 15 09:29:05 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519693030 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.1519693030
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.2878669855
Short name	T873
Test name
Test status
Simulation time	74784700 ps
CPU time	34.43 seconds
Started	Oct 15 09:28:15 AM UTC 24
Finished	Oct 15 09:28:51 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2878669855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_rw_evict_all_en.2878669855
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.190486590
Short name	T884
Test name
Test status
Simulation time	1520578700 ps
CPU time	63.11 seconds
Started	Oct 15 09:28:17 AM UTC 24
Finished	Oct 15 09:29:22 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190486590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.190486590
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.3042159516
Short name	T897
Test name
Test status
Simulation time	55138900 ps
CPU time	120.63 seconds
Started	Oct 15 09:27:57 AM UTC 24
Finished	Oct 15 09:30:00 AM UTC 24
Peak memory	287192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042159516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3042159516
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.1346299787
Short name	T880
Test name
Test status
Simulation time	112868200 ps
CPU time	26.11 seconds
Started	Oct 15 09:28:49 AM UTC 24
Finished	Oct 15 09:29:16 AM UTC 24
Peak memory	268932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346299787 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.1346299787
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.925861067
Short name	T878
Test name
Test status
Simulation time	108418800 ps
CPU time	22.61 seconds
Started	Oct 15 09:28:45 AM UTC 24
Finished	Oct 15 09:29:08 AM UTC 24
Peak memory	284768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925861067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.925861067
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.2328995268
Short name	T393
Test name
Test status
Simulation time	13339200 ps
CPU time	41.36 seconds
Started	Oct 15 09:28:40 AM UTC 24
Finished	Oct 15 09:29:23 AM UTC 24
Peak memory	285316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2328995268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ ctrl_disable.2328995268
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.451489573
Short name	T905
Test name
Test status
Simulation time	1775777800 ps
CPU time	116.46 seconds
Started	Oct 15 09:28:23 AM UTC 24
Finished	Oct 15 09:30:22 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451489573 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.451489573
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.1968247108
Short name	T906
Test name
Test status
Simulation time	1564842500 ps
CPU time	119.54 seconds
Started	Oct 15 09:28:25 AM UTC 24
Finished	Oct 15 09:30:27 AM UTC 24
Peak memory	301692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968247108 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.1968247108
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2560951950
Short name	T915
Test name
Test status
Simulation time	15679036000 ps
CPU time	137.68 seconds
Started	Oct 15 09:28:27 AM UTC 24
Finished	Oct 15 09:30:47 AM UTC 24
Peak memory	303692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2560951950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.flash_ctrl_intr_rd_slow_flash.2560951950
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.2647759271
Short name	T918
Test name
Test status
Simulation time	40501300 ps
CPU time	147.72 seconds
Started	Oct 15 09:28:24 AM UTC 24
Finished	Oct 15 09:30:54 AM UTC 24
Peak memory	271244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647759271 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.2647759271
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.2949250678
Short name	T879
Test name
Test status
Simulation time	29340200 ps
CPU time	36.53 seconds
Started	Oct 15 09:28:31 AM UTC 24
Finished	Oct 15 09:29:09 AM UTC 24
Peak memory	287564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949250678 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.2949250678
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.2889239178
Short name	T886
Test name
Test status
Simulation time	29026200 ps
CPU time	45.15 seconds
Started	Oct 15 09:28:38 AM UTC 24
Finished	Oct 15 09:29:25 AM UTC 24
Peak memory	285412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2889239178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c trl_rw_evict_all_en.2889239178
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.4024551362
Short name	T894
Test name
Test status
Simulation time	1961597000 ps
CPU time	72.9 seconds
Started	Oct 15 09:28:43 AM UTC 24
Finished	Oct 15 09:29:58 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024551362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.4024551362
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.3065811371
Short name	T925
Test name
Test status
Simulation time	34223800 ps
CPU time	163.51 seconds
Started	Oct 15 09:28:22 AM UTC 24
Finished	Oct 15 09:31:09 AM UTC 24
Peak memory	287312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065811371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3065811371
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.2067874299
Short name	T888
Test name
Test status
Simulation time	76805400 ps
CPU time	16.12 seconds
Started	Oct 15 09:29:16 AM UTC 24
Finished	Oct 15 09:29:33 AM UTC 24
Peak memory	268816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067874299 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.2067874299
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.2852904660
Short name	T889
Test name
Test status
Simulation time	51728900 ps
CPU time	29.33 seconds
Started	Oct 15 09:29:10 AM UTC 24
Finished	Oct 15 09:29:40 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852904660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2852904660
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.2440988936
Short name	T895
Test name
Test status
Simulation time	3454535700 ps
CPU time	68.63 seconds
Started	Oct 15 09:28:50 AM UTC 24
Finished	Oct 15 09:30:00 AM UTC 24
Peak memory	274980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440988936 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.2440988936
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.2656263881
Short name	T975
Test name
Test status
Simulation time	13360028400 ps
CPU time	255.83 seconds
Started	Oct 15 09:28:59 AM UTC 24
Finished	Oct 15 09:33:19 AM UTC 24
Peak memory	293532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656263881 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.2656263881
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1923710122
Short name	T1048
Test name
Test status
Simulation time	12103237000 ps
CPU time	377.8 seconds
Started	Oct 15 09:29:05 AM UTC 24
Finished	Oct 15 09:35:28 AM UTC 24
Peak memory	301620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1923710122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.flash_ctrl_intr_rd_slow_flash.1923710122
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2112748961
Short name	T933
Test name
Test status
Simulation time	37897900 ps
CPU time	163.33 seconds
Started	Oct 15 09:28:51 AM UTC 24
Finished	Oct 15 09:31:37 AM UTC 24
Peak memory	271116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112748961 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.2112748961
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.168966713
Short name	T890
Test name
Test status
Simulation time	244984200 ps
CPU time	40.55 seconds
Started	Oct 15 09:29:06 AM UTC 24
Finished	Oct 15 09:29:48 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168966713 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.168966713
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2102380943
Short name	T891
Test name
Test status
Simulation time	38378400 ps
CPU time	39.6 seconds
Started	Oct 15 09:29:09 AM UTC 24
Finished	Oct 15 09:29:49 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2102380943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_rw_evict_all_en.2102380943
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.3391505151
Short name	T903
Test name
Test status
Simulation time	2248160000 ps
CPU time	64.68 seconds
Started	Oct 15 09:29:10 AM UTC 24
Finished	Oct 15 09:30:16 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391505151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3391505151
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.3229123185
Short name	T945
Test name
Test status
Simulation time	50045100 ps
CPU time	189.2 seconds
Started	Oct 15 09:28:49 AM UTC 24
Finished	Oct 15 09:32:01 AM UTC 24
Peak memory	287192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229123185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3229123185
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.3176743701
Short name	T899
Test name
Test status
Simulation time	76817300 ps
CPU time	18.4 seconds
Started	Oct 15 09:29:41 AM UTC 24
Finished	Oct 15 09:30:01 AM UTC 24
Peak memory	268816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176743701 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.3176743701
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.2330395322
Short name	T893
Test name
Test status
Simulation time	13956200 ps
CPU time	18.96 seconds
Started	Oct 15 09:29:34 AM UTC 24
Finished	Oct 15 09:29:54 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330395322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2330395322
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.4196620384
Short name	T896
Test name
Test status
Simulation time	43965600 ps
CPU time	32.82 seconds
Started	Oct 15 09:29:26 AM UTC 24
Finished	Oct 15 09:30:00 AM UTC 24
Peak memory	285468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4196620384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ ctrl_disable.4196620384
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.1906502349
Short name	T934
Test name
Test status
Simulation time	3575233900 ps
CPU time	138.93 seconds
Started	Oct 15 09:29:19 AM UTC 24
Finished	Oct 15 09:31:41 AM UTC 24
Peak memory	274856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906502349 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.1906502349
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.454739747
Short name	T979
Test name
Test status
Simulation time	1678368300 ps
CPU time	243.07 seconds
Started	Oct 15 09:29:22 AM UTC 24
Finished	Oct 15 09:33:28 AM UTC 24
Peak memory	301716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454739747 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.454739747
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.453283211
Short name	T947
Test name
Test status
Simulation time	23405232700 ps
CPU time	159.68 seconds
Started	Oct 15 09:29:23 AM UTC 24
Finished	Oct 15 09:32:05 AM UTC 24
Peak memory	301620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=453283211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 33.flash_ctrl_intr_rd_slow_flash.453283211
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.3077110474
Short name	T949
Test name
Test status
Simulation time	71332000 ps
CPU time	170.27 seconds
Started	Oct 15 09:29:20 AM UTC 24
Finished	Oct 15 09:32:13 AM UTC 24
Peak memory	270908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077110474 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.3077110474
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2652412697
Short name	T898
Test name
Test status
Simulation time	28308700 ps
CPU time	34.81 seconds
Started	Oct 15 09:29:24 AM UTC 24
Finished	Oct 15 09:30:00 AM UTC 24
Peak memory	285412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652412697 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.2652412697
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.623654697
Short name	T900
Test name
Test status
Simulation time	69160300 ps
CPU time	39.69 seconds
Started	Oct 15 09:29:24 AM UTC 24
Finished	Oct 15 09:30:05 AM UTC 24
Peak memory	287428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=623654697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ct rl_rw_evict_all_en.623654697
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.543447677
Short name	T919
Test name
Test status
Simulation time	2138662100 ps
CPU time	83.13 seconds
Started	Oct 15 09:29:31 AM UTC 24
Finished	Oct 15 09:30:56 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543447677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.543447677
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.1943477328
Short name	T965
Test name
Test status
Simulation time	49086300 ps
CPU time	213.24 seconds
Started	Oct 15 09:29:17 AM UTC 24
Finished	Oct 15 09:32:54 AM UTC 24
Peak memory	291280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943477328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1943477328
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.775187383
Short name	T904
Test name
Test status
Simulation time	146166500 ps
CPU time	18.47 seconds
Started	Oct 15 09:30:03 AM UTC 24
Finished	Oct 15 09:30:22 AM UTC 24
Peak memory	270852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775187383 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.775187383
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.3497094146
Short name	T907
Test name
Test status
Simulation time	90962300 ps
CPU time	25.21 seconds
Started	Oct 15 09:30:01 AM UTC 24
Finished	Oct 15 09:30:28 AM UTC 24
Peak memory	292408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497094146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3497094146
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.2319498870
Short name	T908
Test name
Test status
Simulation time	25079000 ps
CPU time	25.52 seconds
Started	Oct 15 09:30:01 AM UTC 24
Finished	Oct 15 09:30:28 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2319498870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ ctrl_disable.2319498870
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.995056421
Short name	T938
Test name
Test status
Simulation time	3164951100 ps
CPU time	115.82 seconds
Started	Oct 15 09:29:50 AM UTC 24
Finished	Oct 15 09:31:48 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995056421 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.995056421
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.2642092934
Short name	T944
Test name
Test status
Simulation time	3277271300 ps
CPU time	123.44 seconds
Started	Oct 15 09:29:53 AM UTC 24
Finished	Oct 15 09:31:58 AM UTC 24
Peak memory	301788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642092934 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.2642092934
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3849426034
Short name	T1022
Test name
Test status
Simulation time	12899629300 ps
CPU time	296.87 seconds
Started	Oct 15 09:29:55 AM UTC 24
Finished	Oct 15 09:34:56 AM UTC 24
Peak memory	301752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3849426034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.flash_ctrl_intr_rd_slow_flash.3849426034
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.659031181
Short name	T958
Test name
Test status
Simulation time	464273000 ps
CPU time	163.52 seconds
Started	Oct 15 09:29:51 AM UTC 24
Finished	Oct 15 09:32:37 AM UTC 24
Peak memory	270984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659031181 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.659031181
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.462454213
Short name	T916
Test name
Test status
Simulation time	114069800 ps
CPU time	50.33 seconds
Started	Oct 15 09:29:59 AM UTC 24
Finished	Oct 15 09:30:51 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462454213 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.462454213
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.3714919486
Short name	T914
Test name
Test status
Simulation time	97093600 ps
CPU time	38.39 seconds
Started	Oct 15 09:30:01 AM UTC 24
Finished	Oct 15 09:30:41 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3714919486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_rw_evict_all_en.3714919486
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.3194774470
Short name	T928
Test name
Test status
Simulation time	1366259500 ps
CPU time	78.07 seconds
Started	Oct 15 09:30:01 AM UTC 24
Finished	Oct 15 09:31:21 AM UTC 24
Peak memory	272876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194774470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3194774470
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1356037415
Short name	T962
Test name
Test status
Simulation time	626953400 ps
CPU time	181.42 seconds
Started	Oct 15 09:29:45 AM UTC 24
Finished	Oct 15 09:32:50 AM UTC 24
Peak memory	287380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356037415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1356037415
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.577548967
Short name	T920
Test name
Test status
Simulation time	98794600 ps
CPU time	25.76 seconds
Started	Oct 15 09:30:31 AM UTC 24
Finished	Oct 15 09:30:58 AM UTC 24
Peak memory	268796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577548967 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.577548967
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.3066271736
Short name	T917
Test name
Test status
Simulation time	39131700 ps
CPU time	20.77 seconds
Started	Oct 15 09:30:31 AM UTC 24
Finished	Oct 15 09:30:53 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066271736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3066271736
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.4019922260
Short name	T417
Test name
Test status
Simulation time	63477400 ps
CPU time	30.81 seconds
Started	Oct 15 09:30:29 AM UTC 24
Finished	Oct 15 09:31:01 AM UTC 24
Peak memory	285340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4019922260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ ctrl_disable.4019922260
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.155754886
Short name	T930
Test name
Test status
Simulation time	1599511200 ps
CPU time	72.95 seconds
Started	Oct 15 09:30:13 AM UTC 24
Finished	Oct 15 09:31:28 AM UTC 24
Peak memory	272800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155754886 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.155754886
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.192401304
Short name	T986
Test name
Test status
Simulation time	3581150200 ps
CPU time	199.14 seconds
Started	Oct 15 09:30:17 AM UTC 24
Finished	Oct 15 09:33:39 AM UTC 24
Peak memory	301696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192401304 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.192401304
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.504521743
Short name	T995
Test name
Test status
Simulation time	38087604300 ps
CPU time	209.12 seconds
Started	Oct 15 09:30:23 AM UTC 24
Finished	Oct 15 09:33:56 AM UTC 24
Peak memory	301408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=504521743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 35.flash_ctrl_intr_rd_slow_flash.504521743
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.1252527859
Short name	T983
Test name
Test status
Simulation time	72578500 ps
CPU time	197.55 seconds
Started	Oct 15 09:30:14 AM UTC 24
Finished	Oct 15 09:33:35 AM UTC 24
Peak memory	268776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252527859 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.1252527859
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3039822280
Short name	T924
Test name
Test status
Simulation time	76578300 ps
CPU time	38.47 seconds
Started	Oct 15 09:30:27 AM UTC 24
Finished	Oct 15 09:31:07 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3039822280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c trl_rw_evict_all_en.3039822280
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.3146088384
Short name	T943
Test name
Test status
Simulation time	5152931500 ps
CPU time	81.63 seconds
Started	Oct 15 09:30:29 AM UTC 24
Finished	Oct 15 09:31:52 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146088384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3146088384
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.210429354
Short name	T997
Test name
Test status
Simulation time	231799800 ps
CPU time	228.61 seconds
Started	Oct 15 09:30:07 AM UTC 24
Finished	Oct 15 09:33:58 AM UTC 24
Peak memory	289236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210429354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.210429354
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.1045560502
Short name	T931
Test name
Test status
Simulation time	72112400 ps
CPU time	27.29 seconds
Started	Oct 15 09:30:59 AM UTC 24
Finished	Oct 15 09:31:28 AM UTC 24
Peak memory	274944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045560502 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.1045560502
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.2596533236
Short name	T929
Test name
Test status
Simulation time	15660300 ps
CPU time	25.21 seconds
Started	Oct 15 09:30:59 AM UTC 24
Finished	Oct 15 09:31:26 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596533236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2596533236
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.1867510084
Short name	T932
Test name
Test status
Simulation time	11678200 ps
CPU time	32.28 seconds
Started	Oct 15 09:30:55 AM UTC 24
Finished	Oct 15 09:31:29 AM UTC 24
Peak memory	285316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1867510084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ ctrl_disable.1867510084
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.3810154875
Short name	T964
Test name
Test status
Simulation time	6790493000 ps
CPU time	135.21 seconds
Started	Oct 15 09:30:34 AM UTC 24
Finished	Oct 15 09:32:52 AM UTC 24
Peak memory	274984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810154875 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.3810154875
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.1703755619
Short name	T984
Test name
Test status
Simulation time	2803146200 ps
CPU time	171.02 seconds
Started	Oct 15 09:30:41 AM UTC 24
Finished	Oct 15 09:33:35 AM UTC 24
Peak memory	301692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703755619 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.1703755619
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1198293355
Short name	T971
Test name
Test status
Simulation time	5830131200 ps
CPU time	138.84 seconds
Started	Oct 15 09:30:48 AM UTC 24
Finished	Oct 15 09:33:09 AM UTC 24
Peak memory	303364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1198293355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.flash_ctrl_intr_rd_slow_flash.1198293355
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.281523169
Short name	T970
Test name
Test status
Simulation time	41687500 ps
CPU time	148.67 seconds
Started	Oct 15 09:30:36 AM UTC 24
Finished	Oct 15 09:33:08 AM UTC 24
Peak memory	270960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281523169 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.281523169
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.1328605297
Short name	T936
Test name
Test status
Simulation time	170349200 ps
CPU time	50.81 seconds
Started	Oct 15 09:30:52 AM UTC 24
Finished	Oct 15 09:31:44 AM UTC 24
Peak memory	287436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328605297 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.1328605297
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.2667475606
Short name	T939
Test name
Test status
Simulation time	39020000 ps
CPU time	53.51 seconds
Started	Oct 15 09:30:54 AM UTC 24
Finished	Oct 15 09:31:49 AM UTC 24
Peak memory	287652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2667475606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c trl_rw_evict_all_en.2667475606
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.162579004
Short name	T956
Test name
Test status
Simulation time	9260050000 ps
CPU time	92.08 seconds
Started	Oct 15 09:30:57 AM UTC 24
Finished	Oct 15 09:32:31 AM UTC 24
Peak memory	272872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162579004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.162579004
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.2234061183
Short name	T1007
Test name
Test status
Simulation time	77595300 ps
CPU time	224.63 seconds
Started	Oct 15 09:30:31 AM UTC 24
Finished	Oct 15 09:34:19 AM UTC 24
Peak memory	289296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234061183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2234061183
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.442651598
Short name	T940
Test name
Test status
Simulation time	25945000 ps
CPU time	19 seconds
Started	Oct 15 09:31:29 AM UTC 24
Finished	Oct 15 09:31:49 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442651598 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.442651598
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.2840460665
Short name	T941
Test name
Test status
Simulation time	12773600 ps
CPU time	22.6 seconds
Started	Oct 15 09:31:27 AM UTC 24
Finished	Oct 15 09:31:51 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840460665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2840460665
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.3880242096
Short name	T937
Test name
Test status
Simulation time	10089900 ps
CPU time	28.45 seconds
Started	Oct 15 09:31:15 AM UTC 24
Finished	Oct 15 09:31:45 AM UTC 24
Peak memory	283264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3880242096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ ctrl_disable.3880242096
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.4000786066
Short name	T953
Test name
Test status
Simulation time	3709244500 ps
CPU time	79.42 seconds
Started	Oct 15 09:31:02 AM UTC 24
Finished	Oct 15 09:32:23 AM UTC 24
Peak memory	272804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000786066 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.4000786066
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.1968686573
Short name	T974
Test name
Test status
Simulation time	542807900 ps
CPU time	124.4 seconds
Started	Oct 15 09:31:08 AM UTC 24
Finished	Oct 15 09:33:15 AM UTC 24
Peak memory	293632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968686573 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.1968686573
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1551799765
Short name	T992
Test name
Test status
Simulation time	11856089000 ps
CPU time	158.76 seconds
Started	Oct 15 09:31:10 AM UTC 24
Finished	Oct 15 09:33:51 AM UTC 24
Peak memory	303668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1551799765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.flash_ctrl_intr_rd_slow_flash.1551799765
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.489296573
Short name	T998
Test name
Test status
Simulation time	472713600 ps
CPU time	173.14 seconds
Started	Oct 15 09:31:04 AM UTC 24
Finished	Oct 15 09:34:00 AM UTC 24
Peak memory	275016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489296573 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.489296573
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.1806295432
Short name	T946
Test name
Test status
Simulation time	28770800 ps
CPU time	49.65 seconds
Started	Oct 15 09:31:10 AM UTC 24
Finished	Oct 15 09:32:01 AM UTC 24
Peak memory	285380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806295432 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.1806295432
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.1285823757
Short name	T951
Test name
Test status
Simulation time	27513100 ps
CPU time	61.11 seconds
Started	Oct 15 09:31:11 AM UTC 24
Finished	Oct 15 09:32:14 AM UTC 24
Peak memory	287452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1285823757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c trl_rw_evict_all_en.1285823757
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.2491873416
Short name	T954
Test name
Test status
Simulation time	1672602800 ps
CPU time	66.79 seconds
Started	Oct 15 09:31:22 AM UTC 24
Finished	Oct 15 09:32:31 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491873416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2491873416
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.3882852122
Short name	T1006
Test name
Test status
Simulation time	37206100 ps
CPU time	195.67 seconds
Started	Oct 15 09:30:59 AM UTC 24
Finished	Oct 15 09:34:18 AM UTC 24
Peak memory	289432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882852122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3882852122
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.3501034936
Short name	T950
Test name
Test status
Simulation time	39902000 ps
CPU time	20.5 seconds
Started	Oct 15 09:31:52 AM UTC 24
Finished	Oct 15 09:32:14 AM UTC 24
Peak memory	275092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501034936 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.3501034936
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.509904095
Short name	T952
Test name
Test status
Simulation time	25290500 ps
CPU time	29.25 seconds
Started	Oct 15 09:31:50 AM UTC 24
Finished	Oct 15 09:32:20 AM UTC 24
Peak memory	284704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509904095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.509904095
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.2661692258
Short name	T390
Test name
Test status
Simulation time	10009600 ps
CPU time	33.19 seconds
Started	Oct 15 09:31:49 AM UTC 24
Finished	Oct 15 09:32:23 AM UTC 24
Peak memory	285372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2661692258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ ctrl_disable.2661692258
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.677042329
Short name	T1005
Test name
Test status
Simulation time	21578603600 ps
CPU time	164.07 seconds
Started	Oct 15 09:31:30 AM UTC 24
Finished	Oct 15 09:34:17 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677042329 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.677042329
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.3885184719
Short name	T1030
Test name
Test status
Simulation time	1784396000 ps
CPU time	199.22 seconds
Started	Oct 15 09:31:41 AM UTC 24
Finished	Oct 15 09:35:03 AM UTC 24
Peak memory	301724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885184719 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.3885184719
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1081768298
Short name	T1001
Test name
Test status
Simulation time	15281023300 ps
CPU time	143.12 seconds
Started	Oct 15 09:31:41 AM UTC 24
Finished	Oct 15 09:34:07 AM UTC 24
Peak memory	303668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1081768298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.flash_ctrl_intr_rd_slow_flash.1081768298
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.1533526944
Short name	T1025
Test name
Test status
Simulation time	139244500 ps
CPU time	197.24 seconds
Started	Oct 15 09:31:38 AM UTC 24
Finished	Oct 15 09:34:58 AM UTC 24
Peak memory	270712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533526944 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.1533526944
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.3469679765
Short name	T957
Test name
Test status
Simulation time	104614300 ps
CPU time	44.51 seconds
Started	Oct 15 09:31:46 AM UTC 24
Finished	Oct 15 09:32:32 AM UTC 24
Peak memory	285416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469679765 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.3469679765
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.288732489
Short name	T955
Test name
Test status
Simulation time	68608800 ps
CPU time	44.1 seconds
Started	Oct 15 09:31:46 AM UTC 24
Finished	Oct 15 09:32:31 AM UTC 24
Peak memory	285380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=288732489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ct rl_rw_evict_all_en.288732489
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.3557494078
Short name	T1055
Test name
Test status
Simulation time	160149200 ps
CPU time	246.43 seconds
Started	Oct 15 09:31:29 AM UTC 24
Finished	Oct 15 09:35:39 AM UTC 24
Peak memory	287320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557494078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3557494078
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.3948963749
Short name	T963
Test name
Test status
Simulation time	207259600 ps
CPU time	28.82 seconds
Started	Oct 15 09:32:21 AM UTC 24
Finished	Oct 15 09:32:52 AM UTC 24
Peak memory	272900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948963749 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.3948963749
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.2824383599
Short name	T959
Test name
Test status
Simulation time	14093800 ps
CPU time	25.12 seconds
Started	Oct 15 09:32:15 AM UTC 24
Finished	Oct 15 09:32:42 AM UTC 24
Peak memory	295004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824383599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2824383599
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.287482518
Short name	T961
Test name
Test status
Simulation time	14462400 ps
CPU time	26.79 seconds
Started	Oct 15 09:32:14 AM UTC 24
Finished	Oct 15 09:32:42 AM UTC 24
Peak memory	285312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=287482518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c trl_disable.287482518
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.3359504511
Short name	T1014
Test name
Test status
Simulation time	15618600600 ps
CPU time	160.43 seconds
Started	Oct 15 09:31:53 AM UTC 24
Finished	Oct 15 09:34:37 AM UTC 24
Peak memory	275040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359504511 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.3359504511
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.3508232251
Short name	T1067
Test name
Test status
Simulation time	1724552600 ps
CPU time	230.44 seconds
Started	Oct 15 09:32:02 AM UTC 24
Finished	Oct 15 09:35:55 AM UTC 24
Peak memory	293500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508232251 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.3508232251
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2139660977
Short name	T1020
Test name
Test status
Simulation time	24872837500 ps
CPU time	164.28 seconds
Started	Oct 15 09:32:03 AM UTC 24
Finished	Oct 15 09:34:50 AM UTC 24
Peak memory	305804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2139660977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.flash_ctrl_intr_rd_slow_flash.2139660977
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.940159468
Short name	T1033
Test name
Test status
Simulation time	132819000 ps
CPU time	186.71 seconds
Started	Oct 15 09:31:59 AM UTC 24
Finished	Oct 15 09:35:09 AM UTC 24
Peak memory	271108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940159468 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.940159468
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.3022487507
Short name	T966
Test name
Test status
Simulation time	31447400 ps
CPU time	48.76 seconds
Started	Oct 15 09:32:06 AM UTC 24
Finished	Oct 15 09:32:56 AM UTC 24
Peak memory	287496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022487507 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.3022487507
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.2070802938
Short name	T322
Test name
Test status
Simulation time	29770000 ps
CPU time	44.56 seconds
Started	Oct 15 09:32:12 AM UTC 24
Finished	Oct 15 09:32:58 AM UTC 24
Peak memory	285404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2070802938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c trl_rw_evict_all_en.2070802938
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.245778439
Short name	T432
Test name
Test status
Simulation time	3585450000 ps
CPU time	75.7 seconds
Started	Oct 15 09:32:14 AM UTC 24
Finished	Oct 15 09:33:32 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245778439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.245778439
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.3682999305
Short name	T967
Test name
Test status
Simulation time	22116300 ps
CPU time	61.29 seconds
Started	Oct 15 09:31:53 AM UTC 24
Finished	Oct 15 09:32:56 AM UTC 24
Peak memory	285136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682999305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3682999305
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.515666209
Short name	T481
Test name
Test status
Simulation time	177549200 ps
CPU time	29.49 seconds
Started	Oct 15 08:41:42 AM UTC 24
Finished	Oct 15 08:42:13 AM UTC 24
Peak memory	274940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515666209 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.515666209
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3693939414
Short name	T475
Test name
Test status
Simulation time	26284400 ps
CPU time	22.94 seconds
Started	Oct 15 08:41:24 AM UTC 24
Finished	Oct 15 08:41:48 AM UTC 24
Peak memory	272828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693939414 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.3693939414
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3650331592
Short name	T474
Test name
Test status
Simulation time	14414900 ps
CPU time	20.13 seconds
Started	Oct 15 08:41:07 AM UTC 24
Finished	Oct 15 08:41:28 AM UTC 24
Peak memory	284764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650331592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3650331592
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.1752049784
Short name	T484
Test name
Test status
Simulation time	3135878300 ps
CPU time	228.05 seconds
Started	Oct 15 08:39:26 AM UTC 24
Finished	Oct 15 08:43:18 AM UTC 24
Peak memory	289488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1752049784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.1752049784
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2017804443
Short name	T107
Test name
Test status
Simulation time	20477700 ps
CPU time	32.12 seconds
Started	Oct 15 08:40:32 AM UTC 24
Finished	Oct 15 08:41:06 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2017804443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_disable.2017804443
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2460917654
Short name	T506
Test name
Test status
Simulation time	33371616400 ps
CPU time	686.56 seconds
Started	Oct 15 08:36:56 AM UTC 24
Finished	Oct 15 08:48:30 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460917654 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2460917654
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.2847302561
Short name	T838
Test name
Test status
Simulation time	14002639200 ps
CPU time	2952.55 seconds
Started	Oct 15 08:37:27 AM UTC 24
Finished	Oct 15 09:27:11 AM UTC 24
Peak memory	277688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847302561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.2847302561
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.94208826
Short name	T1060
Test name
Test status
Simulation time	1393042100 ps
CPU time	3471.63 seconds
Started	Oct 15 08:37:21 AM UTC 24
Finished	Oct 15 09:35:49 AM UTC 24
Peak memory	277744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94 208826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_e rror_prog_type.94208826
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.4261767535
Short name	T566
Test name
Test status
Simulation time	817000400 ps
CPU time	1347.12 seconds
Started	Oct 15 08:37:26 AM UTC 24
Finished	Oct 15 09:00:08 AM UTC 24
Peak memory	283108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261767535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.4261767535
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2433604477
Short name	T66
Test name
Test status
Simulation time	790839900 ps
CPU time	32.3 seconds
Started	Oct 15 08:37:14 AM UTC 24
Finished	Oct 15 08:37:47 AM UTC 24
Peak memory	272852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 33604477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc h_code.2433604477
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.1707365881
Short name	T721
Test name
Test status
Simulation time	350770913000 ps
CPU time	2456.67 seconds
Started	Oct 15 08:37:16 AM UTC 24
Finished	Oct 15 09:18:40 AM UTC 24
Peak memory	277840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707365881 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.1707365881
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3890171274
Short name	T809
Test name
Test status
Simulation time	252242189700 ps
CPU time	2879.78 seconds
Started	Oct 15 08:37:09 AM UTC 24
Finished	Oct 15 09:25:40 AM UTC 24
Peak memory	277744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890171274 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.3890171274
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.3138630798
Short name	T461
Test name
Test status
Simulation time	221419400 ps
CPU time	97.01 seconds
Started	Oct 15 08:36:41 AM UTC 24
Finished	Oct 15 08:38:20 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138630798 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3138630798
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.569569625
Short name	T288
Test name
Test status
Simulation time	10044830400 ps
CPU time	78.54 seconds
Started	Oct 15 08:41:36 AM UTC 24
Finished	Oct 15 08:42:56 AM UTC 24
Peak memory	275296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=569569625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.569569625
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.3378182406
Short name	T477
Test name
Test status
Simulation time	47318700 ps
CPU time	23.98 seconds
Started	Oct 15 08:41:34 AM UTC 24
Finished	Oct 15 08:41:59 AM UTC 24
Peak memory	271128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3378182406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3378182406
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3978003532
Short name	T198
Test name
Test status
Simulation time	160188500000 ps
CPU time	924.55 seconds
Started	Oct 15 08:37:00 AM UTC 24
Finished	Oct 15 08:52:35 AM UTC 24
Peak memory	274744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978003532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.3978003532
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.3468369184
Short name	T316
Test name
Test status
Simulation time	3309035200 ps
CPU time	124.06 seconds
Started	Oct 15 08:36:50 AM UTC 24
Finished	Oct 15 08:38:56 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468369184 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.3468369184
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.3201830160
Short name	T345
Test name
Test status
Simulation time	6557928100 ps
CPU time	210.34 seconds
Started	Oct 15 08:39:56 AM UTC 24
Finished	Oct 15 08:43:29 AM UTC 24
Peak memory	293696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201830160 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.3201830160
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1838616158
Short name	T339
Test name
Test status
Simulation time	12717664200 ps
CPU time	486.87 seconds
Started	Oct 15 08:40:06 AM UTC 24
Finished	Oct 15 08:48:19 AM UTC 24
Peak memory	303676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1838616158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_intr_rd_slow_flash.1838616158
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.2144879748
Short name	T406
Test name
Test status
Simulation time	9836136400 ps
CPU time	72.91 seconds
Started	Oct 15 08:39:56 AM UTC 24
Finished	Oct 15 08:41:10 AM UTC 24
Peak memory	275092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144879748 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.2144879748
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3498415593
Short name	T463
Test name
Test status
Simulation time	5594343700 ps
CPU time	84.76 seconds
Started	Oct 15 08:37:32 AM UTC 24
Finished	Oct 15 08:38:58 AM UTC 24
Peak memory	275088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498415593 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3498415593
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2122752215
Short name	T290
Test name
Test status
Simulation time	15477100 ps
CPU time	28.26 seconds
Started	Oct 15 08:41:29 AM UTC 24
Finished	Oct 15 08:41:58 AM UTC 24
Peak memory	270872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2122752215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_lcmgr_intg.2122752215
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.647323858
Short name	T159
Test name
Test status
Simulation time	36291463100 ps
CPU time	232.45 seconds
Started	Oct 15 08:37:13 AM UTC 24
Finished	Oct 15 08:41:09 AM UTC 24
Peak memory	283144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=647323858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_mp_regions.647323858
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.3026449759
Short name	T191
Test name
Test status
Simulation time	147358300 ps
CPU time	170.79 seconds
Started	Oct 15 08:37:01 AM UTC 24
Finished	Oct 15 08:39:55 AM UTC 24
Peak memory	273096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026449759 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.3026449759
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.1401348823
Short name	T482
Test name
Test status
Simulation time	4387415100 ps
CPU time	153.23 seconds
Started	Oct 15 08:39:46 AM UTC 24
Finished	Oct 15 08:42:22 AM UTC 24
Peak memory	305852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1401348823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.1401348823
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2884216458
Short name	T240
Test name
Test status
Simulation time	44822700 ps
CPU time	23.83 seconds
Started	Oct 15 08:41:21 AM UTC 24
Finished	Oct 15 08:41:46 AM UTC 24
Peak memory	275400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884216458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2884216458
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1379167353
Short name	T257
Test name
Test status
Simulation time	2838350000 ps
CPU time	183.49 seconds
Started	Oct 15 08:36:48 AM UTC 24
Finished	Oct 15 08:39:54 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379167353 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1379167353
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.765632522
Short name	T470
Test name
Test status
Simulation time	54710200 ps
CPU time	19.36 seconds
Started	Oct 15 08:40:10 AM UTC 24
Finished	Oct 15 08:40:31 AM UTC 24
Peak memory	270940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765632522 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.765632522
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.2450027763
Short name	T480
Test name
Test status
Simulation time	386581400 ps
CPU time	327.99 seconds
Started	Oct 15 08:36:39 AM UTC 24
Finished	Oct 15 08:42:11 AM UTC 24
Peak memory	280908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450027763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2450027763
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1459983071
Short name	T280
Test name
Test status
Simulation time	87519500 ps
CPU time	127.79 seconds
Started	Oct 15 08:36:47 AM UTC 24
Finished	Oct 15 08:38:57 AM UTC 24
Peak memory	272844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459983071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1459983071
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2385836054
Short name	T354
Test name
Test status
Simulation time	61266200 ps
CPU time	50.63 seconds
Started	Oct 15 08:40:30 AM UTC 24
Finished	Oct 15 08:41:23 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385836054 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.2385836054
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.1406765014
Short name	T465
Test name
Test status
Simulation time	32260400 ps
CPU time	24.82 seconds
Started	Oct 15 08:38:59 AM UTC 24
Finished	Oct 15 08:39:25 AM UTC 24
Peak memory	275092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1406765014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_read_word_sweep_derr.1406765014
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1352285006
Short name	T464
Test name
Test status
Simulation time	80051000 ps
CPU time	41.69 seconds
Started	Oct 15 08:38:16 AM UTC 24
Finished	Oct 15 08:38:59 AM UTC 24
Peak memory	275068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352285006 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.1352285006
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.3773404581
Short name	T225
Test name
Test status
Simulation time	427089600 ps
CPU time	93.26 seconds
Started	Oct 15 08:37:47 AM UTC 24
Finished	Oct 15 08:39:22 AM UTC 24
Peak memory	291424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3773404581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.3773404581
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3004147004
Short name	T473
Test name
Test status
Simulation time	2962622500 ps
CPU time	137.69 seconds
Started	Oct 15 08:39:00 AM UTC 24
Finished	Oct 15 08:41:20 AM UTC 24
Peak memory	291528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004147004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3004147004
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1201783467
Short name	T469
Test name
Test status
Simulation time	629277800 ps
CPU time	126.73 seconds
Started	Oct 15 08:38:20 AM UTC 24
Finished	Oct 15 08:40:29 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1201783467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_ro_serr.1201783467
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.1175469012
Short name	T211
Test name
Test status
Simulation time	5564328700 ps
CPU time	199.7 seconds
Started	Oct 15 08:39:23 AM UTC 24
Finished	Oct 15 08:42:46 AM UTC 24
Peak memory	297684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1175469012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.flash_ctrl_rw_derr.1175469012
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.2883161828
Short name	T371
Test name
Test status
Simulation time	29528400 ps
CPU time	37.91 seconds
Started	Oct 15 08:40:24 AM UTC 24
Finished	Oct 15 08:41:04 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883161828 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.2883161828
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1161671925
Short name	T472
Test name
Test status
Simulation time	46074400 ps
CPU time	43.17 seconds
Started	Oct 15 08:40:24 AM UTC 24
Finished	Oct 15 08:41:09 AM UTC 24
Peak memory	287428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1161671925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_rw_evict_all_en.1161671925
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.3861772242
Short name	T476
Test name
Test status
Simulation time	7588440400 ps
CPU time	177.9 seconds
Started	Oct 15 08:38:50 AM UTC 24
Finished	Oct 15 08:41:50 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3861772242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.3861772242
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.42111439
Short name	T140
Test name
Test status
Simulation time	3260135600 ps
CPU time	6722.84 seconds
Started	Oct 15 08:40:52 AM UTC 24
Finished	Oct 15 10:34:14 AM UTC 24
Peak memory	316056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42111439 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.42111439
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2783833468
Short name	T424
Test name
Test status
Simulation time	1149090000 ps
CPU time	91.5 seconds
Started	Oct 15 08:41:05 AM UTC 24
Finished	Oct 15 08:42:38 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783833468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2783833468
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1948557352
Short name	T466
Test name
Test status
Simulation time	480274400 ps
CPU time	68.99 seconds
Started	Oct 15 08:38:58 AM UTC 24
Finished	Oct 15 08:40:09 AM UTC 24
Peak memory	275140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194 8557352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_address.1948557352
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.548321579
Short name	T467
Test name
Test status
Simulation time	1019420000 ps
CPU time	82.23 seconds
Started	Oct 15 08:38:58 AM UTC 24
Finished	Oct 15 08:40:22 AM UTC 24
Peak memory	275144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54 8321579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_counter.548321579
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2256838390
Short name	T478
Test name
Test status
Simulation time	35583900 ps
CPU time	319.6 seconds
Started	Oct 15 08:36:36 AM UTC 24
Finished	Oct 15 08:42:00 AM UTC 24
Peak memory	291408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256838390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2256838390
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3511928198
Short name	T457
Test name
Test status
Simulation time	56158400 ps
CPU time	32.68 seconds
Started	Oct 15 08:36:39 AM UTC 24
Finished	Oct 15 08:37:13 AM UTC 24
Peak memory	270688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511928198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3511928198
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.769675297
Short name	T485
Test name
Test status
Simulation time	27695500 ps
CPU time	161.47 seconds
Started	Oct 15 08:41:05 AM UTC 24
Finished	Oct 15 08:43:49 AM UTC 24
Peak memory	289188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769675297 -assert nopostproc +UVM_TESTNA ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.769675297
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.4249331478
Short name	T458
Test name
Test status
Simulation time	88608300 ps
CPU time	35.04 seconds
Started	Oct 15 08:36:39 AM UTC 24
Finished	Oct 15 08:37:15 AM UTC 24
Peak memory	270688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249331478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.4249331478
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.504229253
Short name	T468
Test name
Test status
Simulation time	4393365200 ps
CPU time	159.85 seconds
Started	Oct 15 08:37:40 AM UTC 24
Finished	Oct 15 08:40:23 AM UTC 24
Peak memory	275152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =504229253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.504229253
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.1026891231
Short name	T968
Test name
Test status
Simulation time	241125300 ps
CPU time	17.33 seconds
Started	Oct 15 09:32:38 AM UTC 24
Finished	Oct 15 09:32:57 AM UTC 24
Peak memory	266776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026891231 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.1026891231
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.1171612418
Short name	T969
Test name
Test status
Simulation time	19733100 ps
CPU time	24.01 seconds
Started	Oct 15 09:32:32 AM UTC 24
Finished	Oct 15 09:32:57 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171612418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1171612418
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.2503809337
Short name	T972
Test name
Test status
Simulation time	33455200 ps
CPU time	37.53 seconds
Started	Oct 15 09:32:32 AM UTC 24
Finished	Oct 15 09:33:11 AM UTC 24
Peak memory	285316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2503809337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ ctrl_disable.2503809337
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.1996497495
Short name	T326
Test name
Test status
Simulation time	2940286200 ps
CPU time	100.25 seconds
Started	Oct 15 09:32:24 AM UTC 24
Finished	Oct 15 09:34:06 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996497495 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.1996497495
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.666010741
Short name	T1040
Test name
Test status
Simulation time	39341300 ps
CPU time	162.43 seconds
Started	Oct 15 09:32:32 AM UTC 24
Finished	Oct 15 09:35:17 AM UTC 24
Peak memory	270920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666010741 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.666010741
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.63363701
Short name	T990
Test name
Test status
Simulation time	2584730900 ps
CPU time	71.49 seconds
Started	Oct 15 09:32:32 AM UTC 24
Finished	Oct 15 09:33:45 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63363701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.63363701
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.1218239428
Short name	T1028
Test name
Test status
Simulation time	38136800 ps
CPU time	155.5 seconds
Started	Oct 15 09:32:24 AM UTC 24
Finished	Oct 15 09:35:02 AM UTC 24
Peak memory	287192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218239428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1218239428
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.1406834848
Short name	T973
Test name
Test status
Simulation time	37754600 ps
CPU time	19.46 seconds
Started	Oct 15 09:32:54 AM UTC 24
Finished	Oct 15 09:33:15 AM UTC 24
Peak memory	268932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406834848 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.1406834848
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3264046383
Short name	T976
Test name
Test status
Simulation time	16293400 ps
CPU time	27.64 seconds
Started	Oct 15 09:32:53 AM UTC 24
Finished	Oct 15 09:33:22 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264046383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3264046383
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.3879869984
Short name	T982
Test name
Test status
Simulation time	20290500 ps
CPU time	40.41 seconds
Started	Oct 15 09:32:51 AM UTC 24
Finished	Oct 15 09:33:33 AM UTC 24
Peak memory	283224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3879869984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ ctrl_disable.3879869984
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.4287118684
Short name	T1019
Test name
Test status
Simulation time	1655586100 ps
CPU time	124.32 seconds
Started	Oct 15 09:32:42 AM UTC 24
Finished	Oct 15 09:34:49 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287118684 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.4287118684
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.97543031
Short name	T1054
Test name
Test status
Simulation time	148115400 ps
CPU time	171.08 seconds
Started	Oct 15 09:32:44 AM UTC 24
Finished	Oct 15 09:35:38 AM UTC 24
Peak memory	270856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97543031 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.97543031
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.4041370209
Short name	T999
Test name
Test status
Simulation time	2482366000 ps
CPU time	71.4 seconds
Started	Oct 15 09:32:52 AM UTC 24
Finished	Oct 15 09:34:05 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041370209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.4041370209
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.273138579
Short name	T1068
Test name
Test status
Simulation time	33934500 ps
CPU time	191.45 seconds
Started	Oct 15 09:32:42 AM UTC 24
Finished	Oct 15 09:35:57 AM UTC 24
Peak memory	289236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273138579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.273138579
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.3913013462
Short name	T980
Test name
Test status
Simulation time	66963200 ps
CPU time	17.55 seconds
Started	Oct 15 09:33:10 AM UTC 24
Finished	Oct 15 09:33:29 AM UTC 24
Peak memory	268820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913013462 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.3913013462
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.1870860265
Short name	T981
Test name
Test status
Simulation time	49873900 ps
CPU time	20.38 seconds
Started	Oct 15 09:33:09 AM UTC 24
Finished	Oct 15 09:33:30 AM UTC 24
Peak memory	294936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870860265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1870860265
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.3583366516
Short name	T985
Test name
Test status
Simulation time	10513500 ps
CPU time	35.73 seconds
Started	Oct 15 09:32:59 AM UTC 24
Finished	Oct 15 09:33:36 AM UTC 24
Peak memory	285096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3583366516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ ctrl_disable.3583366516
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.335125439
Short name	T1034
Test name
Test status
Simulation time	14945802700 ps
CPU time	129.76 seconds
Started	Oct 15 09:32:57 AM UTC 24
Finished	Oct 15 09:35:10 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335125439 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.335125439
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.4146628020
Short name	T1053
Test name
Test status
Simulation time	54246100 ps
CPU time	156.9 seconds
Started	Oct 15 09:32:57 AM UTC 24
Finished	Oct 15 09:35:37 AM UTC 24
Peak memory	270712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146628020 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.4146628020
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.79068851
Short name	T428
Test name
Test status
Simulation time	7704100000 ps
CPU time	94.85 seconds
Started	Oct 15 09:32:59 AM UTC 24
Finished	Oct 15 09:34:36 AM UTC 24
Peak memory	274780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79068851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.79068851
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.1344285393
Short name	T1058
Test name
Test status
Simulation time	675530500 ps
CPU time	164.81 seconds
Started	Oct 15 09:32:57 AM UTC 24
Finished	Oct 15 09:35:45 AM UTC 24
Peak memory	279120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344285393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1344285393
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.402203659
Short name	T989
Test name
Test status
Simulation time	95152800 ps
CPU time	18.36 seconds
Started	Oct 15 09:33:25 AM UTC 24
Finished	Oct 15 09:33:44 AM UTC 24
Peak memory	268288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402203659 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.402203659
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.1399583619
Short name	T988
Test name
Test status
Simulation time	36143000 ps
CPU time	17.87 seconds
Started	Oct 15 09:33:24 AM UTC 24
Finished	Oct 15 09:33:43 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399583619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1399583619
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.699937576
Short name	T991
Test name
Test status
Simulation time	10213300 ps
CPU time	25.69 seconds
Started	Oct 15 09:33:19 AM UTC 24
Finished	Oct 15 09:33:46 AM UTC 24
Peak memory	285316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=699937576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_c trl_disable.699937576
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.3062583494
Short name	T1021
Test name
Test status
Simulation time	26830606700 ps
CPU time	92.1 seconds
Started	Oct 15 09:33:16 AM UTC 24
Finished	Oct 15 09:34:50 AM UTC 24
Peak memory	272792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062583494 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.3062583494
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.381831600
Short name	T193
Test name
Test status
Simulation time	46268100 ps
CPU time	168.43 seconds
Started	Oct 15 09:33:16 AM UTC 24
Finished	Oct 15 09:36:08 AM UTC 24
Peak memory	270592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381831600 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.381831600
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.1717886247
Short name	T1016
Test name
Test status
Simulation time	552021900 ps
CPU time	76.48 seconds
Started	Oct 15 09:33:24 AM UTC 24
Finished	Oct 15 09:34:42 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717886247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1717886247
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.16059070
Short name	T1018
Test name
Test status
Simulation time	22825800 ps
CPU time	89.39 seconds
Started	Oct 15 09:33:12 AM UTC 24
Finished	Oct 15 09:34:43 AM UTC 24
Peak memory	287188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16059070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.16059070
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.18812240
Short name	T994
Test name
Test status
Simulation time	167657600 ps
CPU time	18.51 seconds
Started	Oct 15 09:33:36 AM UTC 24
Finished	Oct 15 09:33:56 AM UTC 24
Peak memory	268936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18812240 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.18812240
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.1656306714
Short name	T993
Test name
Test status
Simulation time	20723000 ps
CPU time	18.2 seconds
Started	Oct 15 09:33:34 AM UTC 24
Finished	Oct 15 09:33:53 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656306714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.1656306714
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.2998260528
Short name	T1002
Test name
Test status
Simulation time	15325800 ps
CPU time	34.64 seconds
Started	Oct 15 09:33:32 AM UTC 24
Finished	Oct 15 09:34:08 AM UTC 24
Peak memory	285340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2998260528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ ctrl_disable.2998260528
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.8735113
Short name	T1037
Test name
Test status
Simulation time	2460054400 ps
CPU time	100.82 seconds
Started	Oct 15 09:33:29 AM UTC 24
Finished	Oct 15 09:35:13 AM UTC 24
Peak memory	274844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8735113 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.8735113
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.1983243440
Short name	T1023
Test name
Test status
Simulation time	408470500 ps
CPU time	82.34 seconds
Started	Oct 15 09:33:33 AM UTC 24
Finished	Oct 15 09:34:57 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983243440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1983243440
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.3304011486
Short name	T1120
Test name
Test status
Simulation time	48038600 ps
CPU time	315.66 seconds
Started	Oct 15 09:33:29 AM UTC 24
Finished	Oct 15 09:38:50 AM UTC 24
Peak memory	291408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304011486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3304011486
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.3476680491
Short name	T1000
Test name
Test status
Simulation time	52984600 ps
CPU time	19.78 seconds
Started	Oct 15 09:33:46 AM UTC 24
Finished	Oct 15 09:34:07 AM UTC 24
Peak memory	268932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476680491 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.3476680491
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.3751569236
Short name	T1004
Test name
Test status
Simulation time	48210300 ps
CPU time	24.69 seconds
Started	Oct 15 09:33:46 AM UTC 24
Finished	Oct 15 09:34:12 AM UTC 24
Peak memory	284768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751569236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3751569236
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.1488103990
Short name	T1003
Test name
Test status
Simulation time	20382700 ps
CPU time	27.79 seconds
Started	Oct 15 09:33:42 AM UTC 24
Finished	Oct 15 09:34:12 AM UTC 24
Peak memory	285532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1488103990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ ctrl_disable.1488103990
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.2425740483
Short name	T1044
Test name
Test status
Simulation time	2795578300 ps
CPU time	105.97 seconds
Started	Oct 15 09:33:37 AM UTC 24
Finished	Oct 15 09:35:25 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425740483 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.2425740483
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2681475278
Short name	T1081
Test name
Test status
Simulation time	75492600 ps
CPU time	157.73 seconds
Started	Oct 15 09:33:40 AM UTC 24
Finished	Oct 15 09:36:21 AM UTC 24
Peak memory	271116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681475278 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.2681475278
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.1681504149
Short name	T1031
Test name
Test status
Simulation time	2845029800 ps
CPU time	78.82 seconds
Started	Oct 15 09:33:43 AM UTC 24
Finished	Oct 15 09:35:04 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681504149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1681504149
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.3706839348
Short name	T1064
Test name
Test status
Simulation time	30812100 ps
CPU time	133.76 seconds
Started	Oct 15 09:33:36 AM UTC 24
Finished	Oct 15 09:35:52 AM UTC 24
Peak memory	287132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706839348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3706839348
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.18416390
Short name	T1009
Test name
Test status
Simulation time	637982400 ps
CPU time	26.41 seconds
Started	Oct 15 09:34:00 AM UTC 24
Finished	Oct 15 09:34:27 AM UTC 24
Peak memory	268932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18416390 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.18416390
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.4200139552
Short name	T1008
Test name
Test status
Simulation time	15580500 ps
CPU time	26.07 seconds
Started	Oct 15 09:33:57 AM UTC 24
Finished	Oct 15 09:34:25 AM UTC 24
Peak memory	294944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200139552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.4200139552
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.3126058490
Short name	T1011
Test name
Test status
Simulation time	10948300 ps
CPU time	30.82 seconds
Started	Oct 15 09:33:56 AM UTC 24
Finished	Oct 15 09:34:28 AM UTC 24
Peak memory	285404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3126058490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ ctrl_disable.3126058490
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3534287020
Short name	T1075
Test name
Test status
Simulation time	6773661200 ps
CPU time	133.29 seconds
Started	Oct 15 09:33:52 AM UTC 24
Finished	Oct 15 09:36:08 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534287020 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.3534287020
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.870888361
Short name	T1085
Test name
Test status
Simulation time	126288400 ps
CPU time	152.7 seconds
Started	Oct 15 09:33:54 AM UTC 24
Finished	Oct 15 09:36:29 AM UTC 24
Peak memory	270856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870888361 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.870888361
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3565326004
Short name	T429
Test name
Test status
Simulation time	1458375600 ps
CPU time	63.29 seconds
Started	Oct 15 09:33:57 AM UTC 24
Finished	Oct 15 09:35:03 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565326004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3565326004
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.3288415673
Short name	T1066
Test name
Test status
Simulation time	102954400 ps
CPU time	126.26 seconds
Started	Oct 15 09:33:47 AM UTC 24
Finished	Oct 15 09:35:55 AM UTC 24
Peak memory	287320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288415673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3288415673
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.959344695
Short name	T1015
Test name
Test status
Simulation time	85320500 ps
CPU time	23.94 seconds
Started	Oct 15 09:34:12 AM UTC 24
Finished	Oct 15 09:34:38 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959344695 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.959344695
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.2996987370
Short name	T1012
Test name
Test status
Simulation time	38218100 ps
CPU time	19.26 seconds
Started	Oct 15 09:34:09 AM UTC 24
Finished	Oct 15 09:34:30 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996987370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2996987370
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.279473793
Short name	T1017
Test name
Test status
Simulation time	15606100 ps
CPU time	32.9 seconds
Started	Oct 15 09:34:07 AM UTC 24
Finished	Oct 15 09:34:43 AM UTC 24
Peak memory	285320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=279473793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_c trl_disable.279473793
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.2158069450
Short name	T1050
Test name
Test status
Simulation time	2975748300 ps
CPU time	83.99 seconds
Started	Oct 15 09:34:06 AM UTC 24
Finished	Oct 15 09:35:32 AM UTC 24
Peak memory	272800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158069450 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.2158069450
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3701996124
Short name	T1087
Test name
Test status
Simulation time	40565700 ps
CPU time	167.29 seconds
Started	Oct 15 09:34:07 AM UTC 24
Finished	Oct 15 09:36:57 AM UTC 24
Peak memory	270648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701996124 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.3701996124
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.2225527756
Short name	T1036
Test name
Test status
Simulation time	2027710100 ps
CPU time	60.77 seconds
Started	Oct 15 09:34:08 AM UTC 24
Finished	Oct 15 09:35:11 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225527756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2225527756
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1811453653
Short name	T1089
Test name
Test status
Simulation time	20367500 ps
CPU time	180.73 seconds
Started	Oct 15 09:34:01 AM UTC 24
Finished	Oct 15 09:37:04 AM UTC 24
Peak memory	278992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811453653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.1811453653
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1755128403
Short name	T1024
Test name
Test status
Simulation time	31280900 ps
CPU time	24.04 seconds
Started	Oct 15 09:34:32 AM UTC 24
Finished	Oct 15 09:34:57 AM UTC 24
Peak memory	274948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755128403 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1755128403
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.1605025381
Short name	T1027
Test name
Test status
Simulation time	93180700 ps
CPU time	26.45 seconds
Started	Oct 15 09:34:32 AM UTC 24
Finished	Oct 15 09:35:00 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605025381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1605025381
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.2721068860
Short name	T391
Test name
Test status
Simulation time	26426300 ps
CPU time	29.68 seconds
Started	Oct 15 09:34:20 AM UTC 24
Finished	Oct 15 09:34:51 AM UTC 24
Peak memory	285312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2721068860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ ctrl_disable.2721068860
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.2742862954
Short name	T327
Test name
Test status
Simulation time	2522429300 ps
CPU time	87.92 seconds
Started	Oct 15 09:34:19 AM UTC 24
Finished	Oct 15 09:35:49 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742862954 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.2742862954
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.1388208887
Short name	T1086
Test name
Test status
Simulation time	76329900 ps
CPU time	142.82 seconds
Started	Oct 15 09:34:19 AM UTC 24
Finished	Oct 15 09:36:44 AM UTC 24
Peak memory	275020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388208887 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.1388208887
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.3479817059
Short name	T1056
Test name
Test status
Simulation time	3534919600 ps
CPU time	73.5 seconds
Started	Oct 15 09:34:26 AM UTC 24
Finished	Oct 15 09:35:42 AM UTC 24
Peak memory	274916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479817059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3479817059
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.2381613420
Short name	T1090
Test name
Test status
Simulation time	53448300 ps
CPU time	175.03 seconds
Started	Oct 15 09:34:12 AM UTC 24
Finished	Oct 15 09:37:10 AM UTC 24
Peak memory	287164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381613420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2381613420
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.217705950
Short name	T1029
Test name
Test status
Simulation time	60816400 ps
CPU time	19.11 seconds
Started	Oct 15 09:34:43 AM UTC 24
Finished	Oct 15 09:35:03 AM UTC 24
Peak memory	268816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217705950 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.217705950
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.2715548310
Short name	T1026
Test name
Test status
Simulation time	19723100 ps
CPU time	18.52 seconds
Started	Oct 15 09:34:39 AM UTC 24
Finished	Oct 15 09:34:59 AM UTC 24
Peak memory	284832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715548310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2715548310
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.305296714
Short name	T1035
Test name
Test status
Simulation time	10770700 ps
CPU time	32.24 seconds
Started	Oct 15 09:34:36 AM UTC 24
Finished	Oct 15 09:35:10 AM UTC 24
Peak memory	285308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=305296714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_c trl_disable.305296714
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.2488607022
Short name	T1059
Test name
Test status
Simulation time	6819875400 ps
CPU time	70.64 seconds
Started	Oct 15 09:34:33 AM UTC 24
Finished	Oct 15 09:35:46 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488607022 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.2488607022
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.479377530
Short name	T1092
Test name
Test status
Simulation time	76108000 ps
CPU time	161.81 seconds
Started	Oct 15 09:34:33 AM UTC 24
Finished	Oct 15 09:37:18 AM UTC 24
Peak memory	274928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479377530 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.479377530
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.3325778522
Short name	T1071
Test name
Test status
Simulation time	4855815400 ps
CPU time	82.21 seconds
Started	Oct 15 09:34:37 AM UTC 24
Finished	Oct 15 09:36:02 AM UTC 24
Peak memory	275048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325778522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3325778522
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.266999525
Short name	T1093
Test name
Test status
Simulation time	30923600 ps
CPU time	167.12 seconds
Started	Oct 15 09:34:33 AM UTC 24
Finished	Oct 15 09:37:23 AM UTC 24
Peak memory	289232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266999525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.266999525
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2687430534
Short name	T491
Test name
Test status
Simulation time	70796700 ps
CPU time	18.38 seconds
Started	Oct 15 08:45:06 AM UTC 24
Finished	Oct 15 08:45:26 AM UTC 24
Peak memory	274944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687430534 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2687430534
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.2209571933
Short name	T394
Test name
Test status
Simulation time	54381100 ps
CPU time	21.6 seconds
Started	Oct 15 08:44:52 AM UTC 24
Finished	Oct 15 08:45:15 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209571933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2209571933
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.4219583612
Short name	T493
Test name
Test status
Simulation time	22145300 ps
CPU time	37.65 seconds
Started	Oct 15 08:44:51 AM UTC 24
Finished	Oct 15 08:45:30 AM UTC 24
Peak memory	285444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4219583612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c trl_disable.4219583612
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.2236801084
Short name	T960
Test name
Test status
Simulation time	21294112700 ps
CPU time	2999.18 seconds
Started	Oct 15 08:42:12 AM UTC 24
Finished	Oct 15 09:32:42 AM UTC 24
Peak memory	272860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236801084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.2236801084
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.4182884836
Short name	T548
Test name
Test status
Simulation time	311257200 ps
CPU time	898.59 seconds
Started	Oct 15 08:42:03 AM UTC 24
Finished	Oct 15 08:57:12 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182884836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.4182884836
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2739630603
Short name	T483
Test name
Test status
Simulation time	161432600 ps
CPU time	34.05 seconds
Started	Oct 15 08:42:03 AM UTC 24
Finished	Oct 15 08:42:38 AM UTC 24
Peak memory	274900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 39630603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc h_code.2739630603
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.1757887082
Short name	T284
Test name
Test status
Simulation time	36637300 ps
CPU time	20.38 seconds
Started	Oct 15 08:45:01 AM UTC 24
Finished	Oct 15 08:45:23 AM UTC 24
Peak memory	274936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1757887082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1757887082
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.2051934299
Short name	T543
Test name
Test status
Simulation time	80140381200 ps
CPU time	862.16 seconds
Started	Oct 15 08:42:00 AM UTC 24
Finished	Oct 15 08:56:32 AM UTC 24
Peak memory	274872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051934299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.2051934299
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1362833825
Short name	T317
Test name
Test status
Simulation time	6944344400 ps
CPU time	130.56 seconds
Started	Oct 15 08:41:52 AM UTC 24
Finished	Oct 15 08:44:05 AM UTC 24
Peak memory	274856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362833825 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.1362833825
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.4048186889
Short name	T49
Test name
Test status
Simulation time	563140000 ps
CPU time	112.54 seconds
Started	Oct 15 08:43:19 AM UTC 24
Finished	Oct 15 08:45:14 AM UTC 24
Peak memory	305984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048186889 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.4048186889
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.463246206
Short name	T329
Test name
Test status
Simulation time	7353496700 ps
CPU time	222.79 seconds
Started	Oct 15 08:43:49 AM UTC 24
Finished	Oct 15 08:47:35 AM UTC 24
Peak memory	303700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=463246206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_rd_slow_flash.463246206
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.3880343108
Short name	T494
Test name
Test status
Simulation time	2966136900 ps
CPU time	117.96 seconds
Started	Oct 15 08:43:30 AM UTC 24
Finished	Oct 15 08:45:31 AM UTC 24
Peak memory	270928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880343108 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.3880343108
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3426861724
Short name	T501
Test name
Test status
Simulation time	96885214300 ps
CPU time	184.94 seconds
Started	Oct 15 08:44:05 AM UTC 24
Finished	Oct 15 08:47:13 AM UTC 24
Peak memory	271040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426861724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3426861724
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1771815978
Short name	T486
Test name
Test status
Simulation time	8994352900 ps
CPU time	112.62 seconds
Started	Oct 15 08:42:14 AM UTC 24
Finished	Oct 15 08:44:09 AM UTC 24
Peak memory	272848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771815978 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1771815978
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.4273798732
Short name	T490
Test name
Test status
Simulation time	8090625100 ps
CPU time	197.77 seconds
Started	Oct 15 08:42:01 AM UTC 24
Finished	Oct 15 08:45:22 AM UTC 24
Peak memory	275156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4273798732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.4273798732
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.280103836
Short name	T495
Test name
Test status
Simulation time	149722200 ps
CPU time	208.12 seconds
Started	Oct 15 08:42:00 AM UTC 24
Finished	Oct 15 08:45:31 AM UTC 24
Peak memory	270840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280103836 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.280103836
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2559989532
Short name	T497
Test name
Test status
Simulation time	200467700 ps
CPU time	293.69 seconds
Started	Oct 15 08:41:48 AM UTC 24
Finished	Oct 15 08:46:46 AM UTC 24
Peak memory	275036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559989532 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2559989532
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.2282972762
Short name	T488
Test name
Test status
Simulation time	71763600 ps
CPU time	22.47 seconds
Started	Oct 15 08:44:11 AM UTC 24
Finished	Oct 15 08:44:34 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282972762 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.2282972762
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.218640240
Short name	T642
Test name
Test status
Simulation time	821852300 ps
CPU time	1737.03 seconds
Started	Oct 15 08:41:46 AM UTC 24
Finished	Oct 15 09:11:02 AM UTC 24
Peak memory	297620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218640240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.218640240
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1374990093
Short name	T357
Test name
Test status
Simulation time	193166900 ps
CPU time	52.82 seconds
Started	Oct 15 08:44:38 AM UTC 24
Finished	Oct 15 08:45:32 AM UTC 24
Peak memory	287568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374990093 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.1374990093
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3694644022
Short name	T151
Test name
Test status
Simulation time	1127182600 ps
CPU time	128.72 seconds
Started	Oct 15 08:42:39 AM UTC 24
Finished	Oct 15 08:44:51 AM UTC 24
Peak memory	291556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3694644022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.3694644022
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.1254932254
Short name	T156
Test name
Test status
Simulation time	7175698600 ps
CPU time	129.15 seconds
Started	Oct 15 08:42:58 AM UTC 24
Finished	Oct 15 08:45:09 AM UTC 24
Peak memory	291520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254932254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1254932254
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.1152769520
Short name	T152
Test name
Test status
Simulation time	2038671800 ps
CPU time	135.69 seconds
Started	Oct 15 08:42:42 AM UTC 24
Finished	Oct 15 08:45:00 AM UTC 24
Peak memory	306068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1152769520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_ro_serr.1152769520
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2009703713
Short name	T517
Test name
Test status
Simulation time	5426722700 ps
CPU time	467.23 seconds
Started	Oct 15 08:42:39 AM UTC 24
Finished	Oct 15 08:50:32 AM UTC 24
Peak memory	322200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009703713 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.2009703713
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.1020573141
Short name	T492
Test name
Test status
Simulation time	1586536900 ps
CPU time	138.91 seconds
Started	Oct 15 08:43:05 AM UTC 24
Finished	Oct 15 08:45:26 AM UTC 24
Peak memory	291588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1020573141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 5.flash_ctrl_rw_derr.1020573141
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.2390663808
Short name	T154
Test name
Test status
Simulation time	104141700 ps
CPU time	33.26 seconds
Started	Oct 15 08:44:27 AM UTC 24
Finished	Oct 15 08:45:01 AM UTC 24
Peak memory	287568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390663808 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.2390663808
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.37668058
Short name	T489
Test name
Test status
Simulation time	28964600 ps
CPU time	40.09 seconds
Started	Oct 15 08:44:35 AM UTC 24
Finished	Oct 15 08:45:16 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=37668058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _rw_evict_all_en.37668058
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.1423167690
Short name	T502
Test name
Test status
Simulation time	2111083100 ps
CPU time	270.7 seconds
Started	Oct 15 08:42:47 AM UTC 24
Finished	Oct 15 08:47:21 AM UTC 24
Peak memory	305924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1423167690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.1423167690
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3686352681
Short name	T425
Test name
Test status
Simulation time	330925500 ps
CPU time	74.18 seconds
Started	Oct 15 08:44:52 AM UTC 24
Finished	Oct 15 08:46:08 AM UTC 24
Peak memory	274920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686352681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3686352681
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.1023698945
Short name	T153
Test name
Test status
Simulation time	41546700 ps
CPU time	192.47 seconds
Started	Oct 15 08:41:44 AM UTC 24
Finished	Oct 15 08:45:00 AM UTC 24
Peak memory	287256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023698945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1023698945
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2310197493
Short name	T155
Test name
Test status
Simulation time	7849425400 ps
CPU time	158.96 seconds
Started	Oct 15 08:42:23 AM UTC 24
Finished	Oct 15 08:45:05 AM UTC 24
Peak memory	270944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2310197493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.2310197493
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.1382542470
Short name	T1032
Test name
Test status
Simulation time	13515200 ps
CPU time	21.09 seconds
Started	Oct 15 09:34:44 AM UTC 24
Finished	Oct 15 09:35:06 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382542470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1382542470
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1611186553
Short name	T1088
Test name
Test status
Simulation time	37260600 ps
CPU time	133.4 seconds
Started	Oct 15 09:34:44 AM UTC 24
Finished	Oct 15 09:36:59 AM UTC 24
Peak memory	270836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611186553 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.1611186553
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.1734125766
Short name	T1039
Test name
Test status
Simulation time	18897100 ps
CPU time	23.13 seconds
Started	Oct 15 09:34:50 AM UTC 24
Finished	Oct 15 09:35:15 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734125766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1734125766
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.640235102
Short name	T1094
Test name
Test status
Simulation time	354579400 ps
CPU time	159.34 seconds
Started	Oct 15 09:34:50 AM UTC 24
Finished	Oct 15 09:37:32 AM UTC 24
Peak memory	274992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640235102 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.640235102
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.1910558263
Short name	T1038
Test name
Test status
Simulation time	26240500 ps
CPU time	19.24 seconds
Started	Oct 15 09:34:52 AM UTC 24
Finished	Oct 15 09:35:13 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910558263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1910558263
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.2577302383
Short name	T1096
Test name
Test status
Simulation time	86162500 ps
CPU time	164.62 seconds
Started	Oct 15 09:34:51 AM UTC 24
Finished	Oct 15 09:37:39 AM UTC 24
Peak memory	275152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577302383 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.2577302383
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.1867868648
Short name	T1041
Test name
Test status
Simulation time	20893400 ps
CPU time	19.13 seconds
Started	Oct 15 09:34:58 AM UTC 24
Finished	Oct 15 09:35:18 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867868648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1867868648
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1430703870
Short name	T1099
Test name
Test status
Simulation time	78460000 ps
CPU time	168.76 seconds
Started	Oct 15 09:34:56 AM UTC 24
Finished	Oct 15 09:37:48 AM UTC 24
Peak memory	274936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430703870 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.1430703870
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.3236298960
Short name	T1047
Test name
Test status
Simulation time	44642300 ps
CPU time	26.28 seconds
Started	Oct 15 09:34:59 AM UTC 24
Finished	Oct 15 09:35:26 AM UTC 24
Peak memory	284828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236298960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3236298960
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3378204591
Short name	T1091
Test name
Test status
Simulation time	42654000 ps
CPU time	131.03 seconds
Started	Oct 15 09:34:58 AM UTC 24
Finished	Oct 15 09:37:11 AM UTC 24
Peak memory	275148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378204591 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.3378204591
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.2767236312
Short name	T1045
Test name
Test status
Simulation time	44680000 ps
CPU time	23.2 seconds
Started	Oct 15 09:35:01 AM UTC 24
Finished	Oct 15 09:35:25 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767236312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2767236312
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.2867571214
Short name	T1104
Test name
Test status
Simulation time	141094100 ps
CPU time	175.71 seconds
Started	Oct 15 09:35:00 AM UTC 24
Finished	Oct 15 09:37:59 AM UTC 24
Peak memory	272952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867571214 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.2867571214
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.1127246663
Short name	T1042
Test name
Test status
Simulation time	21326200 ps
CPU time	17.52 seconds
Started	Oct 15 09:35:03 AM UTC 24
Finished	Oct 15 09:35:22 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127246663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1127246663
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3016973668
Short name	T1097
Test name
Test status
Simulation time	98394100 ps
CPU time	153.11 seconds
Started	Oct 15 09:35:03 AM UTC 24
Finished	Oct 15 09:37:39 AM UTC 24
Peak memory	275212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016973668 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.3016973668
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.3239461406
Short name	T1043
Test name
Test status
Simulation time	14598300 ps
CPU time	19.56 seconds
Started	Oct 15 09:35:04 AM UTC 24
Finished	Oct 15 09:35:25 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239461406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3239461406
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1502436570
Short name	T1105
Test name
Test status
Simulation time	71790000 ps
CPU time	171.67 seconds
Started	Oct 15 09:35:04 AM UTC 24
Finished	Oct 15 09:37:59 AM UTC 24
Peak memory	274804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502436570 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1502436570
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.2397940621
Short name	T1046
Test name
Test status
Simulation time	53105900 ps
CPU time	18.23 seconds
Started	Oct 15 09:35:07 AM UTC 24
Finished	Oct 15 09:35:26 AM UTC 24
Peak memory	294936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397940621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2397940621
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.881283078
Short name	T1110
Test name
Test status
Simulation time	220051900 ps
CPU time	194.94 seconds
Started	Oct 15 09:35:06 AM UTC 24
Finished	Oct 15 09:38:24 AM UTC 24
Peak memory	274736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881283078 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.881283078
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.3732437789
Short name	T1049
Test name
Test status
Simulation time	15274200 ps
CPU time	18.32 seconds
Started	Oct 15 09:35:11 AM UTC 24
Finished	Oct 15 09:35:30 AM UTC 24
Peak memory	284828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732437789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3732437789
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3437255686
Short name	T1101
Test name
Test status
Simulation time	168818300 ps
CPU time	158.92 seconds
Started	Oct 15 09:35:10 AM UTC 24
Finished	Oct 15 09:37:51 AM UTC 24
Peak memory	270840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437255686 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.3437255686
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.641810457
Short name	T512
Test name
Test status
Simulation time	112142300 ps
CPU time	28.36 seconds
Started	Oct 15 08:48:51 AM UTC 24
Finished	Oct 15 08:49:21 AM UTC 24
Peak memory	268928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641810457 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.641810457
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1817333382
Short name	T395
Test name
Test status
Simulation time	16866200 ps
CPU time	25.94 seconds
Started	Oct 15 08:48:31 AM UTC 24
Finished	Oct 15 08:48:58 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817333382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1817333382
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1719709576
Short name	T415
Test name
Test status
Simulation time	26190900 ps
CPU time	36.3 seconds
Started	Oct 15 08:48:20 AM UTC 24
Finished	Oct 15 08:48:58 AM UTC 24
Peak memory	285248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1719709576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c trl_disable.1719709576
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.3685897122
Short name	T1123
Test name
Test status
Simulation time	3667018500 ps
CPU time	3230.35 seconds
Started	Oct 15 08:45:31 AM UTC 24
Finished	Oct 15 09:39:56 AM UTC 24
Peak memory	272984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685897122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3685897122
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.1189246812
Short name	T627
Test name
Test status
Simulation time	3262666900 ps
CPU time	1385.23 seconds
Started	Oct 15 08:45:27 AM UTC 24
Finished	Oct 15 09:08:48 AM UTC 24
Peak memory	285164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189246812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1189246812
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.252040956
Short name	T496
Test name
Test status
Simulation time	536330100 ps
CPU time	43.85 seconds
Started	Oct 15 08:45:26 AM UTC 24
Finished	Oct 15 08:46:12 AM UTC 24
Peak memory	272852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 2040956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch _code.252040956
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3793119703
Short name	T206
Test name
Test status
Simulation time	10034638900 ps
CPU time	95 seconds
Started	Oct 15 08:48:51 AM UTC 24
Finished	Oct 15 08:50:28 AM UTC 24
Peak memory	301628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3793119703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3793119703
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.3558384484
Short name	T180
Test name
Test status
Simulation time	40120836700 ps
CPU time	880.94 seconds
Started	Oct 15 08:45:23 AM UTC 24
Finished	Oct 15 09:00:14 AM UTC 24
Peak memory	274816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558384484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.3558384484
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.221322460
Short name	T505
Test name
Test status
Simulation time	6639638600 ps
CPU time	184.43 seconds
Started	Oct 15 08:45:18 AM UTC 24
Finished	Oct 15 08:48:25 AM UTC 24
Peak memory	274848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221322460 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.221322460
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.163522850
Short name	T50
Test name
Test status
Simulation time	10514763400 ps
CPU time	236.9 seconds
Started	Oct 15 08:47:14 AM UTC 24
Finished	Oct 15 08:51:14 AM UTC 24
Peak memory	301696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163522850 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.163522850
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3811692393
Short name	T347
Test name
Test status
Simulation time	49963727300 ps
CPU time	302.49 seconds
Started	Oct 15 08:47:22 AM UTC 24
Finished	Oct 15 08:52:29 AM UTC 24
Peak memory	301624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3811692393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_intr_rd_slow_flash.3811692393
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.175925302
Short name	T509
Test name
Test status
Simulation time	10446988600 ps
CPU time	94.37 seconds
Started	Oct 15 08:47:14 AM UTC 24
Finished	Oct 15 08:48:50 AM UTC 24
Peak memory	271132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175925302 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.175925302
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1413874519
Short name	T518
Test name
Test status
Simulation time	89088446200 ps
CPU time	179.17 seconds
Started	Oct 15 08:47:36 AM UTC 24
Finished	Oct 15 08:50:38 AM UTC 24
Peak memory	271032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413874519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1413874519
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.1195354888
Short name	T499
Test name
Test status
Simulation time	1744970400 ps
CPU time	89.47 seconds
Started	Oct 15 08:45:32 AM UTC 24
Finished	Oct 15 08:47:03 AM UTC 24
Peak memory	273044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195354888 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.1195354888
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3355572567
Short name	T510
Test name
Test status
Simulation time	15649500 ps
CPU time	22.11 seconds
Started	Oct 15 08:48:40 AM UTC 24
Finished	Oct 15 08:49:04 AM UTC 24
Peak memory	270896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3355572567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_lcmgr_intg.3355572567
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.2929481915
Short name	T160
Test name
Test status
Simulation time	81589457900 ps
CPU time	780.21 seconds
Started	Oct 15 08:45:25 AM UTC 24
Finished	Oct 15 08:58:35 AM UTC 24
Peak memory	283152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2929481915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.2929481915
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.330310620
Short name	T189
Test name
Test status
Simulation time	42960100 ps
CPU time	145.08 seconds
Started	Oct 15 08:45:23 AM UTC 24
Finished	Oct 15 08:47:51 AM UTC 24
Peak memory	270864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330310620 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.330310620
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.1082675348
Short name	T522
Test name
Test status
Simulation time	5395309500 ps
CPU time	379.57 seconds
Started	Oct 15 08:45:15 AM UTC 24
Finished	Oct 15 08:51:40 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082675348 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1082675348
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.768547632
Short name	T504
Test name
Test status
Simulation time	160216000 ps
CPU time	24.61 seconds
Started	Oct 15 08:47:49 AM UTC 24
Finished	Oct 15 08:48:15 AM UTC 24
Peak memory	275032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768547632 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.768547632
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.4059437984
Short name	T604
Test name
Test status
Simulation time	4731886200 ps
CPU time	1207.09 seconds
Started	Oct 15 08:45:14 AM UTC 24
Finished	Oct 15 09:05:34 AM UTC 24
Peak memory	295380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059437984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.4059437984
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.1701939715
Short name	T355
Test name
Test status
Simulation time	118607300 ps
CPU time	49.09 seconds
Started	Oct 15 08:48:16 AM UTC 24
Finished	Oct 15 08:49:06 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701939715 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.1701939715
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.1293192751
Short name	T503
Test name
Test status
Simulation time	1111870700 ps
CPU time	133.08 seconds
Started	Oct 15 08:45:33 AM UTC 24
Finished	Oct 15 08:47:49 AM UTC 24
Peak memory	303760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1293192751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.1293192751
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2633883619
Short name	T508
Test name
Test status
Simulation time	483379700 ps
CPU time	106.78 seconds
Started	Oct 15 08:46:50 AM UTC 24
Finished	Oct 15 08:48:39 AM UTC 24
Peak memory	291520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633883619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2633883619
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1271169383
Short name	T507
Test name
Test status
Simulation time	2136622500 ps
CPU time	143.59 seconds
Started	Oct 15 08:46:13 AM UTC 24
Finished	Oct 15 08:48:39 AM UTC 24
Peak memory	305860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1271169383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_ro_serr.1271169383
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2449610203
Short name	T537
Test name
Test status
Simulation time	8727093400 ps
CPU time	499.66 seconds
Started	Oct 15 08:46:09 AM UTC 24
Finished	Oct 15 08:54:35 AM UTC 24
Peak memory	320172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449610203 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.2449610203
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.960833590
Short name	T521
Test name
Test status
Simulation time	1897807900 ps
CPU time	252.8 seconds
Started	Oct 15 08:47:05 AM UTC 24
Finished	Oct 15 08:51:21 AM UTC 24
Peak memory	291536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=960833590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_rw_derr.960833590
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1127924940
Short name	T368
Test name
Test status
Simulation time	46159700 ps
CPU time	57.91 seconds
Started	Oct 15 08:47:51 AM UTC 24
Finished	Oct 15 08:48:51 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127924940 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.1127924940
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1002532424
Short name	T330
Test name
Test status
Simulation time	29502300 ps
CPU time	50 seconds
Started	Oct 15 08:47:59 AM UTC 24
Finished	Oct 15 08:48:51 AM UTC 24
Peak memory	285412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1002532424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct rl_rw_evict_all_en.1002532424
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1899237860
Short name	T513
Test name
Test status
Simulation time	13388422100 ps
CPU time	169.04 seconds
Started	Oct 15 08:46:47 AM UTC 24
Finished	Oct 15 08:49:39 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1899237860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.1899237860
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3086341764
Short name	T514
Test name
Test status
Simulation time	1642981200 ps
CPU time	72.65 seconds
Started	Oct 15 08:48:26 AM UTC 24
Finished	Oct 15 08:49:41 AM UTC 24
Peak memory	274924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086341764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3086341764
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.3098373860
Short name	T498
Test name
Test status
Simulation time	71307900 ps
CPU time	96.65 seconds
Started	Oct 15 08:45:10 AM UTC 24
Finished	Oct 15 08:46:49 AM UTC 24
Peak memory	285140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098373860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3098373860
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.3374776260
Short name	T511
Test name
Test status
Simulation time	2321271600 ps
CPU time	224.88 seconds
Started	Oct 15 08:45:32 AM UTC 24
Finished	Oct 15 08:49:21 AM UTC 24
Peak memory	275152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3374776260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.3374776260
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.1345641117
Short name	T1052
Test name
Test status
Simulation time	20614400 ps
CPU time	22.71 seconds
Started	Oct 15 09:35:12 AM UTC 24
Finished	Oct 15 09:35:36 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345641117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1345641117
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.4172419149
Short name	T1107
Test name
Test status
Simulation time	42126900 ps
CPU time	174.42 seconds
Started	Oct 15 09:35:11 AM UTC 24
Finished	Oct 15 09:38:08 AM UTC 24
Peak memory	270900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172419149 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.4172419149
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1862383671
Short name	T1051
Test name
Test status
Simulation time	13227300 ps
CPU time	21.13 seconds
Started	Oct 15 09:35:13 AM UTC 24
Finished	Oct 15 09:35:36 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862383671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1862383671
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.57287488
Short name	T1095
Test name
Test status
Simulation time	69080100 ps
CPU time	136.52 seconds
Started	Oct 15 09:35:13 AM UTC 24
Finished	Oct 15 09:37:32 AM UTC 24
Peak memory	275016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57287488 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.57287488
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.524034959
Short name	T1062
Test name
Test status
Simulation time	16615500 ps
CPU time	32.22 seconds
Started	Oct 15 09:35:18 AM UTC 24
Finished	Oct 15 09:35:51 AM UTC 24
Peak memory	294944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524034959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.524034959
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2602289007
Short name	T1100
Test name
Test status
Simulation time	36327800 ps
CPU time	152.48 seconds
Started	Oct 15 09:35:15 AM UTC 24
Finished	Oct 15 09:37:51 AM UTC 24
Peak memory	271180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602289007 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.2602289007
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.2841936515
Short name	T1057
Test name
Test status
Simulation time	15321300 ps
CPU time	17.96 seconds
Started	Oct 15 09:35:23 AM UTC 24
Finished	Oct 15 09:35:42 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841936515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2841936515
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1085016156
Short name	T1098
Test name
Test status
Simulation time	43578700 ps
CPU time	138.06 seconds
Started	Oct 15 09:35:19 AM UTC 24
Finished	Oct 15 09:37:39 AM UTC 24
Peak memory	270836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085016156 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.1085016156
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.431744652
Short name	T1061
Test name
Test status
Simulation time	51577600 ps
CPU time	22.72 seconds
Started	Oct 15 09:35:26 AM UTC 24
Finished	Oct 15 09:35:50 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431744652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.431744652
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1083380770
Short name	T1109
Test name
Test status
Simulation time	42906100 ps
CPU time	164.25 seconds
Started	Oct 15 09:35:26 AM UTC 24
Finished	Oct 15 09:38:13 AM UTC 24
Peak memory	270648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083380770 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.1083380770
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.1076760195
Short name	T1065
Test name
Test status
Simulation time	51407900 ps
CPU time	24.48 seconds
Started	Oct 15 09:35:27 AM UTC 24
Finished	Oct 15 09:35:53 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076760195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1076760195
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.1583069575
Short name	T1102
Test name
Test status
Simulation time	423444300 ps
CPU time	146.86 seconds
Started	Oct 15 09:35:26 AM UTC 24
Finished	Oct 15 09:37:56 AM UTC 24
Peak memory	271056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583069575 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.1583069575
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.1097796240
Short name	T1063
Test name
Test status
Simulation time	42286800 ps
CPU time	20.94 seconds
Started	Oct 15 09:35:29 AM UTC 24
Finished	Oct 15 09:35:52 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097796240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1097796240
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1993259847
Short name	T1106
Test name
Test status
Simulation time	134308100 ps
CPU time	157.21 seconds
Started	Oct 15 09:35:27 AM UTC 24
Finished	Oct 15 09:38:07 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993259847 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.1993259847
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.3872173810
Short name	T1070
Test name
Test status
Simulation time	13792800 ps
CPU time	26.2 seconds
Started	Oct 15 09:35:33 AM UTC 24
Finished	Oct 15 09:36:00 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872173810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3872173810
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3799632653
Short name	T1114
Test name
Test status
Simulation time	56775300 ps
CPU time	173.51 seconds
Started	Oct 15 09:35:32 AM UTC 24
Finished	Oct 15 09:38:28 AM UTC 24
Peak memory	270648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799632653 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.3799632653
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.612562704
Short name	T1069
Test name
Test status
Simulation time	16587600 ps
CPU time	21.17 seconds
Started	Oct 15 09:35:37 AM UTC 24
Finished	Oct 15 09:36:00 AM UTC 24
Peak memory	284832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612562704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.612562704
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1403110285
Short name	T1111
Test name
Test status
Simulation time	147317900 ps
CPU time	165.37 seconds
Started	Oct 15 09:35:37 AM UTC 24
Finished	Oct 15 09:38:25 AM UTC 24
Peak memory	275020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403110285 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.1403110285
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.9601461
Short name	T1072
Test name
Test status
Simulation time	37637600 ps
CPU time	23.75 seconds
Started	Oct 15 09:35:39 AM UTC 24
Finished	Oct 15 09:36:04 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9601461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.9601461
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3522482065
Short name	T1113
Test name
Test status
Simulation time	144009800 ps
CPU time	166.38 seconds
Started	Oct 15 09:35:38 AM UTC 24
Finished	Oct 15 09:38:27 AM UTC 24
Peak memory	270712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522482065 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.3522482065
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.554862375
Short name	T533
Test name
Test status
Simulation time	156283000 ps
CPU time	22.57 seconds
Started	Oct 15 08:53:15 AM UTC 24
Finished	Oct 15 08:53:39 AM UTC 24
Peak memory	274944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554862375 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.554862375
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.3212435933
Short name	T532
Test name
Test status
Simulation time	27064900 ps
CPU time	32.01 seconds
Started	Oct 15 08:53:02 AM UTC 24
Finished	Oct 15 08:53:35 AM UTC 24
Peak memory	284764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212435933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.3212435933
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3045588780
Short name	T127
Test name
Test status
Simulation time	22088800 ps
CPU time	36.31 seconds
Started	Oct 15 08:52:37 AM UTC 24
Finished	Oct 15 08:53:14 AM UTC 24
Peak memory	285440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3045588780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c trl_disable.3045588780
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.118925310
Short name	T987
Test name
Test status
Simulation time	24720291500 ps
CPU time	2616.2 seconds
Started	Oct 15 08:49:39 AM UTC 24
Finished	Oct 15 09:33:42 AM UTC 24
Peak memory	272908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118925310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.118925310
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.210685388
Short name	T515
Test name
Test status
Simulation time	2535460700 ps
CPU time	44.93 seconds
Started	Oct 15 08:49:21 AM UTC 24
Finished	Oct 15 08:50:08 AM UTC 24
Peak memory	272860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 0685388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch _code.210685388
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.867428943
Short name	T199
Test name
Test status
Simulation time	10015425200 ps
CPU time	112.37 seconds
Started	Oct 15 08:53:12 AM UTC 24
Finished	Oct 15 08:55:07 AM UTC 24
Peak memory	361020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=867428943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.867428943
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.605239369
Short name	T531
Test name
Test status
Simulation time	15557000 ps
CPU time	22.98 seconds
Started	Oct 15 08:53:09 AM UTC 24
Finished	Oct 15 08:53:33 AM UTC 24
Peak memory	269016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=605239369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7 .flash_ctrl_hw_read_seed_err.605239369
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3028104582
Short name	T516
Test name
Test status
Simulation time	6044190800 ps
CPU time	80.55 seconds
Started	Oct 15 08:49:05 AM UTC 24
Finished	Oct 15 08:50:27 AM UTC 24
Peak memory	272804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028104582 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.3028104582
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3844058114
Short name	T545
Test name
Test status
Simulation time	9873373900 ps
CPU time	331.89 seconds
Started	Oct 15 08:51:23 AM UTC 24
Finished	Oct 15 08:56:59 AM UTC 24
Peak memory	301624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3844058114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_intr_rd_slow_flash.3844058114
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3366018906
Short name	T525
Test name
Test status
Simulation time	2223519600 ps
CPU time	93.56 seconds
Started	Oct 15 08:51:22 AM UTC 24
Finished	Oct 15 08:52:57 AM UTC 24
Peak memory	270928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366018906 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.3366018906
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1538481227
Short name	T547
Test name
Test status
Simulation time	34696776200 ps
CPU time	315.69 seconds
Started	Oct 15 08:51:41 AM UTC 24
Finished	Oct 15 08:57:01 AM UTC 24
Peak memory	271168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538481227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1538481227
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1352967797
Short name	T519
Test name
Test status
Simulation time	1557978000 ps
CPU time	73.39 seconds
Started	Oct 15 08:49:41 AM UTC 24
Finished	Oct 15 08:50:57 AM UTC 24
Peak memory	270804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352967797 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1352967797
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3469031966
Short name	T530
Test name
Test status
Simulation time	47703100 ps
CPU time	17.42 seconds
Started	Oct 15 08:53:05 AM UTC 24
Finished	Oct 15 08:53:23 AM UTC 24
Peak memory	270872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3469031966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_lcmgr_intg.3469031966
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1270356747
Short name	T93
Test name
Test status
Simulation time	26444729000 ps
CPU time	458.68 seconds
Started	Oct 15 08:49:07 AM UTC 24
Finished	Oct 15 08:56:52 AM UTC 24
Peak memory	283172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1270356747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.1270356747
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1426656518
Short name	T524
Test name
Test status
Simulation time	277712800 ps
CPU time	187.97 seconds
Started	Oct 15 08:49:06 AM UTC 24
Finished	Oct 15 08:52:17 AM UTC 24
Peak memory	270836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426656518 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.1426656518
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1549949488
Short name	T544
Test name
Test status
Simulation time	385210400 ps
CPU time	473.19 seconds
Started	Oct 15 08:48:59 AM UTC 24
Finished	Oct 15 08:56:57 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549949488 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1549949488
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.647552596
Short name	T538
Test name
Test status
Simulation time	2440169000 ps
CPU time	143.6 seconds
Started	Oct 15 08:52:17 AM UTC 24
Finished	Oct 15 08:54:43 AM UTC 24
Peak memory	270932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647552596 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.647552596
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3906945350
Short name	T161
Test name
Test status
Simulation time	3312114900 ps
CPU time	1157.97 seconds
Started	Oct 15 08:48:59 AM UTC 24
Finished	Oct 15 09:08:30 AM UTC 24
Peak memory	293460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906945350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3906945350
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.932590746
Short name	T528
Test name
Test status
Simulation time	63885700 ps
CPU time	36.02 seconds
Started	Oct 15 08:52:33 AM UTC 24
Finished	Oct 15 08:53:11 AM UTC 24
Peak memory	287432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932590746 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.932590746
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.2809098156
Short name	T523
Test name
Test status
Simulation time	464316700 ps
CPU time	121.97 seconds
Started	Oct 15 08:50:28 AM UTC 24
Finished	Oct 15 08:52:32 AM UTC 24
Peak memory	291552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2809098156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.2809098156
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.827605392
Short name	T534
Test name
Test status
Simulation time	621784500 ps
CPU time	160.54 seconds
Started	Oct 15 08:50:57 AM UTC 24
Finished	Oct 15 08:53:41 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827605392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.827605392
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.303073883
Short name	T208
Test name
Test status
Simulation time	1090876000 ps
CPU time	113.74 seconds
Started	Oct 15 08:50:33 AM UTC 24
Finished	Oct 15 08:52:29 AM UTC 24
Peak memory	305988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=303073883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ ctrl_ro_serr.303073883
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1696328967
Short name	T546
Test name
Test status
Simulation time	6160757100 ps
CPU time	386.52 seconds
Started	Oct 15 08:50:29 AM UTC 24
Finished	Oct 15 08:57:00 AM UTC 24
Peak memory	324304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696328967 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.1696328967
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3002347780
Short name	T207
Test name
Test status
Simulation time	1769249100 ps
CPU time	243.41 seconds
Started	Oct 15 08:51:09 AM UTC 24
Finished	Oct 15 08:55:16 AM UTC 24
Peak memory	299816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3002347780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.flash_ctrl_rw_derr.3002347780
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2420698567
Short name	T529
Test name
Test status
Simulation time	81761000 ps
CPU time	44.01 seconds
Started	Oct 15 08:52:29 AM UTC 24
Finished	Oct 15 08:53:15 AM UTC 24
Peak memory	287560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2420698567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct rl_rw_evict_all_en.2420698567
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.3874653086
Short name	T535
Test name
Test status
Simulation time	3294221300 ps
CPU time	207.86 seconds
Started	Oct 15 08:50:39 AM UTC 24
Finished	Oct 15 08:54:10 AM UTC 24
Peak memory	305860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3874653086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.3874653086
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3696061122
Short name	T536
Test name
Test status
Simulation time	409349200 ps
CPU time	82.82 seconds
Started	Oct 15 08:52:58 AM UTC 24
Finished	Oct 15 08:54:23 AM UTC 24
Peak memory	274912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696061122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3696061122
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.1865494123
Short name	T527
Test name
Test status
Simulation time	41677100 ps
CPU time	252.08 seconds
Started	Oct 15 08:48:52 AM UTC 24
Finished	Oct 15 08:53:08 AM UTC 24
Peak memory	289420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865494123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1865494123
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.4135668436
Short name	T526
Test name
Test status
Simulation time	3894205000 ps
CPU time	172.38 seconds
Started	Oct 15 08:50:09 AM UTC 24
Finished	Oct 15 08:53:04 AM UTC 24
Peak memory	270940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4135668436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.4135668436
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.2109362207
Short name	T1074
Test name
Test status
Simulation time	28850500 ps
CPU time	23.49 seconds
Started	Oct 15 09:35:42 AM UTC 24
Finished	Oct 15 09:36:07 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109362207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2109362207
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.964903831
Short name	T1103
Test name
Test status
Simulation time	114171500 ps
CPU time	134.34 seconds
Started	Oct 15 09:35:40 AM UTC 24
Finished	Oct 15 09:37:57 AM UTC 24
Peak memory	274928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964903831 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.964903831
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.1838547359
Short name	T1073
Test name
Test status
Simulation time	31893900 ps
CPU time	17.62 seconds
Started	Oct 15 09:35:47 AM UTC 24
Finished	Oct 15 09:36:06 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838547359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1838547359
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3240218276
Short name	T1116
Test name
Test status
Simulation time	38736500 ps
CPU time	172.43 seconds
Started	Oct 15 09:35:42 AM UTC 24
Finished	Oct 15 09:38:38 AM UTC 24
Peak memory	271052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240218276 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.3240218276
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.2911716119
Short name	T1077
Test name
Test status
Simulation time	26964500 ps
CPU time	21.32 seconds
Started	Oct 15 09:35:50 AM UTC 24
Finished	Oct 15 09:36:13 AM UTC 24
Peak memory	284828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911716119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2911716119
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.3405672635
Short name	T1117
Test name
Test status
Simulation time	37238300 ps
CPU time	171.81 seconds
Started	Oct 15 09:35:47 AM UTC 24
Finished	Oct 15 09:38:41 AM UTC 24
Peak memory	275340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405672635 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.3405672635
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.610290311
Short name	T1076
Test name
Test status
Simulation time	22966800 ps
CPU time	18.14 seconds
Started	Oct 15 09:35:51 AM UTC 24
Finished	Oct 15 09:36:10 AM UTC 24
Peak memory	284768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610290311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.610290311
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.961052216
Short name	T1115
Test name
Test status
Simulation time	81625200 ps
CPU time	164.75 seconds
Started	Oct 15 09:35:50 AM UTC 24
Finished	Oct 15 09:38:37 AM UTC 24
Peak memory	275208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961052216 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.961052216
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3533823604
Short name	T1078
Test name
Test status
Simulation time	15649100 ps
CPU time	23.34 seconds
Started	Oct 15 09:35:52 AM UTC 24
Finished	Oct 15 09:36:17 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533823604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3533823604
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.208650195
Short name	T1108
Test name
Test status
Simulation time	43076200 ps
CPU time	133.99 seconds
Started	Oct 15 09:35:52 AM UTC 24
Finished	Oct 15 09:38:08 AM UTC 24
Peak memory	271048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208650195 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.208650195
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.1946973535
Short name	T1080
Test name
Test status
Simulation time	42976700 ps
CPU time	23.56 seconds
Started	Oct 15 09:35:54 AM UTC 24
Finished	Oct 15 09:36:19 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946973535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1946973535
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1562104548
Short name	T1121
Test name
Test status
Simulation time	39075700 ps
CPU time	182.57 seconds
Started	Oct 15 09:35:53 AM UTC 24
Finished	Oct 15 09:38:59 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562104548 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.1562104548
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1467916258
Short name	T1079
Test name
Test status
Simulation time	84519200 ps
CPU time	18.9 seconds
Started	Oct 15 09:35:57 AM UTC 24
Finished	Oct 15 09:36:17 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467916258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1467916258
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1465095196
Short name	T1112
Test name
Test status
Simulation time	137236200 ps
CPU time	147.81 seconds
Started	Oct 15 09:35:57 AM UTC 24
Finished	Oct 15 09:38:27 AM UTC 24
Peak memory	273100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465095196 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.1465095196
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3084513489
Short name	T1082
Test name
Test status
Simulation time	15822400 ps
CPU time	19.38 seconds
Started	Oct 15 09:36:01 AM UTC 24
Finished	Oct 15 09:36:22 AM UTC 24
Peak memory	284704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084513489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3084513489
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2385588326
Short name	T1122
Test name
Test status
Simulation time	143321300 ps
CPU time	194.81 seconds
Started	Oct 15 09:35:58 AM UTC 24
Finished	Oct 15 09:39:16 AM UTC 24
Peak memory	270860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385588326 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.2385588326
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.501341440
Short name	T1084
Test name
Test status
Simulation time	28777200 ps
CPU time	22.14 seconds
Started	Oct 15 09:36:03 AM UTC 24
Finished	Oct 15 09:36:26 AM UTC 24
Peak memory	294944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501341440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.501341440
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.1914642007
Short name	T1118
Test name
Test status
Simulation time	40812100 ps
CPU time	159.51 seconds
Started	Oct 15 09:36:01 AM UTC 24
Finished	Oct 15 09:38:43 AM UTC 24
Peak memory	270840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914642007 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.1914642007
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.27554988
Short name	T1083
Test name
Test status
Simulation time	28755500 ps
CPU time	16.32 seconds
Started	Oct 15 09:36:06 AM UTC 24
Finished	Oct 15 09:36:24 AM UTC 24
Peak memory	294940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27554988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.27554988
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.2306309266
Short name	T1119
Test name
Test status
Simulation time	38447800 ps
CPU time	158.86 seconds
Started	Oct 15 09:36:05 AM UTC 24
Finished	Oct 15 09:38:47 AM UTC 24
Peak memory	270904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306309266 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.2306309266
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3504035362
Short name	T559
Test name
Test status
Simulation time	265450100 ps
CPU time	26.26 seconds
Started	Oct 15 08:57:32 AM UTC 24
Finished	Oct 15 08:58:00 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504035362 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3504035362
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1437846764
Short name	T555
Test name
Test status
Simulation time	14177100 ps
CPU time	17.84 seconds
Started	Oct 15 08:57:18 AM UTC 24
Finished	Oct 15 08:57:37 AM UTC 24
Peak memory	284696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437846764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1437846764
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1680750492
Short name	T128
Test name
Test status
Simulation time	25925100 ps
CPU time	26.73 seconds
Started	Oct 15 08:57:16 AM UTC 24
Finished	Oct 15 08:57:44 AM UTC 24
Peak memory	285304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1680750492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c trl_disable.1680750492
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3170081152
Short name	T1124
Test name
Test status
Simulation time	8733882900 ps
CPU time	2804.75 seconds
Started	Oct 15 08:54:35 AM UTC 24
Finished	Oct 15 09:41:50 AM UTC 24
Peak memory	274900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170081152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.3170081152
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.2478148321
Short name	T662
Test name
Test status
Simulation time	1476136300 ps
CPU time	1130.16 seconds
Started	Oct 15 08:54:27 AM UTC 24
Finished	Oct 15 09:13:30 AM UTC 24
Peak memory	285164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478148321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2478148321
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3459880435
Short name	T540
Test name
Test status
Simulation time	1534683200 ps
CPU time	45.85 seconds
Started	Oct 15 08:54:24 AM UTC 24
Finished	Oct 15 08:55:11 AM UTC 24
Peak memory	272852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34 59880435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetc h_code.3459880435
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2264037874
Short name	T114
Test name
Test status
Simulation time	10039326500 ps
CPU time	126.35 seconds
Started	Oct 15 08:57:28 AM UTC 24
Finished	Oct 15 08:59:37 AM UTC 24
Peak memory	279060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2264037874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2264037874
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.284309867
Short name	T285
Test name
Test status
Simulation time	48433800 ps
CPU time	15 seconds
Started	Oct 15 08:57:26 AM UTC 24
Finished	Oct 15 08:57:42 AM UTC 24
Peak memory	270848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=284309867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8 .flash_ctrl_hw_read_seed_err.284309867
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2561125865
Short name	T409
Test name
Test status
Simulation time	160186282500 ps
CPU time	786.55 seconds
Started	Oct 15 08:53:40 AM UTC 24
Finished	Oct 15 09:06:56 AM UTC 24
Peak memory	274944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561125865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.2561125865
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.44303185
Short name	T541
Test name
Test status
Simulation time	5278152700 ps
CPU time	143.76 seconds
Started	Oct 15 08:53:36 AM UTC 24
Finished	Oct 15 08:56:02 AM UTC 24
Peak memory	274852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44303185 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.44303185
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1003852915
Short name	T344
Test name
Test status
Simulation time	527703700 ps
CPU time	150.19 seconds
Started	Oct 15 08:56:26 AM UTC 24
Finished	Oct 15 08:58:58 AM UTC 24
Peak memory	306012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003852915 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.1003852915
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.887971465
Short name	T341
Test name
Test status
Simulation time	5918977400 ps
CPU time	175.82 seconds
Started	Oct 15 08:56:53 AM UTC 24
Finished	Oct 15 08:59:52 AM UTC 24
Peak memory	301628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=887971465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_rd_slow_flash.887971465
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.496255540
Short name	T561
Test name
Test status
Simulation time	4415802200 ps
CPU time	104.45 seconds
Started	Oct 15 08:56:33 AM UTC 24
Finished	Oct 15 08:58:20 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496255540 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.496255540
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.4019327394
Short name	T574
Test name
Test status
Simulation time	44534371000 ps
CPU time	263.5 seconds
Started	Oct 15 08:56:57 AM UTC 24
Finished	Oct 15 09:01:25 AM UTC 24
Peak memory	270928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019327394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.4019327394
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.946553202
Short name	T542
Test name
Test status
Simulation time	2202908100 ps
CPU time	97.24 seconds
Started	Oct 15 08:54:44 AM UTC 24
Finished	Oct 15 08:56:25 AM UTC 24
Peak memory	270928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946553202 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.946553202
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1732597384
Short name	T557
Test name
Test status
Simulation time	26100900 ps
CPU time	27.2 seconds
Started	Oct 15 08:57:19 AM UTC 24
Finished	Oct 15 08:57:47 AM UTC 24
Peak memory	274964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1732597384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_lcmgr_intg.1732597384
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3658770172
Short name	T550
Test name
Test status
Simulation time	2083193900 ps
CPU time	182.95 seconds
Started	Oct 15 08:54:11 AM UTC 24
Finished	Oct 15 08:57:17 AM UTC 24
Peak memory	274964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3658770172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.3658770172
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.2078564359
Short name	T551
Test name
Test status
Simulation time	153054500 ps
CPU time	212.84 seconds
Started	Oct 15 08:53:42 AM UTC 24
Finished	Oct 15 08:57:18 AM UTC 24
Peak memory	270836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078564359 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.2078564359
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.4083739410
Short name	T539
Test name
Test status
Simulation time	105141300 ps
CPU time	71.55 seconds
Started	Oct 15 08:53:34 AM UTC 24
Finished	Oct 15 08:54:48 AM UTC 24
Peak memory	274840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083739410 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.4083739410
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.2861229984
Short name	T552
Test name
Test status
Simulation time	32985800 ps
CPU time	23.52 seconds
Started	Oct 15 08:57:01 AM UTC 24
Finished	Oct 15 08:57:25 AM UTC 24
Peak memory	270800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861229984 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.2861229984
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3448930709
Short name	T94
Test name
Test status
Simulation time	6855499500 ps
CPU time	857.22 seconds
Started	Oct 15 08:53:24 AM UTC 24
Finished	Oct 15 09:07:51 AM UTC 24
Peak memory	293332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448930709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3448930709
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1562743040
Short name	T560
Test name
Test status
Simulation time	189446500 ps
CPU time	50.58 seconds
Started	Oct 15 08:57:13 AM UTC 24
Finished	Oct 15 08:58:05 AM UTC 24
Peak memory	287440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562743040 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.1562743040
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.2730863485
Short name	T553
Test name
Test status
Simulation time	1068183400 ps
CPU time	136.63 seconds
Started	Oct 15 08:55:08 AM UTC 24
Finished	Oct 15 08:57:27 AM UTC 24
Peak memory	291400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2730863485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.2730863485
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2420520638
Short name	T562
Test name
Test status
Simulation time	1307111000 ps
CPU time	171.02 seconds
Started	Oct 15 08:56:00 AM UTC 24
Finished	Oct 15 08:58:54 AM UTC 24
Peak memory	291664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420520638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2420520638
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.4189842455
Short name	T558
Test name
Test status
Simulation time	581335600 ps
CPU time	149.63 seconds
Started	Oct 15 08:55:17 AM UTC 24
Finished	Oct 15 08:57:49 AM UTC 24
Peak memory	291716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4189842455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_ro_serr.4189842455
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.3049269361
Short name	T601
Test name
Test status
Simulation time	17353725100 ps
CPU time	576.73 seconds
Started	Oct 15 08:55:13 AM UTC 24
Finished	Oct 15 09:04:57 AM UTC 24
Peak memory	330644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049269361 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.3049269361
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1459561543
Short name	T563
Test name
Test status
Simulation time	1825773600 ps
CPU time	193.2 seconds
Started	Oct 15 08:56:02 AM UTC 24
Finished	Oct 15 08:59:18 AM UTC 24
Peak memory	295640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1459561543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_rw_derr.1459561543
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3255206464
Short name	T220
Test name
Test status
Simulation time	120748600 ps
CPU time	55.22 seconds
Started	Oct 15 08:57:01 AM UTC 24
Finished	Oct 15 08:57:57 AM UTC 24
Peak memory	285424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255206464 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.3255206464
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.2998282870
Short name	T370
Test name
Test status
Simulation time	250446100 ps
CPU time	43.58 seconds
Started	Oct 15 08:57:02 AM UTC 24
Finished	Oct 15 08:57:47 AM UTC 24
Peak memory	285384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2998282870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct rl_rw_evict_all_en.2998282870
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.3242559832
Short name	T564
Test name
Test status
Simulation time	1459960400 ps
CPU time	219.83 seconds
Started	Oct 15 08:55:57 AM UTC 24
Finished	Oct 15 08:59:40 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3242559832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.3242559832
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.1832129734
Short name	T549
Test name
Test status
Simulation time	47690200 ps
CPU time	236.52 seconds
Started	Oct 15 08:53:15 AM UTC 24
Finished	Oct 15 08:57:15 AM UTC 24
Peak memory	289236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832129734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1832129734
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3635633397
Short name	T554
Test name
Test status
Simulation time	3854404700 ps
CPU time	160.06 seconds
Started	Oct 15 08:54:48 AM UTC 24
Finished	Oct 15 08:57:31 AM UTC 24
Peak memory	270944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3635633397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.3635633397
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.4008298094
Short name	T580
Test name
Test status
Simulation time	71550600 ps
CPU time	21.78 seconds
Started	Oct 15 09:01:16 AM UTC 24
Finished	Oct 15 09:01:39 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008298094 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.4008298094
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.943204756
Short name	T572
Test name
Test status
Simulation time	24041800 ps
CPU time	23.13 seconds
Started	Oct 15 09:00:50 AM UTC 24
Finished	Oct 15 09:01:15 AM UTC 24
Peak memory	284700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943204756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.943204756
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.1495221078
Short name	T571
Test name
Test status
Simulation time	28817100 ps
CPU time	28.76 seconds
Started	Oct 15 09:00:35 AM UTC 24
Finished	Oct 15 09:01:05 AM UTC 24
Peak memory	285312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1495221078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c trl_disable.1495221078
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1768927651
Short name	T1125
Test name
Test status
Simulation time	2797532900 ps
CPU time	2906.34 seconds
Started	Oct 15 08:58:06 AM UTC 24
Finished	Oct 15 09:47:04 AM UTC 24
Peak memory	275632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768927651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.1768927651
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.302943240
Short name	T708
Test name
Test status
Simulation time	623997900 ps
CPU time	1155.06 seconds
Started	Oct 15 08:58:01 AM UTC 24
Finished	Oct 15 09:17:28 AM UTC 24
Peak memory	285156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302943240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.302943240
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1249068295
Short name	T69
Test name
Test status
Simulation time	603348400 ps
CPU time	44.18 seconds
Started	Oct 15 08:57:59 AM UTC 24
Finished	Oct 15 08:58:45 AM UTC 24
Peak memory	272852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12 49068295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc h_code.1249068295
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1694395977
Short name	T589
Test name
Test status
Simulation time	10018178700 ps
CPU time	129.24 seconds
Started	Oct 15 09:01:16 AM UTC 24
Finished	Oct 15 09:03:27 AM UTC 24
Peak memory	318116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1694395977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1694395977
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3164915259
Short name	T579
Test name
Test status
Simulation time	18670000 ps
CPU time	28.76 seconds
Started	Oct 15 09:01:07 AM UTC 24
Finished	Oct 15 09:01:38 AM UTC 24
Peak memory	274960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3164915259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3164915259
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.242465569
Short name	T187
Test name
Test status
Simulation time	420314780300 ps
CPU time	789.5 seconds
Started	Oct 15 08:57:47 AM UTC 24
Finished	Oct 15 09:11:06 AM UTC 24
Peak memory	274880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242465569 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.242465569
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.1705201180
Short name	T582
Test name
Test status
Simulation time	3061673700 ps
CPU time	233.7 seconds
Started	Oct 15 08:57:44 AM UTC 24
Finished	Oct 15 09:01:41 AM UTC 24
Peak memory	272808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705201180 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.1705201180
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3820869838
Short name	T348
Test name
Test status
Simulation time	2352970600 ps
CPU time	216.88 seconds
Started	Oct 15 08:59:38 AM UTC 24
Finished	Oct 15 09:03:18 AM UTC 24
Peak memory	301720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820869838 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.3820869838
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1359761470
Short name	T585
Test name
Test status
Simulation time	11485880300 ps
CPU time	186.21 seconds
Started	Oct 15 08:59:53 AM UTC 24
Finished	Oct 15 09:03:02 AM UTC 24
Peak memory	303692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1359761470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_intr_rd_slow_flash.1359761470
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2771864526
Short name	T573
Test name
Test status
Simulation time	4017793900 ps
CPU time	92.29 seconds
Started	Oct 15 08:59:41 AM UTC 24
Finished	Oct 15 09:01:15 AM UTC 24
Peak memory	271056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771864526 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.2771864526
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.114693126
Short name	T600
Test name
Test status
Simulation time	70765906800 ps
CPU time	273.27 seconds
Started	Oct 15 08:59:55 AM UTC 24
Finished	Oct 15 09:04:32 AM UTC 24
Peak memory	270928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114693126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.114693126
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2476218835
Short name	T567
Test name
Test status
Simulation time	3493356700 ps
CPU time	109.94 seconds
Started	Oct 15 08:58:21 AM UTC 24
Finished	Oct 15 09:00:14 AM UTC 24
Peak memory	274896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476218835 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2476218835
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2811520155
Short name	T575
Test name
Test status
Simulation time	45619600 ps
CPU time	19.37 seconds
Started	Oct 15 09:01:06 AM UTC 24
Finished	Oct 15 09:01:27 AM UTC 24
Peak memory	272916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2811520155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_lcmgr_intg.2811520155
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.3356281500
Short name	T565
Test name
Test status
Simulation time	1705597800 ps
CPU time	122.46 seconds
Started	Oct 15 08:57:50 AM UTC 24
Finished	Oct 15 08:59:54 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3356281500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.3356281500
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.753947342
Short name	T98
Test name
Test status
Simulation time	78458800 ps
CPU time	167.96 seconds
Started	Oct 15 08:57:48 AM UTC 24
Finished	Oct 15 09:00:38 AM UTC 24
Peak memory	270648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753947342 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.753947342
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.788722403
Short name	T591
Test name
Test status
Simulation time	57840000 ps
CPU time	349.18 seconds
Started	Oct 15 08:57:42 AM UTC 24
Finished	Oct 15 09:03:36 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788722403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.788722403
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.4100512431
Short name	T569
Test name
Test status
Simulation time	92086100 ps
CPU time	23.4 seconds
Started	Oct 15 09:00:09 AM UTC 24
Finished	Oct 15 09:00:34 AM UTC 24
Peak memory	275024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100512431 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.4100512431
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.129303641
Short name	T755
Test name
Test status
Simulation time	1506845700 ps
CPU time	1438.21 seconds
Started	Oct 15 08:57:39 AM UTC 24
Finished	Oct 15 09:21:53 AM UTC 24
Peak memory	297620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129303641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.129303641
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3407505349
Short name	T356
Test name
Test status
Simulation time	75422900 ps
CPU time	43.79 seconds
Started	Oct 15 09:00:30 AM UTC 24
Finished	Oct 15 09:01:15 AM UTC 24
Peak memory	289620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407505349 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.3407505349
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1336131464
Short name	T568
Test name
Test status
Simulation time	2231040700 ps
CPU time	110.34 seconds
Started	Oct 15 08:58:37 AM UTC 24
Finished	Oct 15 09:00:29 AM UTC 24
Peak memory	291604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1336131464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.1336131464
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.1827376721
Short name	T578
Test name
Test status
Simulation time	2347731600 ps
CPU time	134.19 seconds
Started	Oct 15 08:59:19 AM UTC 24
Finished	Oct 15 09:01:36 AM UTC 24
Peak memory	291516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827376721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1827376721
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.1844905712
Short name	T581
Test name
Test status
Simulation time	2567927000 ps
CPU time	161.1 seconds
Started	Oct 15 08:58:55 AM UTC 24
Finished	Oct 15 09:01:39 AM UTC 24
Peak memory	291540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1844905712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash _ctrl_ro_serr.1844905712
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.672388769
Short name	T618
Test name
Test status
Simulation time	4154039700 ps
CPU time	479.92 seconds
Started	Oct 15 08:58:45 AM UTC 24
Finished	Oct 15 09:06:51 AM UTC 24
Peak memory	330432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672388769 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.672388769
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.397048670
Short name	T587
Test name
Test status
Simulation time	1490910100 ps
CPU time	217.39 seconds
Started	Oct 15 08:59:25 AM UTC 24
Finished	Oct 15 09:03:07 AM UTC 24
Peak memory	291524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=397048670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_rw_derr.397048670
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.629916761
Short name	T372
Test name
Test status
Simulation time	71293000 ps
CPU time	50.57 seconds
Started	Oct 15 09:00:15 AM UTC 24
Finished	Oct 15 09:01:07 AM UTC 24
Peak memory	287632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629916761 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.629916761
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1145345108
Short name	T570
Test name
Test status
Simulation time	31481000 ps
CPU time	33.48 seconds
Started	Oct 15 09:00:15 AM UTC 24
Finished	Oct 15 09:00:50 AM UTC 24
Peak memory	287428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1145345108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct rl_rw_evict_all_en.1145345108
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.2881463619
Short name	T583
Test name
Test status
Simulation time	1143389800 ps
CPU time	205.3 seconds
Started	Oct 15 08:58:59 AM UTC 24
Finished	Oct 15 09:02:28 AM UTC 24
Peak memory	305988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2881463619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.2881463619
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3312578253
Short name	T584
Test name
Test status
Simulation time	922410400 ps
CPU time	114.84 seconds
Started	Oct 15 09:00:39 AM UTC 24
Finished	Oct 15 09:02:36 AM UTC 24
Peak memory	275044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312578253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3312578253
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.4260815087
Short name	T576
Test name
Test status
Simulation time	690326600 ps
CPU time	227.65 seconds
Started	Oct 15 08:57:37 AM UTC 24
Finished	Oct 15 09:01:28 AM UTC 24
Peak memory	291348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260815087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.4260815087
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1751949482
Short name	T577
Test name
Test status
Simulation time	21203954500 ps
CPU time	186.4 seconds
Started	Oct 15 08:58:21 AM UTC 24
Finished	Oct 15 09:01:31 AM UTC 24
Peak memory	271056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1751949482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.1751949482
Directory	/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest

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