| T1094 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3116290662 |
|
|
Feb 09 06:24:01 AM UTC 25 |
Feb 09 06:24:30 AM UTC 25 |
29136800 ps |
| T1095 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.4119755843 |
|
|
Feb 09 06:24:12 AM UTC 25 |
Feb 09 06:24:31 AM UTC 25 |
15149900 ps |
| T1096 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3212467014 |
|
|
Feb 09 06:24:10 AM UTC 25 |
Feb 09 06:24:31 AM UTC 25 |
24826300 ps |
| T1097 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.574064843 |
|
|
Feb 09 06:22:16 AM UTC 25 |
Feb 09 06:24:32 AM UTC 25 |
150460600 ps |
| T1098 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.1471749942 |
|
|
Feb 09 06:24:06 AM UTC 25 |
Feb 09 06:24:33 AM UTC 25 |
24230500 ps |
| T1099 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2807961695 |
|
|
Feb 09 06:21:46 AM UTC 25 |
Feb 09 06:24:35 AM UTC 25 |
154772400 ps |
| T1100 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3083909767 |
|
|
Feb 09 06:24:17 AM UTC 25 |
Feb 09 06:24:39 AM UTC 25 |
26515100 ps |
| T1101 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.330822351 |
|
|
Feb 09 06:24:15 AM UTC 25 |
Feb 09 06:24:44 AM UTC 25 |
63688300 ps |
| T1102 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.300493382 |
|
|
Feb 09 06:24:22 AM UTC 25 |
Feb 09 06:24:48 AM UTC 25 |
21685200 ps |
| T1103 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2739728857 |
|
|
Feb 09 06:22:04 AM UTC 25 |
Feb 09 06:24:48 AM UTC 25 |
152587900 ps |
| T1104 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.3697486343 |
|
|
Feb 09 06:24:25 AM UTC 25 |
Feb 09 06:24:50 AM UTC 25 |
45130900 ps |
| T1105 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.2912815718 |
|
|
Feb 09 06:20:51 AM UTC 25 |
Feb 09 06:25:00 AM UTC 25 |
3309670700 ps |
| T1106 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.1459134002 |
|
|
Feb 09 06:22:33 AM UTC 25 |
Feb 09 06:25:09 AM UTC 25 |
122139900 ps |
| T1107 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.3859026268 |
|
|
Feb 09 06:22:52 AM UTC 25 |
Feb 09 06:25:18 AM UTC 25 |
132510400 ps |
| T1108 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1709653143 |
|
|
Feb 09 06:19:46 AM UTC 25 |
Feb 09 06:25:18 AM UTC 25 |
154993367600 ps |
| T1109 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2964276672 |
|
|
Feb 09 06:22:46 AM UTC 25 |
Feb 09 06:25:33 AM UTC 25 |
40673700 ps |
| T1110 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.665896497 |
|
|
Feb 09 06:22:44 AM UTC 25 |
Feb 09 06:25:47 AM UTC 25 |
29101500 ps |
| T1111 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4182986307 |
|
|
Feb 09 06:23:19 AM UTC 25 |
Feb 09 06:25:55 AM UTC 25 |
139648300 ps |
| T1112 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3350299839 |
|
|
Feb 09 06:22:11 AM UTC 25 |
Feb 09 06:25:56 AM UTC 25 |
208610300 ps |
| T1113 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.4230574216 |
|
|
Feb 09 06:23:43 AM UTC 25 |
Feb 09 06:25:59 AM UTC 25 |
657705100 ps |
| T1114 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.4113397917 |
|
|
Feb 09 06:23:29 AM UTC 25 |
Feb 09 06:26:07 AM UTC 25 |
74504400 ps |
| T1115 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3784625470 |
|
|
Feb 09 06:23:23 AM UTC 25 |
Feb 09 06:26:07 AM UTC 25 |
71440000 ps |
| T1116 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.954408443 |
|
|
Feb 09 06:23:41 AM UTC 25 |
Feb 09 06:26:08 AM UTC 25 |
80128200 ps |
| T1117 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3690691813 |
|
|
Feb 09 06:23:03 AM UTC 25 |
Feb 09 06:26:11 AM UTC 25 |
179182200 ps |
| T1118 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1987238439 |
|
|
Feb 09 06:23:27 AM UTC 25 |
Feb 09 06:26:16 AM UTC 25 |
78418000 ps |
| T1119 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1995331967 |
|
|
Feb 09 06:23:10 AM UTC 25 |
Feb 09 06:26:18 AM UTC 25 |
38933800 ps |
| T1120 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1007645681 |
|
|
Feb 09 06:23:01 AM UTC 25 |
Feb 09 06:26:19 AM UTC 25 |
39107600 ps |
| T1121 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.594344982 |
|
|
Feb 09 06:01:13 AM UTC 25 |
Feb 09 06:26:19 AM UTC 25 |
304908100 ps |
| T1122 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1312004688 |
|
|
Feb 09 06:23:17 AM UTC 25 |
Feb 09 06:26:20 AM UTC 25 |
42130600 ps |
| T398 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.1953753850 |
|
|
Feb 09 06:23:29 AM UTC 25 |
Feb 09 06:26:21 AM UTC 25 |
727660800 ps |
| T1123 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4021058596 |
|
|
Feb 09 06:20:09 AM UTC 25 |
Feb 09 06:26:21 AM UTC 25 |
119173737000 ps |
| T1124 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.4179592912 |
|
|
Feb 09 06:23:43 AM UTC 25 |
Feb 09 06:26:23 AM UTC 25 |
195460700 ps |
| T1125 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3899845227 |
|
|
Feb 09 06:24:13 AM UTC 25 |
Feb 09 06:26:25 AM UTC 25 |
602896600 ps |
| T1126 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.2193721811 |
|
|
Feb 09 06:23:48 AM UTC 25 |
Feb 09 06:26:31 AM UTC 25 |
303518900 ps |
| T1127 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.4042369093 |
|
|
Feb 09 06:23:50 AM UTC 25 |
Feb 09 06:26:34 AM UTC 25 |
38571700 ps |
| T1128 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1316818793 |
|
|
Feb 09 06:24:12 AM UTC 25 |
Feb 09 06:26:34 AM UTC 25 |
71092500 ps |
| T400 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.592157261 |
|
|
Feb 09 06:24:00 AM UTC 25 |
Feb 09 06:26:35 AM UTC 25 |
36260000 ps |
| T1129 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.4089204142 |
|
|
Feb 09 05:34:36 AM UTC 25 |
Feb 09 06:26:35 AM UTC 25 |
10091013400 ps |
| T1130 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.327537201 |
|
|
Feb 09 06:23:52 AM UTC 25 |
Feb 09 06:26:41 AM UTC 25 |
39135600 ps |
| T1131 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.15569815 |
|
|
Feb 09 06:24:06 AM UTC 25 |
Feb 09 06:26:42 AM UTC 25 |
74831200 ps |
| T1132 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3811484158 |
|
|
Feb 09 06:23:55 AM UTC 25 |
Feb 09 06:26:43 AM UTC 25 |
108453200 ps |
| T1133 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.2404495951 |
|
|
Feb 09 06:23:41 AM UTC 25 |
Feb 09 06:26:43 AM UTC 25 |
38173700 ps |
| T1134 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3917519573 |
|
|
Feb 09 06:24:07 AM UTC 25 |
Feb 09 06:26:45 AM UTC 25 |
43285600 ps |
| T1135 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1108486178 |
|
|
Feb 09 06:24:02 AM UTC 25 |
Feb 09 06:26:49 AM UTC 25 |
77763300 ps |
| T1136 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2377668384 |
|
|
Feb 09 06:24:02 AM UTC 25 |
Feb 09 06:26:52 AM UTC 25 |
152942600 ps |
| T1137 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1834606824 |
|
|
Feb 09 06:24:06 AM UTC 25 |
Feb 09 06:26:59 AM UTC 25 |
121517800 ps |
| T1138 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1500603762 |
|
|
Feb 09 06:24:01 AM UTC 25 |
Feb 09 06:27:00 AM UTC 25 |
147018300 ps |
| T1139 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2476345479 |
|
|
Feb 09 06:24:19 AM UTC 25 |
Feb 09 06:27:02 AM UTC 25 |
737978100 ps |
| T1140 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1848418725 |
|
|
Feb 09 06:24:16 AM UTC 25 |
Feb 09 06:27:14 AM UTC 25 |
75058100 ps |
| T1141 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1449571536 |
|
|
Feb 09 06:24:23 AM UTC 25 |
Feb 09 06:27:21 AM UTC 25 |
79698300 ps |
| T1142 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1773950233 |
|
|
Feb 09 05:43:19 AM UTC 25 |
Feb 09 06:34:08 AM UTC 25 |
3788087000 ps |
| T1143 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1434733608 |
|
|
Feb 09 06:07:35 AM UTC 25 |
Feb 09 06:36:18 AM UTC 25 |
2845104600 ps |
| T1144 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.961007066 |
|
|
Feb 09 05:46:56 AM UTC 25 |
Feb 09 06:37:57 AM UTC 25 |
1421916500 ps |
| T10 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.314910774 |
|
|
Feb 09 05:09:26 AM UTC 25 |
Feb 09 06:49:38 AM UTC 25 |
1338164300 ps |
| T11 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.46213295 |
|
|
Feb 09 05:02:11 AM UTC 25 |
Feb 09 06:55:50 AM UTC 25 |
2352644500 ps |
| T12 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.267237677 |
|
|
Feb 09 05:16:09 AM UTC 25 |
Feb 09 07:08:16 AM UTC 25 |
1514418900 ps |
| T69 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.4184603584 |
|
|
Feb 09 05:22:57 AM UTC 25 |
Feb 09 07:13:51 AM UTC 25 |
1724439100 ps |
| T142 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3315980796 |
|
|
Feb 09 05:29:45 AM UTC 25 |
Feb 09 07:30:58 AM UTC 25 |
2764684200 ps |
| T1145 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2613952565 |
|
|
Feb 09 03:41:44 AM UTC 25 |
Feb 09 03:42:09 AM UTC 25 |
15519200 ps |
| T250 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2689479230 |
|
|
Feb 09 03:41:41 AM UTC 25 |
Feb 09 03:42:10 AM UTC 25 |
25134500 ps |
| T1146 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.131957067 |
|
|
Feb 09 03:41:41 AM UTC 25 |
Feb 09 03:42:13 AM UTC 25 |
17726200 ps |
| T1147 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.88033769 |
|
|
Feb 09 03:41:41 AM UTC 25 |
Feb 09 03:42:13 AM UTC 25 |
78946400 ps |
| T127 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1962779331 |
|
|
Feb 09 03:41:41 AM UTC 25 |
Feb 09 03:42:19 AM UTC 25 |
60571900 ps |
| T75 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4056820414 |
|
|
Feb 09 03:42:11 AM UTC 25 |
Feb 09 03:42:31 AM UTC 25 |
44500200 ps |
| T237 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2625856794 |
|
|
Feb 09 03:42:04 AM UTC 25 |
Feb 09 03:42:32 AM UTC 25 |
63751300 ps |
| T1148 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1920645075 |
|
|
Feb 09 03:42:32 AM UTC 25 |
Feb 09 03:42:52 AM UTC 25 |
20679600 ps |
| T76 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.724929976 |
|
|
Feb 09 03:42:17 AM UTC 25 |
Feb 09 03:42:52 AM UTC 25 |
279484700 ps |
| T77 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2245637254 |
|
|
Feb 09 03:42:20 AM UTC 25 |
Feb 09 03:42:53 AM UTC 25 |
424907100 ps |
| T131 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1385178592 |
|
|
Feb 09 03:42:15 AM UTC 25 |
Feb 09 03:42:54 AM UTC 25 |
309285900 ps |
| T1149 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.211909984 |
|
|
Feb 09 03:42:33 AM UTC 25 |
Feb 09 03:42:59 AM UTC 25 |
72710200 ps |
| T130 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3959638459 |
|
|
Feb 09 03:42:27 AM UTC 25 |
Feb 09 03:42:59 AM UTC 25 |
711206100 ps |
| T257 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.670396155 |
|
|
Feb 09 03:42:47 AM UTC 25 |
Feb 09 03:43:05 AM UTC 25 |
14871500 ps |
| T238 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.71585175 |
|
|
Feb 09 03:42:53 AM UTC 25 |
Feb 09 03:43:10 AM UTC 25 |
151351100 ps |
| T1150 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1037268422 |
|
|
Feb 09 03:42:52 AM UTC 25 |
Feb 09 03:43:20 AM UTC 25 |
14303400 ps |
| T241 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2825413670 |
|
|
Feb 09 03:42:54 AM UTC 25 |
Feb 09 03:43:25 AM UTC 25 |
24385900 ps |
| T251 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2970881249 |
|
|
Feb 09 03:42:09 AM UTC 25 |
Feb 09 03:43:28 AM UTC 25 |
126338200 ps |
| T242 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4229529570 |
|
|
Feb 09 03:43:00 AM UTC 25 |
Feb 09 03:43:34 AM UTC 25 |
436437800 ps |
| T224 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.196404392 |
|
|
Feb 09 03:43:11 AM UTC 25 |
Feb 09 03:43:39 AM UTC 25 |
59830900 ps |
| T252 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.559342401 |
|
|
Feb 09 03:42:53 AM UTC 25 |
Feb 09 03:43:43 AM UTC 25 |
42847300 ps |
| T128 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.791063809 |
|
|
Feb 09 03:43:05 AM UTC 25 |
Feb 09 03:43:44 AM UTC 25 |
50606800 ps |
| T239 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1417738262 |
|
|
Feb 09 03:43:39 AM UTC 25 |
Feb 09 03:43:56 AM UTC 25 |
30837800 ps |
| T1151 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2591922682 |
|
|
Feb 09 03:43:25 AM UTC 25 |
Feb 09 03:43:57 AM UTC 25 |
27077900 ps |
| T339 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.4190801762 |
|
|
Feb 09 03:43:29 AM UTC 25 |
Feb 09 03:43:58 AM UTC 25 |
29524500 ps |
| T1152 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3343484272 |
|
|
Feb 09 03:43:34 AM UTC 25 |
Feb 09 03:43:58 AM UTC 25 |
28171300 ps |
| T1153 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2370841237 |
|
|
Feb 09 03:43:26 AM UTC 25 |
Feb 09 03:43:59 AM UTC 25 |
13580700 ps |
| T243 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1424545291 |
|
|
Feb 09 03:43:41 AM UTC 25 |
Feb 09 03:44:08 AM UTC 25 |
406491500 ps |
| T244 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2551457393 |
|
|
Feb 09 03:43:00 AM UTC 25 |
Feb 09 03:44:12 AM UTC 25 |
1836365200 ps |
| T1154 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.424520544 |
|
|
Feb 09 03:43:59 AM UTC 25 |
Feb 09 03:44:26 AM UTC 25 |
32670600 ps |
| T255 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3742346976 |
|
|
Feb 09 03:43:45 AM UTC 25 |
Feb 09 03:44:27 AM UTC 25 |
362070600 ps |
| T245 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4240909349 |
|
|
Feb 09 03:44:13 AM UTC 25 |
Feb 09 03:44:31 AM UTC 25 |
17577400 ps |
| T1155 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.607184300 |
|
|
Feb 09 03:44:00 AM UTC 25 |
Feb 09 03:44:31 AM UTC 25 |
24999700 ps |
| T253 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1949923003 |
|
|
Feb 09 03:43:58 AM UTC 25 |
Feb 09 03:44:32 AM UTC 25 |
181848000 ps |
| T129 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2791680183 |
|
|
Feb 09 03:43:58 AM UTC 25 |
Feb 09 03:44:32 AM UTC 25 |
47005200 ps |
| T225 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1913952970 |
|
|
Feb 09 03:43:58 AM UTC 25 |
Feb 09 03:44:32 AM UTC 25 |
52335500 ps |
| T1156 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3422105805 |
|
|
Feb 09 03:43:41 AM UTC 25 |
Feb 09 03:44:34 AM UTC 25 |
31574500 ps |
| T340 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3075588198 |
|
|
Feb 09 03:44:09 AM UTC 25 |
Feb 09 03:44:35 AM UTC 25 |
16164600 ps |
| T1157 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1106707952 |
|
|
Feb 09 03:44:12 AM UTC 25 |
Feb 09 03:44:40 AM UTC 25 |
52781200 ps |
| T254 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2918500367 |
|
|
Feb 09 03:42:14 AM UTC 25 |
Feb 09 03:44:41 AM UTC 25 |
13702294600 ps |
| T382 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1066102826 |
|
|
Feb 09 03:44:18 AM UTC 25 |
Feb 09 03:44:42 AM UTC 25 |
62656700 ps |
| T381 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1032647234 |
|
|
Feb 09 03:42:55 AM UTC 25 |
Feb 09 03:44:46 AM UTC 25 |
3016477000 ps |
| T1158 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3441962624 |
|
|
Feb 09 03:43:44 AM UTC 25 |
Feb 09 03:44:49 AM UTC 25 |
2908456700 ps |
| T341 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2511005751 |
|
|
Feb 09 03:44:35 AM UTC 25 |
Feb 09 03:44:54 AM UTC 25 |
55795400 ps |
| T1159 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.808038668 |
|
|
Feb 09 03:44:35 AM UTC 25 |
Feb 09 03:44:58 AM UTC 25 |
84487200 ps |
| T234 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2289496508 |
|
|
Feb 09 03:44:32 AM UTC 25 |
Feb 09 03:44:59 AM UTC 25 |
23525000 ps |
| T1160 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2545648531 |
|
|
Feb 09 03:44:37 AM UTC 25 |
Feb 09 03:45:01 AM UTC 25 |
28358800 ps |
| T1161 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2095843597 |
|
|
Feb 09 03:44:33 AM UTC 25 |
Feb 09 03:45:02 AM UTC 25 |
55271400 ps |
| T293 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2348121275 |
|
|
Feb 09 03:44:16 AM UTC 25 |
Feb 09 03:45:03 AM UTC 25 |
105426000 ps |
| T240 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1211645073 |
|
|
Feb 09 03:44:41 AM UTC 25 |
Feb 09 03:45:08 AM UTC 25 |
16208200 ps |
| T226 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.976402337 |
|
|
Feb 09 03:44:33 AM UTC 25 |
Feb 09 03:45:10 AM UTC 25 |
62599600 ps |
| T383 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.741892208 |
|
|
Feb 09 03:44:43 AM UTC 25 |
Feb 09 03:45:13 AM UTC 25 |
26854400 ps |
| T1162 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.427007304 |
|
|
Feb 09 03:45:01 AM UTC 25 |
Feb 09 03:45:28 AM UTC 25 |
35667600 ps |
| T235 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.310897054 |
|
|
Feb 09 03:44:59 AM UTC 25 |
Feb 09 03:45:31 AM UTC 25 |
158485300 ps |
| T1163 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2852990906 |
|
|
Feb 09 03:45:02 AM UTC 25 |
Feb 09 03:45:31 AM UTC 25 |
12418700 ps |
| T342 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2855482651 |
|
|
Feb 09 03:45:04 AM UTC 25 |
Feb 09 03:45:33 AM UTC 25 |
58820600 ps |
| T1164 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3689978728 |
|
|
Feb 09 03:45:09 AM UTC 25 |
Feb 09 03:45:36 AM UTC 25 |
130923100 ps |
| T258 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2879607710 |
|
|
Feb 09 03:45:01 AM UTC 25 |
Feb 09 03:45:38 AM UTC 25 |
57086500 ps |
| T1165 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2740975650 |
|
|
Feb 09 03:44:32 AM UTC 25 |
Feb 09 03:45:38 AM UTC 25 |
65413700 ps |
| T285 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.320711462 |
|
|
Feb 09 03:44:55 AM UTC 25 |
Feb 09 03:45:41 AM UTC 25 |
901118800 ps |
| T286 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3121107553 |
|
|
Feb 09 03:44:27 AM UTC 25 |
Feb 09 03:45:45 AM UTC 25 |
6450552200 ps |
| T1166 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3625643594 |
|
|
Feb 09 03:45:14 AM UTC 25 |
Feb 09 03:45:45 AM UTC 25 |
160578400 ps |
| T1167 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.857524621 |
|
|
Feb 09 03:44:29 AM UTC 25 |
Feb 09 03:45:46 AM UTC 25 |
448909400 ps |
| T1168 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.67295030 |
|
|
Feb 09 03:45:32 AM UTC 25 |
Feb 09 03:45:55 AM UTC 25 |
46399500 ps |
| T1169 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3498566119 |
|
|
Feb 09 03:44:42 AM UTC 25 |
Feb 09 03:45:57 AM UTC 25 |
45579600 ps |
| T346 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2904060593 |
|
|
Feb 09 03:45:38 AM UTC 25 |
Feb 09 03:46:02 AM UTC 25 |
16358100 ps |
| T295 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3690355978 |
|
|
Feb 09 03:45:39 AM UTC 25 |
Feb 09 03:46:04 AM UTC 25 |
58877700 ps |
| T1170 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1139549533 |
|
|
Feb 09 03:45:34 AM UTC 25 |
Feb 09 03:46:04 AM UTC 25 |
16855400 ps |
| T1171 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3095993923 |
|
|
Feb 09 03:44:50 AM UTC 25 |
Feb 09 03:46:07 AM UTC 25 |
873882700 ps |
| T256 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4094782536 |
|
|
Feb 09 03:45:29 AM UTC 25 |
Feb 09 03:46:07 AM UTC 25 |
58209600 ps |
| T261 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1515641207 |
|
|
Feb 09 03:45:46 AM UTC 25 |
Feb 09 03:46:13 AM UTC 25 |
54839200 ps |
| T287 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2485865055 |
|
|
Feb 09 03:44:47 AM UTC 25 |
Feb 09 03:46:14 AM UTC 25 |
6406427400 ps |
| T1172 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2443331738 |
|
|
Feb 09 03:45:47 AM UTC 25 |
Feb 09 03:46:16 AM UTC 25 |
62766100 ps |
| T1173 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.428165121 |
|
|
Feb 09 03:45:10 AM UTC 25 |
Feb 09 03:46:17 AM UTC 25 |
613061200 ps |
| T1174 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3132625380 |
|
|
Feb 09 03:45:42 AM UTC 25 |
Feb 09 03:46:18 AM UTC 25 |
157699100 ps |
| T343 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2444425682 |
|
|
Feb 09 03:45:58 AM UTC 25 |
Feb 09 03:46:18 AM UTC 25 |
51313800 ps |
| T1175 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.264781558 |
|
|
Feb 09 03:45:56 AM UTC 25 |
Feb 09 03:46:28 AM UTC 25 |
23066800 ps |
| T288 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1662794092 |
|
|
Feb 09 03:46:03 AM UTC 25 |
Feb 09 03:46:33 AM UTC 25 |
128108900 ps |
| T1176 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1933506380 |
|
|
Feb 09 03:45:39 AM UTC 25 |
Feb 09 03:46:35 AM UTC 25 |
202274000 ps |
| T1177 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1512905700 |
|
|
Feb 09 03:46:15 AM UTC 25 |
Feb 09 03:46:36 AM UTC 25 |
16234200 ps |
| T1178 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1393672133 |
|
|
Feb 09 03:46:04 AM UTC 25 |
Feb 09 03:46:38 AM UTC 25 |
333152400 ps |
| T1179 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3424213181 |
|
|
Feb 09 03:46:04 AM UTC 25 |
Feb 09 03:46:41 AM UTC 25 |
101294100 ps |
| T345 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.4088405037 |
|
|
Feb 09 03:46:17 AM UTC 25 |
Feb 09 03:46:42 AM UTC 25 |
18320400 ps |
| T1180 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3161100911 |
|
|
Feb 09 03:46:15 AM UTC 25 |
Feb 09 03:46:43 AM UTC 25 |
170728000 ps |
| T259 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3526338371 |
|
|
Feb 09 03:46:07 AM UTC 25 |
Feb 09 03:46:45 AM UTC 25 |
88342900 ps |
| T294 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1048052102 |
|
|
Feb 09 03:46:19 AM UTC 25 |
Feb 09 03:46:49 AM UTC 25 |
98250000 ps |
| T289 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.665385032 |
|
|
Feb 09 03:46:18 AM UTC 25 |
Feb 09 03:46:51 AM UTC 25 |
77421200 ps |
| T1181 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2847006682 |
|
|
Feb 09 03:46:34 AM UTC 25 |
Feb 09 03:46:56 AM UTC 25 |
20797700 ps |
| T1182 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3444753937 |
|
|
Feb 09 03:46:19 AM UTC 25 |
Feb 09 03:46:58 AM UTC 25 |
228929100 ps |
| T262 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.873630896 |
|
|
Feb 09 03:46:28 AM UTC 25 |
Feb 09 03:47:01 AM UTC 25 |
92239300 ps |
| T347 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1286963961 |
|
|
Feb 09 03:46:36 AM UTC 25 |
Feb 09 03:47:02 AM UTC 25 |
16233000 ps |
| T1183 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3124486073 |
|
|
Feb 09 03:46:36 AM UTC 25 |
Feb 09 03:47:06 AM UTC 25 |
40308800 ps |
| T1184 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.628867382 |
|
|
Feb 09 03:46:46 AM UTC 25 |
Feb 09 03:47:09 AM UTC 25 |
14266400 ps |
| T1185 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4248001956 |
|
|
Feb 09 03:46:37 AM UTC 25 |
Feb 09 03:47:11 AM UTC 25 |
93357200 ps |
| T290 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.911763603 |
|
|
Feb 09 03:46:42 AM UTC 25 |
Feb 09 03:47:12 AM UTC 25 |
190421800 ps |
| T263 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1205586164 |
|
|
Feb 09 03:46:43 AM UTC 25 |
Feb 09 03:47:13 AM UTC 25 |
35720100 ps |
| T1186 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3034271713 |
|
|
Feb 09 03:46:50 AM UTC 25 |
Feb 09 03:47:14 AM UTC 25 |
31514100 ps |
| T1187 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1295851945 |
|
|
Feb 09 03:46:39 AM UTC 25 |
Feb 09 03:47:17 AM UTC 25 |
227908300 ps |
| T361 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.276028422 |
|
|
Feb 09 03:46:52 AM UTC 25 |
Feb 09 03:47:19 AM UTC 25 |
26852100 ps |
| T291 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2046021717 |
|
|
Feb 09 03:46:57 AM UTC 25 |
Feb 09 03:47:30 AM UTC 25 |
138257700 ps |
| T1188 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.242962897 |
|
|
Feb 09 03:47:12 AM UTC 25 |
Feb 09 03:47:31 AM UTC 25 |
17153700 ps |
| T1189 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3473033786 |
|
|
Feb 09 03:47:09 AM UTC 25 |
Feb 09 03:47:36 AM UTC 25 |
25191600 ps |
| T1190 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4157691600 |
|
|
Feb 09 03:47:02 AM UTC 25 |
Feb 09 03:47:37 AM UTC 25 |
82440300 ps |
| T1191 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2561298566 |
|
|
Feb 09 03:47:03 AM UTC 25 |
Feb 09 03:47:37 AM UTC 25 |
45378500 ps |
| T1192 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2633912921 |
|
|
Feb 09 03:47:11 AM UTC 25 |
Feb 09 03:47:40 AM UTC 25 |
52324000 ps |
| T1193 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1516405883 |
|
|
Feb 09 03:47:14 AM UTC 25 |
Feb 09 03:47:45 AM UTC 25 |
27614700 ps |
| T292 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2710043205 |
|
|
Feb 09 03:47:14 AM UTC 25 |
Feb 09 03:47:47 AM UTC 25 |
115971600 ps |
| T296 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.167068217 |
|
|
Feb 09 03:47:17 AM UTC 25 |
Feb 09 03:47:51 AM UTC 25 |
224227300 ps |
| T260 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.958445434 |
|
|
Feb 09 03:47:21 AM UTC 25 |
Feb 09 03:47:56 AM UTC 25 |
97444700 ps |
| T1194 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.949095689 |
|
|
Feb 09 03:47:32 AM UTC 25 |
Feb 09 03:48:03 AM UTC 25 |
20894000 ps |
| T1195 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3300687161 |
|
|
Feb 09 03:46:59 AM UTC 25 |
Feb 09 03:48:03 AM UTC 25 |
227147900 ps |
| T1196 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.406860110 |
|
|
Feb 09 03:47:38 AM UTC 25 |
Feb 09 03:48:03 AM UTC 25 |
18470300 ps |
| T344 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.93160473 |
|
|
Feb 09 03:47:38 AM UTC 25 |
Feb 09 03:48:04 AM UTC 25 |
33628300 ps |
| T1197 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.84878018 |
|
|
Feb 09 03:47:37 AM UTC 25 |
Feb 09 03:48:09 AM UTC 25 |
13075800 ps |
| T362 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1287680740 |
|
|
Feb 09 03:48:01 AM UTC 25 |
Feb 09 03:48:20 AM UTC 25 |
25638600 ps |
| T297 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2867228649 |
|
|
Feb 09 03:47:46 AM UTC 25 |
Feb 09 03:48:21 AM UTC 25 |
61644400 ps |
| T1198 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.122864893 |
|
|
Feb 09 03:47:48 AM UTC 25 |
Feb 09 03:48:22 AM UTC 25 |
87034000 ps |
| T1199 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.693961008 |
|
|
Feb 09 03:48:00 AM UTC 25 |
Feb 09 03:48:26 AM UTC 25 |
12807200 ps |
| T1200 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3292382412 |
|
|
Feb 09 03:47:57 AM UTC 25 |
Feb 09 03:48:29 AM UTC 25 |
12572500 ps |
| T298 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1599897608 |
|
|
Feb 09 03:48:04 AM UTC 25 |
Feb 09 03:48:32 AM UTC 25 |
1111570300 ps |
| T1201 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3593643372 |
|
|
Feb 09 03:47:41 AM UTC 25 |
Feb 09 03:48:34 AM UTC 25 |
118486900 ps |
| T1202 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2147107179 |
|
|
Feb 09 03:48:05 AM UTC 25 |
Feb 09 03:48:37 AM UTC 25 |
843984600 ps |
| T264 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.385753896 |
|
|
Feb 09 03:48:05 AM UTC 25 |
Feb 09 03:48:38 AM UTC 25 |
87392500 ps |
| T1203 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1457250074 |
|
|
Feb 09 03:48:04 AM UTC 25 |
Feb 09 03:48:38 AM UTC 25 |
31991900 ps |
| T1204 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2978700943 |
|
|
Feb 09 03:48:22 AM UTC 25 |
Feb 09 03:48:48 AM UTC 25 |
17797300 ps |
| T1205 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1550291489 |
|
|
Feb 09 03:48:21 AM UTC 25 |
Feb 09 03:48:52 AM UTC 25 |
13338800 ps |
| T1206 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3247556685 |
|
|
Feb 09 03:48:22 AM UTC 25 |
Feb 09 03:48:54 AM UTC 25 |
33745400 ps |
| T1207 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3092750309 |
|
|
Feb 09 03:48:27 AM UTC 25 |
Feb 09 03:48:56 AM UTC 25 |
123188500 ps |
| T1208 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2907285585 |
|
|
Feb 09 03:48:33 AM UTC 25 |
Feb 09 03:49:06 AM UTC 25 |
39855900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3168984836 |
|
|
Feb 09 03:48:38 AM UTC 25 |
Feb 09 03:49:07 AM UTC 25 |
12639100 ps |
| T1210 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3643246008 |
|
|
Feb 09 03:48:34 AM UTC 25 |
Feb 09 03:49:08 AM UTC 25 |
143988600 ps |
| T1211 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3911197517 |
|
|
Feb 09 03:48:38 AM UTC 25 |
Feb 09 03:49:08 AM UTC 25 |
34194600 ps |
| T1212 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.906238080 |
|
|
Feb 09 03:48:49 AM UTC 25 |
Feb 09 03:49:15 AM UTC 25 |
48720600 ps |
| T1213 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3339948720 |
|
|
Feb 09 03:48:53 AM UTC 25 |
Feb 09 03:49:20 AM UTC 25 |
34558700 ps |
| T1214 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1488522733 |
|
|
Feb 09 03:49:07 AM UTC 25 |
Feb 09 03:49:28 AM UTC 25 |
39715400 ps |
| T299 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1931760819 |
|
|
Feb 09 03:48:56 AM UTC 25 |
Feb 09 03:49:32 AM UTC 25 |
126418900 ps |
| T1215 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.546364491 |
|
|
Feb 09 03:48:57 AM UTC 25 |
Feb 09 03:49:33 AM UTC 25 |
390941800 ps |
| T1216 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3004150338 |
|
|
Feb 09 03:49:09 AM UTC 25 |
Feb 09 03:49:37 AM UTC 25 |
45962400 ps |
| T1217 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1165265706 |
|
|
Feb 09 03:48:30 AM UTC 25 |
Feb 09 03:49:40 AM UTC 25 |
389649400 ps |
| T1218 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.4231038753 |
|
|
Feb 09 03:49:16 AM UTC 25 |
Feb 09 03:49:40 AM UTC 25 |
29021000 ps |
| T1219 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1651803209 |
|
|
Feb 09 03:49:09 AM UTC 25 |
Feb 09 03:49:41 AM UTC 25 |
41510000 ps |
| T1220 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1516293605 |
|
|
Feb 09 03:49:21 AM UTC 25 |
Feb 09 03:49:54 AM UTC 25 |
71994100 ps |
| T1221 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4024819397 |
|
|
Feb 09 03:49:32 AM UTC 25 |
Feb 09 03:50:03 AM UTC 25 |
241711800 ps |
| T1222 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3521211935 |
|
|
Feb 09 03:49:34 AM UTC 25 |
Feb 09 03:50:08 AM UTC 25 |
74933900 ps |
| T1223 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1438664424 |
|
|
Feb 09 03:49:41 AM UTC 25 |
Feb 09 03:50:08 AM UTC 25 |
41113000 ps |
| T1224 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2894579979 |
|
|
Feb 09 03:49:41 AM UTC 25 |
Feb 09 03:50:09 AM UTC 25 |
12585700 ps |
| T1225 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2414607508 |
|
|
Feb 09 03:49:42 AM UTC 25 |
Feb 09 03:50:11 AM UTC 25 |
25474700 ps |
| T1226 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3187690736 |
|
|
Feb 09 03:49:55 AM UTC 25 |
Feb 09 03:50:30 AM UTC 25 |
27167100 ps |
| T1227 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1636032999 |
|
|
Feb 09 03:50:05 AM UTC 25 |
Feb 09 03:50:37 AM UTC 25 |
392324200 ps |
| T1228 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2917730749 |
|
|
Feb 09 03:49:29 AM UTC 25 |
Feb 09 03:50:39 AM UTC 25 |
844807900 ps |
| T1229 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.658234105 |
|
|
Feb 09 03:50:12 AM UTC 25 |
Feb 09 03:50:39 AM UTC 25 |
13507700 ps |
| T1230 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3025279260 |
|
|
Feb 09 03:50:09 AM UTC 25 |
Feb 09 03:50:41 AM UTC 25 |
102348200 ps |
| T1231 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3095449501 |
|
|
Feb 09 03:50:09 AM UTC 25 |
Feb 09 03:50:42 AM UTC 25 |
45852800 ps |
| T1232 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3184110125 |
|
|
Feb 09 03:50:34 AM UTC 25 |
Feb 09 03:51:02 AM UTC 25 |
15258800 ps |
| T1233 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4050051777 |
|
|
Feb 09 03:50:30 AM UTC 25 |
Feb 09 03:51:03 AM UTC 25 |
87046200 ps |
| T1234 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.120588215 |
|
|
Feb 09 03:50:40 AM UTC 25 |
Feb 09 03:51:04 AM UTC 25 |
163495000 ps |
| T1235 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1399900735 |
|
|
Feb 09 03:50:38 AM UTC 25 |
Feb 09 03:51:12 AM UTC 25 |
35009800 ps |
| T1236 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.690822367 |
|
|
Feb 09 03:50:42 AM UTC 25 |
Feb 09 03:51:12 AM UTC 25 |
930420600 ps |
| T1237 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1325372497 |
|
|
Feb 09 03:50:41 AM UTC 25 |
Feb 09 03:51:12 AM UTC 25 |
49019800 ps |
| T1238 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.252895949 |
|
|
Feb 09 03:51:03 AM UTC 25 |
Feb 09 03:51:23 AM UTC 25 |
24885600 ps |
| T1239 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.801518781 |
|
|
Feb 09 03:51:04 AM UTC 25 |
Feb 09 03:51:27 AM UTC 25 |
14510900 ps |
| T1240 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.1123389174 |
|
|
Feb 09 03:51:05 AM UTC 25 |
Feb 09 03:51:29 AM UTC 25 |
17521000 ps |
| T1241 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.783233826 |
|
|
Feb 09 03:51:10 AM UTC 25 |
Feb 09 03:51:31 AM UTC 25 |
113701700 ps |
| T1242 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.2577849374 |
|
|
Feb 09 03:51:13 AM UTC 25 |
Feb 09 03:51:39 AM UTC 25 |
15309300 ps |
| T1243 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.253844367 |
|
|
Feb 09 03:51:16 AM UTC 25 |
Feb 09 03:51:40 AM UTC 25 |
52639800 ps |
| T247 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3325037192 |
|
|
Feb 09 03:42:30 AM UTC 25 |
Feb 09 03:51:47 AM UTC 25 |
248504100 ps |
| T1244 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1235812973 |
|
|
Feb 09 03:51:13 AM UTC 25 |
Feb 09 03:51:49 AM UTC 25 |
66770500 ps |
| T1245 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2537807360 |
|
|
Feb 09 03:51:28 AM UTC 25 |
Feb 09 03:51:49 AM UTC 25 |
40596400 ps |
| T1246 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.815277440 |
|
|
Feb 09 03:51:24 AM UTC 25 |
Feb 09 03:51:50 AM UTC 25 |
188825500 ps |
| T1247 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3341098313 |
|
|
Feb 09 03:51:30 AM UTC 25 |
Feb 09 03:51:55 AM UTC 25 |
27347700 ps |
| T1248 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.713769462 |
|
|
Feb 09 03:51:32 AM UTC 25 |
Feb 09 03:51:57 AM UTC 25 |
39806000 ps |
| T1249 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2912975438 |
|
|
Feb 09 03:51:40 AM UTC 25 |
Feb 09 03:52:00 AM UTC 25 |
27456500 ps |
| T1250 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3501483485 |
|
|
Feb 09 03:51:41 AM UTC 25 |
Feb 09 03:52:05 AM UTC 25 |
19792900 ps |
| T1251 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.820982797 |
|
|
Feb 09 03:51:13 AM UTC 25 |
Feb 09 03:52:08 AM UTC 25 |
198705700 ps |
| T1252 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.986083515 |
|
|
Feb 09 03:51:50 AM UTC 25 |
Feb 09 03:52:11 AM UTC 25 |
18139500 ps |
| T1253 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.3262808952 |
|
|
Feb 09 03:51:50 AM UTC 25 |
Feb 09 03:52:12 AM UTC 25 |
19236200 ps |
| T1254 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.2065879019 |
|
|
Feb 09 03:51:48 AM UTC 25 |
Feb 09 03:52:13 AM UTC 25 |
30520400 ps |
| T1255 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1583739924 |
|
|
Feb 09 03:51:50 AM UTC 25 |
Feb 09 03:52:16 AM UTC 25 |
15300200 ps |
| T1256 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2089871324 |
|
|
Feb 09 03:51:48 AM UTC 25 |
Feb 09 03:52:18 AM UTC 25 |
14934500 ps |
| T1257 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2671831539 |
|
|
Feb 09 03:51:56 AM UTC 25 |
Feb 09 03:52:19 AM UTC 25 |
47610300 ps |
| T1258 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1513843811 |
|
|
Feb 09 03:51:57 AM UTC 25 |
Feb 09 03:52:20 AM UTC 25 |
65955100 ps |
| T1259 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.1751563650 |
|
|
Feb 09 03:52:02 AM UTC 25 |
Feb 09 03:52:24 AM UTC 25 |
36338200 ps |
| T1260 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.3632874433 |
|
|
Feb 09 03:52:07 AM UTC 25 |
Feb 09 03:52:29 AM UTC 25 |
17580800 ps |
| T1261 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2844290030 |
|
|
Feb 09 03:52:09 AM UTC 25 |
Feb 09 03:52:30 AM UTC 25 |
14655600 ps |
| T1262 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1573075004 |
|
|
Feb 09 03:52:13 AM UTC 25 |
Feb 09 03:52:34 AM UTC 25 |
14808700 ps |
| T1263 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.3751301665 |
|
|
Feb 09 03:52:07 AM UTC 25 |
Feb 09 03:52:35 AM UTC 25 |
30572200 ps |
| T1264 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.758179273 |
|
|
Feb 09 03:52:17 AM UTC 25 |
Feb 09 03:52:38 AM UTC 25 |
15396300 ps |
| T1265 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.353861533 |
|
|
Feb 09 03:52:11 AM UTC 25 |
Feb 09 03:52:39 AM UTC 25 |
14677300 ps |
| T1266 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2258762873 |
|
|
Feb 09 03:52:13 AM UTC 25 |
Feb 09 03:52:39 AM UTC 25 |
14696300 ps |
| T1267 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2111954324 |
|
|
Feb 09 03:52:18 AM UTC 25 |
Feb 09 03:52:44 AM UTC 25 |
28588900 ps |
| T1268 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.156034059 |
|
|
Feb 09 03:52:20 AM UTC 25 |
Feb 09 03:52:48 AM UTC 25 |
29185500 ps |
| T1269 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.819442650 |
|
|
Feb 09 03:52:31 AM UTC 25 |
Feb 09 03:52:48 AM UTC 25 |
53854500 ps |