| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.2680994377 |
|
|
Sep 11 06:43:48 PM UTC 24 |
Sep 11 06:46:09 PM UTC 24 |
18601900 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.3522378049 |
|
|
Sep 11 06:43:06 PM UTC 24 |
Sep 11 06:46:12 PM UTC 24 |
84551300 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.4179193177 |
|
|
Sep 11 06:41:18 PM UTC 24 |
Sep 11 06:46:12 PM UTC 24 |
23500903100 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.3581210311 |
|
|
Sep 11 06:45:47 PM UTC 24 |
Sep 11 06:46:13 PM UTC 24 |
48551500 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2938890695 |
|
|
Sep 11 06:45:50 PM UTC 24 |
Sep 11 06:46:14 PM UTC 24 |
212312300 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2559305784 |
|
|
Sep 11 06:41:40 PM UTC 24 |
Sep 11 06:46:25 PM UTC 24 |
11554868600 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2870457236 |
|
|
Sep 11 06:43:56 PM UTC 24 |
Sep 11 06:46:33 PM UTC 24 |
172199200 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.612721063 |
|
|
Sep 11 06:43:32 PM UTC 24 |
Sep 11 06:46:45 PM UTC 24 |
159266900 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.553621229 |
|
|
Sep 11 06:44:32 PM UTC 24 |
Sep 11 06:46:52 PM UTC 24 |
148701600 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.4288913982 |
|
|
Sep 11 06:40:33 PM UTC 24 |
Sep 11 06:46:57 PM UTC 24 |
8884482100 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4088477339 |
|
|
Sep 11 06:44:30 PM UTC 24 |
Sep 11 06:46:58 PM UTC 24 |
39092800 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.2846050085 |
|
|
Sep 11 06:43:48 PM UTC 24 |
Sep 11 06:47:00 PM UTC 24 |
2939601200 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.570751653 |
|
|
Sep 11 06:44:16 PM UTC 24 |
Sep 11 06:47:01 PM UTC 24 |
168384800 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1201477856 |
|
|
Sep 11 06:43:26 PM UTC 24 |
Sep 11 06:47:08 PM UTC 24 |
32165300 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.2066910203 |
|
|
Sep 11 06:43:49 PM UTC 24 |
Sep 11 06:47:13 PM UTC 24 |
481908300 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3124588011 |
|
|
Sep 11 06:44:18 PM UTC 24 |
Sep 11 06:47:15 PM UTC 24 |
40073100 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.468607174 |
|
|
Sep 11 05:55:56 PM UTC 24 |
Sep 11 06:47:15 PM UTC 24 |
4007204000 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.688319305 |
|
|
Sep 11 06:44:26 PM UTC 24 |
Sep 11 06:47:19 PM UTC 24 |
70687100 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1620509611 |
|
|
Sep 11 06:44:23 PM UTC 24 |
Sep 11 06:47:23 PM UTC 24 |
42919000 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2466425374 |
|
|
Sep 11 06:44:41 PM UTC 24 |
Sep 11 06:47:24 PM UTC 24 |
460768400 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.200904815 |
|
|
Sep 11 06:44:13 PM UTC 24 |
Sep 11 06:47:34 PM UTC 24 |
129786700 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.4073573212 |
|
|
Sep 11 06:26:30 PM UTC 24 |
Sep 11 06:47:38 PM UTC 24 |
1101511900 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3974059955 |
|
|
Sep 11 06:44:48 PM UTC 24 |
Sep 11 06:47:38 PM UTC 24 |
89257200 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2097893759 |
|
|
Sep 11 06:43:55 PM UTC 24 |
Sep 11 06:47:40 PM UTC 24 |
55031900 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.3499418331 |
|
|
Sep 11 06:44:55 PM UTC 24 |
Sep 11 06:47:41 PM UTC 24 |
49692100 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.822212195 |
|
|
Sep 11 06:44:58 PM UTC 24 |
Sep 11 06:47:43 PM UTC 24 |
112957500 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.2360135406 |
|
|
Sep 11 06:44:36 PM UTC 24 |
Sep 11 06:47:45 PM UTC 24 |
146725200 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1690612853 |
|
|
Sep 11 06:44:52 PM UTC 24 |
Sep 11 06:47:45 PM UTC 24 |
127502600 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1664670338 |
|
|
Sep 11 06:44:49 PM UTC 24 |
Sep 11 06:47:52 PM UTC 24 |
36637100 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.3679188306 |
|
|
Sep 11 06:45:09 PM UTC 24 |
Sep 11 06:47:57 PM UTC 24 |
37370600 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.328987457 |
|
|
Sep 11 06:45:04 PM UTC 24 |
Sep 11 06:47:58 PM UTC 24 |
500218700 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1192903067 |
|
|
Sep 11 06:45:41 PM UTC 24 |
Sep 11 06:48:00 PM UTC 24 |
139466400 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.229316896 |
|
|
Sep 11 06:45:43 PM UTC 24 |
Sep 11 06:48:02 PM UTC 24 |
141822200 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.2633516768 |
|
|
Sep 11 06:45:15 PM UTC 24 |
Sep 11 06:48:06 PM UTC 24 |
76344600 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.1580871921 |
|
|
Sep 11 06:45:45 PM UTC 24 |
Sep 11 06:48:12 PM UTC 24 |
41330500 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.4177754962 |
|
|
Sep 11 06:45:18 PM UTC 24 |
Sep 11 06:48:14 PM UTC 24 |
146419100 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.2076796228 |
|
|
Sep 11 06:45:02 PM UTC 24 |
Sep 11 06:48:18 PM UTC 24 |
41298900 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.928238936 |
|
|
Sep 11 06:45:10 PM UTC 24 |
Sep 11 06:48:19 PM UTC 24 |
151101700 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1653683682 |
|
|
Sep 11 06:45:20 PM UTC 24 |
Sep 11 06:48:19 PM UTC 24 |
142805300 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.2797050803 |
|
|
Sep 11 06:45:31 PM UTC 24 |
Sep 11 06:48:21 PM UTC 24 |
86653800 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1934106549 |
|
|
Sep 11 06:45:25 PM UTC 24 |
Sep 11 06:48:22 PM UTC 24 |
72374900 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.3947998814 |
|
|
Sep 11 06:45:36 PM UTC 24 |
Sep 11 06:48:25 PM UTC 24 |
39957100 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.2366671725 |
|
|
Sep 11 06:45:27 PM UTC 24 |
Sep 11 06:48:25 PM UTC 24 |
152638000 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.813217609 |
|
|
Sep 11 06:45:34 PM UTC 24 |
Sep 11 06:48:30 PM UTC 24 |
528483400 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.213099306 |
|
|
Sep 11 06:45:49 PM UTC 24 |
Sep 11 06:48:32 PM UTC 24 |
132917700 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.253512870 |
|
|
Sep 11 06:00:22 PM UTC 24 |
Sep 11 06:52:38 PM UTC 24 |
3225982700 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2477414150 |
|
|
Sep 11 06:04:29 PM UTC 24 |
Sep 11 06:52:47 PM UTC 24 |
3561834800 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1486790826 |
|
|
Sep 11 06:07:43 PM UTC 24 |
Sep 11 06:56:34 PM UTC 24 |
3178975600 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.787232701 |
|
|
Sep 11 05:28:11 PM UTC 24 |
Sep 11 07:19:24 PM UTC 24 |
5417154500 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.1785727316 |
|
|
Sep 11 05:33:10 PM UTC 24 |
Sep 11 07:28:18 PM UTC 24 |
3872857800 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.2294912979 |
|
|
Sep 11 05:39:14 PM UTC 24 |
Sep 11 07:33:01 PM UTC 24 |
2123187100 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1493186576 |
|
|
Sep 11 05:45:05 PM UTC 24 |
Sep 11 07:36:45 PM UTC 24 |
5060060700 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3931388317 |
|
|
Sep 11 05:50:07 PM UTC 24 |
Sep 11 07:42:01 PM UTC 24 |
13866552300 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3257825747 |
|
|
Sep 11 05:22:08 PM UTC 24 |
Sep 11 05:22:28 PM UTC 24 |
28129700 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2397655848 |
|
|
Sep 11 05:22:07 PM UTC 24 |
Sep 11 05:22:29 PM UTC 24 |
18107900 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3239944515 |
|
|
Sep 11 05:22:08 PM UTC 24 |
Sep 11 05:22:30 PM UTC 24 |
18123100 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1678096243 |
|
|
Sep 11 05:22:06 PM UTC 24 |
Sep 11 05:22:35 PM UTC 24 |
18531800 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2659870018 |
|
|
Sep 11 05:22:12 PM UTC 24 |
Sep 11 05:22:36 PM UTC 24 |
133456000 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3174877999 |
|
|
Sep 11 05:22:06 PM UTC 24 |
Sep 11 05:22:37 PM UTC 24 |
102899300 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.155635615 |
|
|
Sep 11 05:22:10 PM UTC 24 |
Sep 11 05:22:41 PM UTC 24 |
52207100 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3720162385 |
|
|
Sep 11 05:22:14 PM UTC 24 |
Sep 11 05:22:43 PM UTC 24 |
876743700 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3846011783 |
|
|
Sep 11 05:22:16 PM UTC 24 |
Sep 11 05:22:45 PM UTC 24 |
245100400 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2265936597 |
|
|
Sep 11 05:22:23 PM UTC 24 |
Sep 11 05:22:46 PM UTC 24 |
37563400 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1742829627 |
|
|
Sep 11 05:22:21 PM UTC 24 |
Sep 11 05:22:47 PM UTC 24 |
20303400 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1645458714 |
|
|
Sep 11 05:22:16 PM UTC 24 |
Sep 11 05:22:47 PM UTC 24 |
54028100 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1817529763 |
|
|
Sep 11 05:22:19 PM UTC 24 |
Sep 11 05:22:50 PM UTC 24 |
58956000 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2708120836 |
|
|
Sep 11 05:22:20 PM UTC 24 |
Sep 11 05:22:50 PM UTC 24 |
49578700 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3402610566 |
|
|
Sep 11 05:22:18 PM UTC 24 |
Sep 11 05:22:51 PM UTC 24 |
54074300 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.131734315 |
|
|
Sep 11 05:22:31 PM UTC 24 |
Sep 11 05:22:55 PM UTC 24 |
83663200 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2980091491 |
|
|
Sep 11 05:22:39 PM UTC 24 |
Sep 11 05:22:58 PM UTC 24 |
16019200 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1546697489 |
|
|
Sep 11 05:22:27 PM UTC 24 |
Sep 11 05:22:59 PM UTC 24 |
42719500 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1864213060 |
|
|
Sep 11 05:22:34 PM UTC 24 |
Sep 11 05:23:02 PM UTC 24 |
189063000 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2636284102 |
|
|
Sep 11 05:22:36 PM UTC 24 |
Sep 11 05:23:03 PM UTC 24 |
122973100 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3604215830 |
|
|
Sep 11 05:22:13 PM UTC 24 |
Sep 11 05:23:05 PM UTC 24 |
5831989000 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3563030629 |
|
|
Sep 11 05:22:11 PM UTC 24 |
Sep 11 05:23:08 PM UTC 24 |
113557300 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.880967603 |
|
|
Sep 11 05:22:45 PM UTC 24 |
Sep 11 05:23:08 PM UTC 24 |
132425700 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3942114159 |
|
|
Sep 11 05:22:23 PM UTC 24 |
Sep 11 05:23:08 PM UTC 24 |
82052600 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1886450048 |
|
|
Sep 11 05:22:47 PM UTC 24 |
Sep 11 05:23:09 PM UTC 24 |
237896700 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3842254101 |
|
|
Sep 11 05:22:38 PM UTC 24 |
Sep 11 05:23:09 PM UTC 24 |
14113500 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1177759004 |
|
|
Sep 11 05:22:41 PM UTC 24 |
Sep 11 05:23:12 PM UTC 24 |
17650200 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3625130795 |
|
|
Sep 11 05:22:51 PM UTC 24 |
Sep 11 05:23:15 PM UTC 24 |
45584200 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4013639169 |
|
|
Sep 11 05:22:51 PM UTC 24 |
Sep 11 05:23:15 PM UTC 24 |
411705800 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3166178731 |
|
|
Sep 11 05:22:56 PM UTC 24 |
Sep 11 05:23:16 PM UTC 24 |
17059300 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2192181211 |
|
|
Sep 11 05:22:52 PM UTC 24 |
Sep 11 05:23:17 PM UTC 24 |
20151000 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3281877515 |
|
|
Sep 11 05:22:55 PM UTC 24 |
Sep 11 05:23:18 PM UTC 24 |
36159000 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.605357457 |
|
|
Sep 11 05:22:56 PM UTC 24 |
Sep 11 05:23:22 PM UTC 24 |
27163900 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4187242550 |
|
|
Sep 11 05:22:31 PM UTC 24 |
Sep 11 05:23:23 PM UTC 24 |
166165600 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.138070501 |
|
|
Sep 11 05:22:48 PM UTC 24 |
Sep 11 05:23:26 PM UTC 24 |
86630800 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1789649639 |
|
|
Sep 11 05:22:59 PM UTC 24 |
Sep 11 05:23:26 PM UTC 24 |
17571600 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2818271354 |
|
|
Sep 11 05:23:04 PM UTC 24 |
Sep 11 05:23:27 PM UTC 24 |
77676400 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2996509320 |
|
|
Sep 11 05:23:05 PM UTC 24 |
Sep 11 05:23:27 PM UTC 24 |
191018200 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.1739595563 |
|
|
Sep 11 05:23:09 PM UTC 24 |
Sep 11 05:23:28 PM UTC 24 |
16306800 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2576012036 |
|
|
Sep 11 05:23:00 PM UTC 24 |
Sep 11 05:23:29 PM UTC 24 |
213639500 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1729980011 |
|
|
Sep 11 05:23:05 PM UTC 24 |
Sep 11 05:23:30 PM UTC 24 |
29536200 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4022302765 |
|
|
Sep 11 05:22:48 PM UTC 24 |
Sep 11 05:23:32 PM UTC 24 |
336387800 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3346659855 |
|
|
Sep 11 05:23:08 PM UTC 24 |
Sep 11 05:23:33 PM UTC 24 |
22017700 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.359551868 |
|
|
Sep 11 05:22:13 PM UTC 24 |
Sep 11 05:23:34 PM UTC 24 |
1653355300 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2481266783 |
|
|
Sep 11 05:23:09 PM UTC 24 |
Sep 11 05:23:36 PM UTC 24 |
31404500 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4091166183 |
|
|
Sep 11 05:23:09 PM UTC 24 |
Sep 11 05:23:37 PM UTC 24 |
16242700 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2211108182 |
|
|
Sep 11 05:23:16 PM UTC 24 |
Sep 11 05:23:38 PM UTC 24 |
498470200 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3554846508 |
|
|
Sep 11 05:23:09 PM UTC 24 |
Sep 11 05:23:39 PM UTC 24 |
115778200 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.25214347 |
|
|
Sep 11 05:23:19 PM UTC 24 |
Sep 11 05:23:39 PM UTC 24 |
37728100 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.79894059 |
|
|
Sep 11 05:22:47 PM UTC 24 |
Sep 11 05:23:40 PM UTC 24 |
43185000 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.1025321238 |
|
|
Sep 11 05:23:22 PM UTC 24 |
Sep 11 05:23:41 PM UTC 24 |
53039500 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2360460980 |
|
|
Sep 11 05:23:17 PM UTC 24 |
Sep 11 05:23:42 PM UTC 24 |
56637800 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3189421795 |
|
|
Sep 11 05:23:00 PM UTC 24 |
Sep 11 05:23:43 PM UTC 24 |
28861600 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.627285680 |
|
|
Sep 11 05:23:19 PM UTC 24 |
Sep 11 05:23:44 PM UTC 24 |
14558800 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3917358952 |
|
|
Sep 11 05:23:01 PM UTC 24 |
Sep 11 05:23:45 PM UTC 24 |
322754800 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3537188339 |
|
|
Sep 11 05:22:48 PM UTC 24 |
Sep 11 05:23:47 PM UTC 24 |
438776600 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3729033733 |
|
|
Sep 11 05:23:24 PM UTC 24 |
Sep 11 05:23:47 PM UTC 24 |
61749000 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3380465543 |
|
|
Sep 11 05:23:14 PM UTC 24 |
Sep 11 05:23:47 PM UTC 24 |
54621000 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1792007203 |
|
|
Sep 11 05:23:29 PM UTC 24 |
Sep 11 05:23:48 PM UTC 24 |
25854300 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1132481222 |
|
|
Sep 11 05:22:30 PM UTC 24 |
Sep 11 05:23:49 PM UTC 24 |
437842700 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.311086165 |
|
|
Sep 11 05:23:17 PM UTC 24 |
Sep 11 05:23:50 PM UTC 24 |
198737900 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3513724395 |
|
|
Sep 11 05:23:27 PM UTC 24 |
Sep 11 05:23:51 PM UTC 24 |
37185200 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1409981283 |
|
|
Sep 11 05:23:13 PM UTC 24 |
Sep 11 05:23:52 PM UTC 24 |
256578000 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.921529808 |
|
|
Sep 11 05:23:30 PM UTC 24 |
Sep 11 05:23:55 PM UTC 24 |
25298100 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2263661397 |
|
|
Sep 11 05:23:33 PM UTC 24 |
Sep 11 05:23:57 PM UTC 24 |
104446500 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2615572939 |
|
|
Sep 11 05:23:29 PM UTC 24 |
Sep 11 05:23:57 PM UTC 24 |
23809100 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.518722018 |
|
|
Sep 11 05:23:30 PM UTC 24 |
Sep 11 05:23:58 PM UTC 24 |
47646900 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3190819137 |
|
|
Sep 11 05:23:36 PM UTC 24 |
Sep 11 05:23:58 PM UTC 24 |
33950000 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1149010890 |
|
|
Sep 11 05:23:31 PM UTC 24 |
Sep 11 05:23:58 PM UTC 24 |
170235600 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1709264555 |
|
|
Sep 11 05:23:27 PM UTC 24 |
Sep 11 05:23:59 PM UTC 24 |
419840400 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2018400030 |
|
|
Sep 11 05:22:29 PM UTC 24 |
Sep 11 05:23:59 PM UTC 24 |
2178806300 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3794384545 |
|
|
Sep 11 05:23:16 PM UTC 24 |
Sep 11 05:24:00 PM UTC 24 |
338399500 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2243643968 |
|
|
Sep 11 05:23:39 PM UTC 24 |
Sep 11 05:24:00 PM UTC 24 |
59973600 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1102567969 |
|
|
Sep 11 05:23:03 PM UTC 24 |
Sep 11 05:24:01 PM UTC 24 |
4097748000 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1305770134 |
|
|
Sep 11 05:23:37 PM UTC 24 |
Sep 11 05:24:01 PM UTC 24 |
14241300 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.226095847 |
|
|
Sep 11 05:23:34 PM UTC 24 |
Sep 11 05:24:02 PM UTC 24 |
91048400 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3351887624 |
|
|
Sep 11 05:24:48 PM UTC 24 |
Sep 11 05:25:13 PM UTC 24 |
445430400 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3560239413 |
|
|
Sep 11 05:23:39 PM UTC 24 |
Sep 11 05:24:05 PM UTC 24 |
715822700 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1839669429 |
|
|
Sep 11 05:23:28 PM UTC 24 |
Sep 11 05:24:06 PM UTC 24 |
208173200 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.697586918 |
|
|
Sep 11 05:23:41 PM UTC 24 |
Sep 11 05:24:07 PM UTC 24 |
28391600 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1405169095 |
|
|
Sep 11 05:23:39 PM UTC 24 |
Sep 11 05:24:07 PM UTC 24 |
265861500 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1007582362 |
|
|
Sep 11 05:23:44 PM UTC 24 |
Sep 11 05:24:08 PM UTC 24 |
16249300 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4197276641 |
|
|
Sep 11 05:23:42 PM UTC 24 |
Sep 11 05:24:10 PM UTC 24 |
499959200 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3726252210 |
|
|
Sep 11 05:23:47 PM UTC 24 |
Sep 11 05:24:12 PM UTC 24 |
62580900 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.3638823261 |
|
|
Sep 11 05:23:46 PM UTC 24 |
Sep 11 05:24:12 PM UTC 24 |
50889600 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2728693018 |
|
|
Sep 11 05:23:54 PM UTC 24 |
Sep 11 05:24:12 PM UTC 24 |
72939300 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1689487473 |
|
|
Sep 11 05:23:16 PM UTC 24 |
Sep 11 05:24:15 PM UTC 24 |
853343300 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2790570756 |
|
|
Sep 11 05:23:48 PM UTC 24 |
Sep 11 05:24:15 PM UTC 24 |
55691500 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1807130721 |
|
|
Sep 11 05:23:45 PM UTC 24 |
Sep 11 05:24:16 PM UTC 24 |
41092500 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1024325868 |
|
|
Sep 11 05:23:51 PM UTC 24 |
Sep 11 05:24:17 PM UTC 24 |
24824800 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2290837949 |
|
|
Sep 11 05:23:52 PM UTC 24 |
Sep 11 05:24:17 PM UTC 24 |
33451500 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3681748230 |
|
|
Sep 11 05:23:57 PM UTC 24 |
Sep 11 05:24:17 PM UTC 24 |
20407200 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1815917915 |
|
|
Sep 11 05:23:47 PM UTC 24 |
Sep 11 05:24:18 PM UTC 24 |
527831300 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2051441960 |
|
|
Sep 11 05:23:58 PM UTC 24 |
Sep 11 05:24:22 PM UTC 24 |
37388000 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4093709088 |
|
|
Sep 11 05:23:58 PM UTC 24 |
Sep 11 05:24:23 PM UTC 24 |
98587500 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.971844087 |
|
|
Sep 11 05:23:59 PM UTC 24 |
Sep 11 05:24:23 PM UTC 24 |
38863800 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.995783268 |
|
|
Sep 11 05:24:00 PM UTC 24 |
Sep 11 05:24:23 PM UTC 24 |
20440900 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1754019202 |
|
|
Sep 11 05:23:49 PM UTC 24 |
Sep 11 05:24:24 PM UTC 24 |
232334400 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.145895856 |
|
|
Sep 11 05:24:07 PM UTC 24 |
Sep 11 05:24:25 PM UTC 24 |
31371300 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.875214294 |
|
|
Sep 11 05:23:59 PM UTC 24 |
Sep 11 05:24:25 PM UTC 24 |
55635100 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3356944727 |
|
|
Sep 11 05:24:02 PM UTC 24 |
Sep 11 05:24:26 PM UTC 24 |
202770800 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1141540097 |
|
|
Sep 11 05:24:01 PM UTC 24 |
Sep 11 05:24:26 PM UTC 24 |
33796900 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1168204656 |
|
|
Sep 11 05:24:05 PM UTC 24 |
Sep 11 05:24:26 PM UTC 24 |
32580900 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.954024430 |
|
|
Sep 11 05:24:07 PM UTC 24 |
Sep 11 05:24:28 PM UTC 24 |
57944100 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.1833140543 |
|
|
Sep 11 05:24:00 PM UTC 24 |
Sep 11 05:24:29 PM UTC 24 |
16959200 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1472677518 |
|
|
Sep 11 05:24:03 PM UTC 24 |
Sep 11 05:24:30 PM UTC 24 |
215490100 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3230532453 |
|
|
Sep 11 05:24:08 PM UTC 24 |
Sep 11 05:24:31 PM UTC 24 |
43366700 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3179893995 |
|
|
Sep 11 05:24:09 PM UTC 24 |
Sep 11 05:24:32 PM UTC 24 |
103484400 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2107672803 |
|
|
Sep 11 05:24:13 PM UTC 24 |
Sep 11 05:24:35 PM UTC 24 |
44907300 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1784597517 |
|
|
Sep 11 05:24:08 PM UTC 24 |
Sep 11 05:24:35 PM UTC 24 |
38451200 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1281518969 |
|
|
Sep 11 05:24:11 PM UTC 24 |
Sep 11 05:24:35 PM UTC 24 |
322653600 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3499976285 |
|
|
Sep 11 05:24:01 PM UTC 24 |
Sep 11 05:24:35 PM UTC 24 |
272480200 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3401562711 |
|
|
Sep 11 05:24:16 PM UTC 24 |
Sep 11 05:24:39 PM UTC 24 |
25095700 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3296184980 |
|
|
Sep 11 05:24:13 PM UTC 24 |
Sep 11 05:24:39 PM UTC 24 |
36451700 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3238720280 |
|
|
Sep 11 05:24:16 PM UTC 24 |
Sep 11 05:24:39 PM UTC 24 |
22152900 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4000490308 |
|
|
Sep 11 05:24:19 PM UTC 24 |
Sep 11 05:24:42 PM UTC 24 |
235710300 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1377063005 |
|
|
Sep 11 05:24:16 PM UTC 24 |
Sep 11 05:24:42 PM UTC 24 |
294840100 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.294257179 |
|
|
Sep 11 05:24:23 PM UTC 24 |
Sep 11 05:24:45 PM UTC 24 |
23932100 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1902102760 |
|
|
Sep 11 05:24:25 PM UTC 24 |
Sep 11 05:24:46 PM UTC 24 |
45927500 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.2449652203 |
|
|
Sep 11 05:24:24 PM UTC 24 |
Sep 11 05:24:47 PM UTC 24 |
17985900 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2934373140 |
|
|
Sep 11 05:24:19 PM UTC 24 |
Sep 11 05:24:47 PM UTC 24 |
404030400 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1225777149 |
|
|
Sep 11 05:24:29 PM UTC 24 |
Sep 11 05:24:48 PM UTC 24 |
94876800 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1488453804 |
|
|
Sep 11 05:24:19 PM UTC 24 |
Sep 11 05:24:49 PM UTC 24 |
33796000 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3771092734 |
|
|
Sep 11 05:24:27 PM UTC 24 |
Sep 11 05:24:49 PM UTC 24 |
41806400 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3424623364 |
|
|
Sep 11 05:24:27 PM UTC 24 |
Sep 11 05:24:50 PM UTC 24 |
14585200 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.706042849 |
|
|
Sep 11 05:24:31 PM UTC 24 |
Sep 11 05:24:50 PM UTC 24 |
67791800 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3477326528 |
|
|
Sep 11 05:24:26 PM UTC 24 |
Sep 11 05:24:50 PM UTC 24 |
129142000 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2981893210 |
|
|
Sep 11 05:24:30 PM UTC 24 |
Sep 11 05:24:53 PM UTC 24 |
43992200 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1746836898 |
|
|
Sep 11 05:24:24 PM UTC 24 |
Sep 11 05:24:53 PM UTC 24 |
145799500 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.136154082 |
|
|
Sep 11 05:24:27 PM UTC 24 |
Sep 11 05:24:54 PM UTC 24 |
11835200 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2823321551 |
|
|
Sep 11 05:24:29 PM UTC 24 |
Sep 11 05:24:56 PM UTC 24 |
63003900 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3138546820 |
|
|
Sep 11 05:24:33 PM UTC 24 |
Sep 11 05:24:58 PM UTC 24 |
23660400 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3675840448 |
|
|
Sep 11 05:24:35 PM UTC 24 |
Sep 11 05:24:58 PM UTC 24 |
104083200 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1308411478 |
|
|
Sep 11 05:24:30 PM UTC 24 |
Sep 11 05:24:59 PM UTC 24 |
212558100 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.4011607130 |
|
|
Sep 11 05:24:43 PM UTC 24 |
Sep 11 05:25:02 PM UTC 24 |
24145500 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4080564071 |
|
|
Sep 11 05:24:36 PM UTC 24 |
Sep 11 05:25:02 PM UTC 24 |
715076600 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1775744438 |
|
|
Sep 11 05:24:32 PM UTC 24 |
Sep 11 05:25:02 PM UTC 24 |
78316000 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2270598756 |
|
|
Sep 11 05:24:36 PM UTC 24 |
Sep 11 05:25:03 PM UTC 24 |
33367800 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2975908575 |
|
|
Sep 11 05:24:41 PM UTC 24 |
Sep 11 05:25:03 PM UTC 24 |
11787600 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1560645914 |
|
|
Sep 11 05:24:40 PM UTC 24 |
Sep 11 05:25:04 PM UTC 24 |
11729900 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3124178968 |
|
|
Sep 11 05:24:36 PM UTC 24 |
Sep 11 05:25:05 PM UTC 24 |
35380800 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.674599267 |
|
|
Sep 11 05:24:50 PM UTC 24 |
Sep 11 05:25:08 PM UTC 24 |
14400100 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2388500636 |
|
|
Sep 11 05:24:24 PM UTC 24 |
Sep 11 05:25:09 PM UTC 24 |
347644900 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2533011754 |
|
|
Sep 11 05:24:43 PM UTC 24 |
Sep 11 05:25:11 PM UTC 24 |
71103700 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2548152945 |
|
|
Sep 11 05:24:49 PM UTC 24 |
Sep 11 05:25:11 PM UTC 24 |
12585300 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1736660841 |
|
|
Sep 11 05:24:55 PM UTC 24 |
Sep 11 05:25:14 PM UTC 24 |
18831500 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3851534060 |
|
|
Sep 11 05:24:51 PM UTC 24 |
Sep 11 05:25:15 PM UTC 24 |
680075400 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3336218135 |
|
|
Sep 11 05:24:50 PM UTC 24 |
Sep 11 05:25:16 PM UTC 24 |
123689300 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3658029142 |
|
|
Sep 11 05:24:48 PM UTC 24 |
Sep 11 05:25:17 PM UTC 24 |
139878300 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3780550538 |
|
|
Sep 11 05:24:59 PM UTC 24 |
Sep 11 05:25:17 PM UTC 24 |
30029600 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2028736042 |
|
|
Sep 11 05:24:50 PM UTC 24 |
Sep 11 05:25:20 PM UTC 24 |
262025300 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3558396899 |
|
|
Sep 11 05:25:02 PM UTC 24 |
Sep 11 05:25:20 PM UTC 24 |
45515100 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1363993553 |
|
|
Sep 11 05:24:57 PM UTC 24 |
Sep 11 05:25:22 PM UTC 24 |
36678400 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2390732290 |
|
|
Sep 11 05:25:00 PM UTC 24 |
Sep 11 05:25:23 PM UTC 24 |
4133458700 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3328914165 |
|
|
Sep 11 05:24:59 PM UTC 24 |
Sep 11 05:25:24 PM UTC 24 |
43502100 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2559891186 |
|
|
Sep 11 05:24:50 PM UTC 24 |
Sep 11 05:25:26 PM UTC 24 |
186972500 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2462178138 |
|
|
Sep 11 05:24:53 PM UTC 24 |
Sep 11 05:25:26 PM UTC 24 |
240274800 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2009736235 |
|
|
Sep 11 05:25:03 PM UTC 24 |
Sep 11 05:25:26 PM UTC 24 |
11791200 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.1429078680 |
|
|
Sep 11 05:25:04 PM UTC 24 |
Sep 11 05:25:29 PM UTC 24 |
24678700 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4260206060 |
|
|
Sep 11 05:25:04 PM UTC 24 |
Sep 11 05:25:29 PM UTC 24 |
189265600 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1513572636 |
|
|
Sep 11 05:25:03 PM UTC 24 |
Sep 11 05:25:30 PM UTC 24 |
56246000 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.2628813323 |
|
|
Sep 11 05:25:10 PM UTC 24 |
Sep 11 05:25:32 PM UTC 24 |
16539800 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.3740668537 |
|
|
Sep 11 05:25:10 PM UTC 24 |
Sep 11 05:25:33 PM UTC 24 |
208358900 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1034702500 |
|
|
Sep 11 05:24:46 PM UTC 24 |
Sep 11 05:25:33 PM UTC 24 |
172026000 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.1348116605 |
|
|
Sep 11 05:25:12 PM UTC 24 |
Sep 11 05:25:33 PM UTC 24 |
56379800 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.891023453 |
|
|
Sep 11 05:25:12 PM UTC 24 |
Sep 11 05:25:35 PM UTC 24 |
18422200 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3482021871 |
|
|
Sep 11 05:25:15 PM UTC 24 |
Sep 11 05:25:35 PM UTC 24 |
46318100 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2807943788 |
|
|
Sep 11 05:25:04 PM UTC 24 |
Sep 11 05:25:36 PM UTC 24 |
3985231900 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2167014834 |
|
|
Sep 11 05:25:18 PM UTC 24 |
Sep 11 05:25:36 PM UTC 24 |
28428700 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1988307117 |
|
|
Sep 11 05:25:06 PM UTC 24 |
Sep 11 05:25:37 PM UTC 24 |
228791600 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3362022969 |
|
|
Sep 11 05:25:14 PM UTC 24 |
Sep 11 05:25:37 PM UTC 24 |
19053000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3269050337 |
|
|
Sep 11 05:25:03 PM UTC 24 |
Sep 11 05:25:38 PM UTC 24 |
14115000 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2327901395 |
|
|
Sep 11 05:25:16 PM UTC 24 |
Sep 11 05:25:38 PM UTC 24 |
106885800 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3859999265 |
|
|
Sep 11 05:25:17 PM UTC 24 |
Sep 11 05:25:40 PM UTC 24 |
17230700 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.882893038 |
|
|
Sep 11 05:25:18 PM UTC 24 |
Sep 11 05:25:42 PM UTC 24 |
51871000 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2993423459 |
|
|
Sep 11 05:25:24 PM UTC 24 |
Sep 11 05:25:42 PM UTC 24 |
16836200 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.3905671758 |
|
|
Sep 11 05:25:22 PM UTC 24 |
Sep 11 05:25:43 PM UTC 24 |
20193700 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.3804820087 |
|
|
Sep 11 05:25:21 PM UTC 24 |
Sep 11 05:25:44 PM UTC 24 |
58304900 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.242415608 |
|
|
Sep 11 05:25:20 PM UTC 24 |
Sep 11 05:25:46 PM UTC 24 |
16373600 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.15474092 |
|
|
Sep 11 05:25:25 PM UTC 24 |
Sep 11 05:25:47 PM UTC 24 |
15058100 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.3075662247 |
|
|
Sep 11 05:25:28 PM UTC 24 |
Sep 11 05:25:47 PM UTC 24 |
14979800 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.1840916099 |
|
|
Sep 11 05:25:29 PM UTC 24 |
Sep 11 05:25:50 PM UTC 24 |
60786400 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2702838252 |
|
|
Sep 11 05:25:33 PM UTC 24 |
Sep 11 05:25:50 PM UTC 24 |
16546200 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.1059227690 |
|
|
Sep 11 05:25:33 PM UTC 24 |
Sep 11 05:25:50 PM UTC 24 |
81461100 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.4249262885 |
|
|
Sep 11 05:25:27 PM UTC 24 |
Sep 11 05:25:50 PM UTC 24 |
24688100 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.2453102224 |
|
|
Sep 11 05:25:27 PM UTC 24 |
Sep 11 05:25:51 PM UTC 24 |
48539600 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3285582630 |
|
|
Sep 11 05:25:33 PM UTC 24 |
Sep 11 05:25:52 PM UTC 24 |
31406400 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3441419007 |
|
|
Sep 11 05:25:31 PM UTC 24 |
Sep 11 05:25:53 PM UTC 24 |
48670800 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.3873331344 |
|
|
Sep 11 05:25:30 PM UTC 24 |
Sep 11 05:25:54 PM UTC 24 |
26822000 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3410165436 |
|
|
Sep 11 05:25:35 PM UTC 24 |
Sep 11 05:25:54 PM UTC 24 |
14427000 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2218047299 |
|
|
Sep 11 05:25:30 PM UTC 24 |
Sep 11 05:25:55 PM UTC 24 |
38836500 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2955195884 |
|
|
Sep 11 05:25:34 PM UTC 24 |
Sep 11 05:25:56 PM UTC 24 |
16811800 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.3498652 |
|
|
Sep 11 05:25:37 PM UTC 24 |
Sep 11 05:25:58 PM UTC 24 |
53075000 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.3619478678 |
|
|
Sep 11 05:25:34 PM UTC 24 |
Sep 11 05:25:59 PM UTC 24 |
14347100 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.1946617300 |
|
|
Sep 11 05:25:37 PM UTC 24 |
Sep 11 05:26:02 PM UTC 24 |
146035200 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1030098605 |
|
|
Sep 11 05:22:06 PM UTC 24 |
Sep 11 05:30:18 PM UTC 24 |
1339927200 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1386571543 |
|
|
Sep 11 05:23:29 PM UTC 24 |
Sep 11 05:31:28 PM UTC 24 |
348922700 ps |