FLASH_CTRL Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.207m	26.358us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	42.760s	25.145us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.408m	118.005us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.685m	2.466ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.725m	1.558ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	34.310s	414.076us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
		flash_ctrl_csr_aliasing	1.725m	1.558ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	24.970s	53.223us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	25.870s	48.339us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	50.720s	22.549us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.141m	53.377us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.999m	340.531ms	3	3	100.00
		flash_ctrl_hw_rma_reset	22.294m	160.177ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.410s	15.696us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	53.053m	269.233ms	4	5	80.00
V2	erase_suspend	flash_ctrl_erase_suspend	15.005m	4.166ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.299m	2.437ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.162h	99.781ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.526m	15.340ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.039m	43.013us	40	40	100.00
		flash_ctrl_rw_evict_all_en	1.037m	31.700us	40	40	100.00
		flash_ctrl_re_evict	1.165m	103.315us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.912m	97.375us	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.912m	97.375us	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	23.055m	167.431ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	49.780s	382.500us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	30.664m	929.680us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	59.242m	23.441ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	25.932m	764.135us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.698m	2.998ms	2	5	40.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	29.750s	23.024us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.386m	7.496ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	46.350s	16.253us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.470s	26.989us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.571m	500.771us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	5.047m	12.683ms	50	50	100.00
		flash_ctrl_otp_reset	4.621m	76.314us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.999m	340.531ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.591m	7.319ms	39	40	97.50
		flash_ctrl_intr_wr	2.132m	13.134ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.068m	171.419ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.604m	423.266ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.937m	3.579ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.381m	671.980us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	44.110s	18.745us	5	5	100.00
		flash_ctrl_ro_derr	3.165m	620.318us	10	10	100.00
		flash_ctrl_rw_derr	4.521m	9.722ms	10	10	100.00
		flash_ctrl_derr_detect	4.511m	1.494ms	5	5	100.00
		flash_ctrl_integrity	11.678m	5.126ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	40.010s	85.249us	5	5	100.00
		flash_ctrl_ro_serr	2.964m	1.260ms	10	10	100.00
		flash_ctrl_rw_serr	4.621m	1.802ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	2.165m	1.603ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.871m	1.605ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.396m	11.048ms	19	20	95.00
		flash_ctrl_write_word_sweep	22.980s	50.093us	1	1	100.00
		flash_ctrl_read_word_sweep	21.870s	24.776us	1	1	100.00
		flash_ctrl_ro	2.496m	753.575us	19	20	95.00
		flash_ctrl_rw	11.318m	18.825ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	1.003m	326.333us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	21.325m	84.817ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.776m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	30.390s	87.394us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	26.920s	46.594us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	37.320s	61.630us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	37.320s	61.630us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.408m	118.005us	5	5	100.00
		flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
		flash_ctrl_csr_aliasing	1.725m	1.558ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	1.084m	258.852us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.408m	118.005us	5	5	100.00
		flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
		flash_ctrl_csr_aliasing	1.725m	1.558ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	1.084m	258.852us	20	20	100.00
V2		TOTAL			1005	1013	99.21
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	30.990s	34.217us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
		flash_ctrl_tl_intg_err	24.213m	665.371us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	24.213m	665.371us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	24.213m	665.371us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	51.940s	86.912us	3	3	100.00
		flash_ctrl_wr_intg	32.800s	77.701us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.207m	26.358us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.621m	76.314us	80	80	100.00
		flash_ctrl_disable	46.350s	16.253us	50	50	100.00
		flash_ctrl_sec_info_access	1.936m	4.123ms	50	50	100.00
		flash_ctrl_connect	32.470s	26.989us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	28.640s	74.760us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	33.100s	58.213us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	31.390s	11.634us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	46.350s	16.253us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	51.940s	86.912us	3	3	100.00
		flash_ctrl_access_after_disable	21.670s	14.558us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	47.010s	65.826us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	46.350s	16.253us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	49.780s	382.500us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.318m	18.825ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.621m	1.802ms	10	10	100.00
		flash_ctrl_rw_derr	4.521m	9.722ms	10	10	100.00
		flash_ctrl_integrity	11.678m	5.126ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.999m	340.531ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	42.310s	876.100us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	29.150s	28.752us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	29.410s	24.132us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.877h	25.039ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.087m	77.568us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1281	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	95.23	93.83	98.31	92.52	97.16	97.27	98.18

Failure Buckets

Job timed out after * minutes has 5 failures:
- Test flash_ctrl_error_prog_type has 3 failures.
  - 0.flash_ctrl_error_prog_type.27623843523943146228572069030018654612169294120274273047490602303825771773786
    Log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.flash_ctrl_error_prog_type.34040114675191340423851034378631067177131471232162504495350557930053538923872
    Log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test flash_ctrl_host_ctrl_arb has 1 failures.
  - 1.flash_ctrl_host_ctrl_arb.3276481663506575291134850325163246104505533116731417212831668827496231610155
    Log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_wo has 1 failures.
  - 1.flash_ctrl_wo.72165509713945154689193028283001255992528854565796591631444659567206677513180
    Log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_ro has 1 failures.
  - 4.flash_ctrl_ro.80263365167651838064003429531611234233203356170216649992033975846205855342124
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 187019.3 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 187019.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw has 1 failures.
  - 4.flash_ctrl_rw.83407472829167884361767154092923288948561895768646219937732343934152282230360
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 441299.5 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 441299.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp aeef440b_6af393f7:ffffffff_6af393f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 36.flash_ctrl_intr_rd.43982898236582015726336013430001158007682084968185165881821676725704272196699
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3853647.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    aeef440b_6af393f7:ffffffff_6af393f7  mismatch!!
  UVM_INFO @ 3853647.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `29d22a60a2`