FLASH_CTRL Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.673m	81.754us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	54.390s	15.733us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.232m	37.675us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.926m	12.148ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.363m	5.042ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	32.850s	75.109us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
		flash_ctrl_csr_aliasing	1.363m	5.042ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	24.820s	15.506us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	24.880s	18.135us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	47.640s	25.790us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.619m	58.389us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.830m	230.240ms	3	3	100.00
		flash_ctrl_hw_rma_reset	23.088m	380.323ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.670s	15.523us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	57.204m	277.915ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	13.384m	16.022ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.708m	3.822ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.133h	49.893ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.815m	732.785us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	58.810s	28.837us	39	40	97.50
		flash_ctrl_rw_evict_all_en	59.450s	283.046us	38	40	95.00
		flash_ctrl_re_evict	1.054m	74.289us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.846m	1.514ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.846m	1.514ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.448m	12.898ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	40.740s	264.686us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	18.565m	1.545ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	55.921m	43.144ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	22.625m	3.998ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	55.491m	550.327us	2	5	40.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	27.310s	118.259us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.522m	9.665ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	44.110s	26.847us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.340s	16.684us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	40.956m	251.550us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.288m	21.566ms	50	50	100.00
		flash_ctrl_otp_reset	3.938m	136.821us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.830m	230.240ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.747m	3.322ms	39	40	97.50
		flash_ctrl_intr_wr	1.981m	9.306ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.141m	208.185ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.075m	84.927ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.857m	4.105ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.894m	1.640ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	40.560s	42.108us	5	5	100.00
		flash_ctrl_ro_derr	3.048m	3.111ms	10	10	100.00
		flash_ctrl_rw_derr	4.189m	5.774ms	10	10	100.00
		flash_ctrl_derr_detect	4.516m	6.644ms	5	5	100.00
		flash_ctrl_integrity	11.166m	23.070ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	43.570s	23.853us	5	5	100.00
		flash_ctrl_ro_serr	2.831m	1.383ms	10	10	100.00
		flash_ctrl_rw_serr	4.921m	7.830ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.785m	3.150ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.963m	6.605ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.459m	7.370ms	18	20	90.00
		flash_ctrl_write_word_sweep	23.010s	66.778us	1	1	100.00
		flash_ctrl_read_word_sweep	20.910s	151.584us	1	1	100.00
		flash_ctrl_ro	2.465m	2.291ms	20	20	100.00
		flash_ctrl_rw	11.351m	3.970ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	52.120s	349.719us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.488m	98.892ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.837m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.820s	269.082us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	26.430s	18.997us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	31.440s	77.146us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	31.440s	77.146us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.232m	37.675us	5	5	100.00
		flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
		flash_ctrl_csr_aliasing	1.363m	5.042ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	53.920s	761.920us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.232m	37.675us	5	5	100.00
		flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
		flash_ctrl_csr_aliasing	1.363m	5.042ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	53.920s	761.920us	20	20	100.00
V2		TOTAL			1000	1013	98.72
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	25.610s	12.213us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
		flash_ctrl_tl_intg_err	24.151m	372.346us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	24.151m	372.346us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	24.151m	372.346us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	47.840s	134.083us	3	3	100.00
		flash_ctrl_wr_intg	25.570s	148.940us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.673m	81.754us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	3.938m	136.821us	80	80	100.00
		flash_ctrl_disable	44.110s	26.847us	50	50	100.00
		flash_ctrl_sec_info_access	2.025m	12.256ms	50	50	100.00
		flash_ctrl_connect	32.340s	16.684us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	21.820s	67.522us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	27.150s	64.870us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	25.850s	43.656us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	44.110s	26.847us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	47.840s	134.083us	3	3	100.00
		flash_ctrl_access_after_disable	25.520s	12.056us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	48.890s	26.924us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	44.110s	26.847us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	40.740s	264.686us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.351m	3.970ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.921m	7.830ms	9	10	90.00
		flash_ctrl_rw_derr	4.189m	5.774ms	10	10	100.00
		flash_ctrl_integrity	11.166m	23.070ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.830m	230.240ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	38.170s	915.538us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	24.450s	193.059us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	25.270s	28.659us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.913h	3.104ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.122m	74.436us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1267	1281	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	95.23	93.89	98.31	92.52	97.14	97.00	98.24

Failure Buckets

Job timed out after * minutes has 8 failures:
- Test flash_ctrl_error_prog_type has 3 failures.
  - 0.flash_ctrl_error_prog_type.92161624247014676533795630273951915132047858536115980694133411126886286667626
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.flash_ctrl_error_prog_type.71603756751337065937657670622424566753231224125996771921295577221238161905682
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.47549752106961022793971406771772781101381713635705645458532376872896905785360
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_wo has 2 failures.
  - 11.flash_ctrl_wo.99576621121320071323146338780195214440188812198806838950899088893054267817541
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest/run.log
```
  Job timed out after 60 minutes
```
  - 17.flash_ctrl_wo.47448262175515913050884458224253968278657448569702591074969846343739023735664
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 11.flash_ctrl_prog_reset.57038585919252827822699188576647507893971808092247169336803047638669058454509
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_rw has 1 failures.
  - 14.flash_ctrl_rw.19837593215864575877310820676893950413507833660493589856837332513624789346265
    Log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 11.flash_ctrl_rw_evict_all_en.23836055752494606437332418493584250681881078248638305152250516957045993936806
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 58303.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 58303.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.flash_ctrl_rw_evict_all_en.60169653611862463887295110320084819867868063600753815905258609128105301040839
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 42342.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 42342.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 2.flash_ctrl_phy_host_grant_err.112519010476791594890931986518822575965585876732692608608606856931044651816809
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 10199.8 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 10199.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw has 1 failures.
  - 19.flash_ctrl_rw.24510639475511656769707093279662361436170699783538977310287392602227072087889
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 3876326.6 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3876326.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e1cbd_fe47a0e8:ffffffff_fe47a0e* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 23.flash_ctrl_intr_rd.66258285837159653154256131914104211165614900201996835066485721885785006248021
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 833570.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    178e1cbd_fe47a0e8:ffffffff_fe47a0e8  mismatch!!
  UVM_INFO @ 833570.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 38.flash_ctrl_rw_evict.54729818798010384278413278931380148603505082233748505132408917037603279038951
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 42232.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 42232.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8a1401d614`