PWRMGR Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	31.617us	49	50	98.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.770s	35.193us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	19.246us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.500s	374.419us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	41.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.130s	52.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	19.246us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	41.391us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	wakeup	pwrmgr_wakeup	1.630s	253.221us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.630s	253.221us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.840s	38.993us	50	50	100.00
		pwrmgr_lowpower_invalid	0.740s	42.790us	50	50	100.00
V2	reset	pwrmgr_reset	1.340s	73.699us	50	50	100.00
		pwrmgr_reset_invalid	1.080s	115.947us	49	50	98.00
V2	main_power_glitch_reset	pwrmgr_reset	1.340s	73.699us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.690s	352.599us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.650s	267.912us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	58.812us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.330s	1.863ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.720s	18.569us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.540s	140.032us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.540s	140.032us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.770s	35.193us	5	5	100.00
		pwrmgr_csr_rw	0.730s	19.246us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	41.391us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	43.669us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.770s	35.193us	5	5	100.00
		pwrmgr_csr_rw	0.730s	19.246us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	41.391us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	43.669us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.660s	238.762us	20	20	100.00
		pwrmgr_sec_cm	1.500s	351.514us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.500s	351.514us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.500s	351.514us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.660s	238.762us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.000s	753.014us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.320s	891.565us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	76.267us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	30.563us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.500s	351.514us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.500s	351.514us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.500s	351.514us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	51.729us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	57.372us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.740s	299.176us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	19.246us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	19.246us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.440s	910.000us	0	50	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	43.710s	9.816ms	48	50	96.00
V3		TOTAL			48	100	48.00
		TOTAL			1066	1120	95.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 42 failures:
- Test pwrmgr_escalation_timeout has 42 failures.
  - 1.pwrmgr_escalation_timeout.68532274824543528999981792326467152263182027209752711787059441662035237286087
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_ERROR @  40081532 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
  UVM_INFO @  40081532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.pwrmgr_escalation_timeout.83918781581420327034629890645505757231856916645572850113932659385746732148537
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_ERROR @ 104491756 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
  UVM_INFO @ 104491756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 40 more failures.
UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:30) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 8 failures:
- Test pwrmgr_escalation_timeout has 8 failures.
  - 0.pwrmgr_escalation_timeout.44577761041622678684855138119273710737561303293408283976179770942703135029785
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 478716927 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 478716927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.pwrmgr_escalation_timeout.39272889695155262047536983082967476231974376950876283200355725764444225051395
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 245171760 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 245171760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_reset_invalid has 1 failures.
  - 0.pwrmgr_reset_invalid.48342107266317249231289511038644253937503386547029727558655443637366076844148
    Line 305, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 209412521 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 209412521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: pwrmgr_reg_block.wake_status reset value: * wake_status has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 6.pwrmgr_stress_all_with_rand_reset.96656027226815102940017555321969168035827255824892306972153163475637371777581
    Line 1216, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4341959099 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (44 [0x2c] vs 60 [0x3c]) Regname: pwrmgr_reg_block.wake_status reset value: 0x0 wake_status
  UVM_INFO @ 4341959099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test pwrmgr_smoke has 1 failures.

9.pwrmgr_smoke.45803799138905834919703755719216818789678747610622592006585158231269479611444
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest/run.log

  [make]: simulate
  cd /workspace/9.pwrmgr_smoke/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364865588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2364865588
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Dec 31 12:57 2023
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 40.pwrmgr_stress_all_with_rand_reset.68581329721687455168172129883118729268715996214939492460621238105456428538827
    Line 399, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 520316913 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 520316913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```