4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0 | 50 | 0.00 | ||
| V2 | control_clks | pwrmgr_wakeup | 0 | 50 | 0.00 | ||
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 0 | 50 | 0.00 | ||
| pwrmgr_lowpower_invalid | 0 | 50 | 0.00 | ||||
| V2 | reset | pwrmgr_reset | 0 | 50 | 0.00 | ||
| pwrmgr_reset_invalid | 0 | 50 | 0.00 | ||||
| V2 | main_power_glitch_reset | pwrmgr_reset | 0 | 50 | 0.00 | ||
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0 | 50 | 0.00 | ||
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 0 | 50 | 0.00 | ||
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0 | 50 | 0.00 | ||
| V2 | stress_all | pwrmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | pwrmgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| pwrmgr_csr_rw | 0 | 20 | 0.00 | ||||
| pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| pwrmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| pwrmgr_csr_rw | 0 | 20 | 0.00 | ||||
| pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| pwrmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 540 | 0.00 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| pwrmgr_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | prim_count_check | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 375 | 0.00 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 0 | 1120 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 12 | 12 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1122 failures:
0.pwrmgr_smoke.71594295406119241776986868430718153968990972519445763065244174450285439375285
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest/run.log
1.pwrmgr_smoke.11486612971569582439172947855015242636792116117929314814326175234771327527957
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest/run.log
... and 48 more failures.
0.pwrmgr_reset.110953299826473723625910042707016719833209774827732203240275063046898788192471
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset/latest/run.log
1.pwrmgr_reset.60210995329580426506112663148198372632547571620675903233945478731616224148033
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset/latest/run.log
... and 48 more failures.
0.pwrmgr_lowpower_wakeup_race.109435749307573304908093363545881867864256056837710885298631689364847758230150
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log
1.pwrmgr_lowpower_wakeup_race.95795842157548123291118072613369925320273968384425567035367366464303499736351
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log
... and 48 more failures.
0.pwrmgr_wakeup.92908708729051654424061514529144436531355012832504021013430438248084764243900
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
1.pwrmgr_wakeup.42212183327171266966069029913359380785874008606247820553038357662155851141193
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log
... and 48 more failures.
0.pwrmgr_wakeup_reset.94742531804884582427195499201334844028267115418375095921903995979654682066922
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
1.pwrmgr_wakeup_reset.53110021352889519865079035150609064541718352224711465197823401318684893240834
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.