cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.710s | 28.605us | 44 | 50 | 88.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.760s | 26.833us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.720s | 36.239us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.230s | 211.434us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.970s | 134.931us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.640s | 77.019us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.720s | 36.239us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 0.970s | 134.931us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 99 | 105 | 94.29 | |||
| V2 | wakeup | pwrmgr_wakeup | 1.450s | 287.085us | 47 | 50 | 94.00 |
| V2 | control_clks | pwrmgr_wakeup | 1.450s | 287.085us | 47 | 50 | 94.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.810s | 39.805us | 42 | 50 | 84.00 |
| pwrmgr_lowpower_invalid | 0.740s | 41.795us | 47 | 50 | 94.00 | ||
| V2 | reset | pwrmgr_reset | 1.260s | 65.773us | 48 | 50 | 96.00 |
| pwrmgr_reset_invalid | 1.070s | 101.866us | 45 | 50 | 90.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 1.260s | 65.773us | 48 | 50 | 96.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.840s | 341.960us | 48 | 50 | 96.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.380s | 219.079us | 44 | 50 | 88.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.950s | 59.613us | 48 | 50 | 96.00 |
| V2 | stress_all | pwrmgr_stress_all | 9.720s | 2.157ms | 44 | 50 | 88.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.800s | 33.478us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.500s | 169.276us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.500s | 169.276us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.760s | 26.833us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.720s | 36.239us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 0.970s | 134.931us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.900s | 511.648us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.760s | 26.833us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.720s | 36.239us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 0.970s | 134.931us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.900s | 511.648us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 503 | 540 | 93.15 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.750s | 187.360us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 2.120s | 652.762us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 2.120s | 652.762us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 2.120s | 652.762us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.750s | 187.360us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.920s | 823.843us | 49 | 50 | 98.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 3.950s | 867.334us | 48 | 50 | 96.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.970s | 71.759us | 45 | 50 | 90.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.660s | 29.741us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.120s | 652.762us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.120s | 652.762us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.120s | 652.762us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.660s | 43.222us | 47 | 50 | 94.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.720s | 63.364us | 47 | 50 | 94.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.640s | 268.381us | 49 | 50 | 98.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.720s | 36.239us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.720s | 36.239us | 20 | 20 | 100.00 |
| V2S | TOTAL | 360 | 375 | 96.00 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.160s | 309.352us | 47 | 50 | 94.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 34.800s | 9.292ms | 22 | 50 | 44.00 |
| V3 | TOTAL | 69 | 100 | 69.00 | |||
| TOTAL | 1031 | 1120 | 92.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 12 | 12 | 3 | 25.00 |
| V2S | 9 | 9 | 3 | 33.33 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.92 | 98.22 | 96.58 | 99.44 | 96.00 | 96.32 | 100.00 | 98.85 |
Exit reason: Error: User command failed Job returned non-zero exit code has 51 failures:
Test pwrmgr_stress_all has 2 failures.
2.pwrmgr_stress_all.54646929347584955314747925729698832154318087364857962262410753500643995848476
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log
[make]: simulate
cd /workspace/2.pwrmgr_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270072604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.2270072604
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:47 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
36.pwrmgr_stress_all.103796365879382533437216373496951040050210925056253096903355802356367554280730
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest/run.log
[make]: simulate
cd /workspace/36.pwrmgr_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372173082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.2372173082
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_disable_rom_integrity_check has 2 failures.
30.pwrmgr_disable_rom_integrity_check.18644119355360454373997301805856048749825172749638638714593770856585041571388
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest/run.log
[make]: simulate
cd /workspace/30.pwrmgr_disable_rom_integrity_check/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856714812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.856714812
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
37.pwrmgr_disable_rom_integrity_check.66220287951539636898080869916888163643920989641128883804262664144696819847057
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest/run.log
[make]: simulate
cd /workspace/37.pwrmgr_disable_rom_integrity_check/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329598353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.1329598353
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_glitch has 3 failures.
32.pwrmgr_glitch.13174923185260800937556221366171595471631013986840892061319494894662409329855
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest/run.log
[make]: simulate
cd /workspace/32.pwrmgr_glitch/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669064383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.669064383
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
34.pwrmgr_glitch.114138543394748043627680657947962078559507738837633911432822507723144166668245
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest/run.log
[make]: simulate
cd /workspace/34.pwrmgr_glitch/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952741333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1952741333
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test pwrmgr_reset_invalid has 5 failures.
32.pwrmgr_reset_invalid.12102133729189490329111545730378451530561852293020688889419091223572829109888
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest/run.log
[make]: simulate
cd /workspace/32.pwrmgr_reset_invalid/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340800640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1340800640
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
39.pwrmgr_reset_invalid.45006155647806088387990773024292994394767521217287699332495390564440533411415
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest/run.log
[make]: simulate
cd /workspace/39.pwrmgr_reset_invalid/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757455959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.1757455959
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test pwrmgr_lowpower_wakeup_race has 5 failures.
33.pwrmgr_lowpower_wakeup_race.69699686025951131331894432581476894863672817096609509250638142430769475073042
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest/run.log
[make]: simulate
cd /workspace/33.pwrmgr_lowpower_wakeup_race/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411232786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.1411232786
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
39.pwrmgr_lowpower_wakeup_race.39224995898264679051838925200926015973945624151731118059106524167935916082163
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest/run.log
[make]: simulate
cd /workspace/39.pwrmgr_lowpower_wakeup_race/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080370675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.4080370675
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
... and 12 more tests.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 33 failures:
0.pwrmgr_stress_all_with_rand_reset.19516999394347578642130844717558666763837636709321100564467296058014219436091
Line 2231, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2000530308 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 2000530308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all_with_rand_reset.93085605139610844312503140947721007614869880237604551828033585438667125135312
Line 3928, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1470971415 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 1470971415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
0.pwrmgr_stress_all.99333435985513640581402808892750557322357658067864684627714672100954566459904
Line 845, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 456033326 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 456033326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all.97126734601088161181605793465537739031902994979387213566852108821003376232713
Line 582, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 705315120 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 705315120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
7.pwrmgr_aborted_low_power.99481970391957927148302509478266042487936704439957789778485079504889115706957
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest/run.log
UVM_ERROR @ 53977596 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 53977596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.pwrmgr_aborted_low_power.94917997535612720679739224179999644087511961753467397005738750676818968062212
Line 255, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest/run.log
UVM_ERROR @ 84127694 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 84127694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 2 failures:
16.pwrmgr_escalation_timeout.94546118017643459131078438869718574576371248687488574969834795103235700253477
Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest/run.log
Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
UVM_ERROR @ 96939290 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
UVM_INFO @ 96939290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.pwrmgr_escalation_timeout.69638452530649400642402432406609625791045188981187738931446442673001186375684
Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest/run.log
Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
UVM_ERROR @ 94668880 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
UVM_INFO @ 94668880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: pwrmgr_reg_block.wake_status reset value: * wake_status has 1 failures:
18.pwrmgr_lowpower_wakeup_race.21943191718197758021454895518285054742813836475374426841339313440377288480421
Line 301, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 205255567 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (16 [0x10] vs 24 [0x18]) Regname: pwrmgr_reg_block.wake_status reset value: 0x0 wake_status
UVM_INFO @ 205255567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.60570300932416903053780342835428927430857223472085340011223760475015205131846
Line 702, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job pwrmgr-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
47.pwrmgr_smoke.68856389943816114045887561677408802831899235698480359652238449886214561613963
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest/run.log
Job ID: smart:2bb385df-7408-4e8b-b283-1daabc9c38f1