PWRMGR Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.810s	29.225us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	70.201us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	57.511us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.620s	320.862us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	136.442us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.540s	72.018us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	57.511us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	136.442us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.650s	237.285us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.650s	237.285us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.870s	32.206us	46	50	92.00
		pwrmgr_lowpower_invalid	0.860s	42.017us	50	50	100.00
V2	reset	pwrmgr_reset	1.450s	83.534us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	102.047us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.450s	83.534us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.800s	302.856us	48	50	96.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.570s	240.210us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.000s	63.295us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	11.740s	2.675ms	47	50	94.00
V2	intr_test	pwrmgr_intr_test	0.670s	46.401us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.810s	203.675us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.810s	203.675us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	70.201us	5	5	100.00
		pwrmgr_csr_rw	0.730s	57.511us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	136.442us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	49.593us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	70.201us	5	5	100.00
		pwrmgr_csr_rw	0.730s	57.511us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	136.442us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	49.593us	20	20	100.00
V2		TOTAL			530	540	98.15
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.760s	194.693us	20	20	100.00
		pwrmgr_sec_cm	2.260s	728.062us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.260s	728.062us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.260s	728.062us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.760s	194.693us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.280s	835.737us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.480s	828.449us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	73.636us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	30.248us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.260s	728.062us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.260s	728.062us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.260s	728.062us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	39.354us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	60.484us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.740s	276.675us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	57.511us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	57.511us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.090s	163.452us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	48.010s	9.083ms	34	50	68.00
V3		TOTAL			83	100	83.00
		TOTAL			1093	1120	97.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 24 failures:

Test pwrmgr_stress_all_with_rand_reset has 16 failures.

0.pwrmgr_stress_all_with_rand_reset.71783700359089731774061998738917407822681677730736576481403989286233442976031
Line 5705, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20032416634 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 20032416634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_stress_all_with_rand_reset.10863760590846074395819355152987572789767003678839210218668984627815312779896
Line 520, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 682849650 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 682849650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test pwrmgr_stress_all has 3 failures.

2.pwrmgr_stress_all.63282938181932167616654852746977328860954849993452654717783623512512174137977
Line 795, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 188661815 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 188661815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.pwrmgr_stress_all.61791984081028614477345501996141940356994142062554933587779725533979436285588
Line 530, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 383778218 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 383778218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test pwrmgr_aborted_low_power has 4 failures.

5.pwrmgr_aborted_low_power.7161352659094959907400449598453370691088900080542716796909951259226581666994
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  18223502 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  18223502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.pwrmgr_aborted_low_power.7469395283108155643966700640845464688226091696990081527296193670386337141607
Line 281, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  24542796 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  24542796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test pwrmgr_lowpower_wakeup_race has 1 failures.
- 12.pwrmgr_lowpower_wakeup_race.74231756965504771493355306554120979391156227500950957477749159404615027021079
  Line 292, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest/run.log
```
  UVM_ERROR @  99926210 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  99926210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwrmgr_wakeup_reset has 2 failures.
  - 11.pwrmgr_wakeup_reset.46701299935796514852365194520077225624796789572205234095551782632646154260891
    Line 373, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.pwrmgr_wakeup_reset.114740103475627431881241214331324234607398157400945063570964490484219883802905
    Line 377, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 36.pwrmgr_escalation_timeout.18480145402905621421306287588720746748214445351041724441382712100328071299362
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1724001093 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1724001093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```