PWRMGR Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.790s	49.572us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	48.471us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	36.939us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.560s	1.220ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	472.797us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.670s	57.032us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	36.939us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	472.797us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.590s	261.514us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.590s	261.514us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.820s	102.788us	46	50	92.00
		pwrmgr_lowpower_invalid	0.790s	43.327us	50	50	100.00
V2	reset	pwrmgr_reset	1.400s	82.480us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	110.053us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.400s	82.480us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.630s	336.727us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.730s	277.900us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	57.801us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.960s	1.554ms	44	50	88.00
V2	intr_test	pwrmgr_intr_test	0.700s	18.999us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.770s	248.089us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.770s	248.089us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	48.471us	5	5	100.00
		pwrmgr_csr_rw	0.720s	36.939us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	472.797us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.030s	47.321us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	48.471us	5	5	100.00
		pwrmgr_csr_rw	0.720s	36.939us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	472.797us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.030s	47.321us	20	20	100.00
V2		TOTAL			529	540	97.96
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.740s	474.482us	20	20	100.00
		pwrmgr_sec_cm	2.200s	687.485us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.200s	687.485us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.200s	687.485us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.740s	474.482us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.100s	798.212us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.350s	834.690us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	68.955us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	28.499us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.200s	687.485us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.200s	687.485us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.200s	687.485us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.740s	183.301us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	34.615us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.600s	279.276us	49	50	98.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	36.939us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	36.939us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	325.422us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	43.300s	9.494ms	25	50	50.00
V3		TOTAL			75	100	75.00
		TOTAL			1083	1120	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 36 failures:

Test pwrmgr_stress_all_with_rand_reset has 25 failures.

1.pwrmgr_stress_all_with_rand_reset.55386374522114704052087513162298687734508288280614997275282764869273367364150
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 118427781 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 118427781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all_with_rand_reset.71156405830863175269534487434090503198801534881970848571162306811883748993604
Line 465, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1280082376 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1280082376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test pwrmgr_stress_all has 6 failures.

1.pwrmgr_stress_all.16895042595310678563773615970784034864885702157311038963330143783887938807874
Line 1273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 505239327 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 505239327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all.9174741275651221303036199007456170361109483980702346991941484479133904982014
Line 1374, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 637863272 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 637863272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test pwrmgr_aborted_low_power has 4 failures.

2.pwrmgr_aborted_low_power.81509146491019712154380439491893602728328822293768584500835847356407990327440
Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  18175174 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  18175174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_aborted_low_power.75328242148906175946522356978013288940407127644474534237378012870055421357960
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  17370596 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  17370596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test pwrmgr_sec_cm_ctrl_config_regwen has 1 failures.
- 5.pwrmgr_sec_cm_ctrl_config_regwen.21380746700546993475616642299177019533057286524311527576098695500292644900562
  Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  41096069 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  41096069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_wakeup_reset has 1 failures.
  - 41.pwrmgr_wakeup_reset.73628923372709863891500125355672699799616946031652558767146142175544934162589
    Line 435, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```