4d88b9516c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.770s | 30.792us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.700s | 44.645us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.710s | 134.464us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.550s | 543.979us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.050s | 86.581us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.490s | 74.568us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.710s | 134.464us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 1.050s | 86.581us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 1.470s | 223.053us | 50 | 50 | 100.00 |
| V2 | control_clks | pwrmgr_wakeup | 1.470s | 223.053us | 50 | 50 | 100.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.850s | 33.265us | 50 | 50 | 100.00 |
| pwrmgr_lowpower_invalid | 0.800s | 40.227us | 49 | 50 | 98.00 | ||
| V2 | reset | pwrmgr_reset | 1.350s | 74.896us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.150s | 100.222us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 1.350s | 74.896us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.860s | 339.285us | 50 | 50 | 100.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.560s | 238.020us | 49 | 50 | 98.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.950s | 65.288us | 48 | 50 | 96.00 |
| V2 | stress_all | pwrmgr_stress_all | 9.380s | 2.598ms | 45 | 50 | 90.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.700s | 22.761us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.700s | 147.770us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.700s | 147.770us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.700s | 44.645us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.710s | 134.464us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.050s | 86.581us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.940s | 140.320us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.700s | 44.645us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.710s | 134.464us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.050s | 86.581us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.940s | 140.320us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 531 | 540 | 98.33 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.720s | 180.248us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 1.450s | 856.169us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 1.450s | 856.169us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 1.450s | 856.169us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.720s | 180.248us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 4.160s | 817.722us | 50 | 50 | 100.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.330s | 843.521us | 49 | 50 | 98.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.140s | 74.389us | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.790s | 30.810us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 1.450s | 856.169us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 1.450s | 856.169us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 1.450s | 856.169us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.800s | 47.251us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.680s | 40.249us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.690s | 257.791us | 50 | 50 | 100.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.710s | 134.464us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.710s | 134.464us | 20 | 20 | 100.00 |
| V2S | TOTAL | 373 | 375 | 99.47 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.130s | 166.134us | 48 | 50 | 96.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 34.760s | 6.822ms | 23 | 50 | 46.00 |
| V3 | TOTAL | 71 | 100 | 71.00 | |||
| TOTAL | 1080 | 1120 | 96.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 12 | 12 | 8 | 66.67 |
| V2S | 9 | 9 | 7 | 77.78 |
| V3 | 2 | 2 | 0 | 0.00 |
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 32 failures:
Test pwrmgr_stress_all_with_rand_reset has 26 failures.
0.pwrmgr_stress_all_with_rand_reset.106885180687498804185686518581265282414164197725250082261031560648296977344849
Line 626, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 444803394 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 444803394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_stress_all_with_rand_reset.34920622871255256052102064901364004372295687944999746578396416451923907550003
Line 1057, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2110543390 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 2110543390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Test pwrmgr_lowpower_wakeup_race has 1 failures.
2.pwrmgr_lowpower_wakeup_race.53332005144666668374074101884975667952001845093736099875695291286361337106770
Line 289, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 70027894 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 70027894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwrmgr_stress_all has 5 failures.
22.pwrmgr_stress_all.24865975926110735197541020436842812079581539041739519484728058904888305409317
Line 895, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 178485866 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 178485866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.pwrmgr_stress_all.110948088911099600699612990093960596938986424659357360985675120844274504645662
Line 903, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 1606206989 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 1606206989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 6 failures:
Test pwrmgr_sec_cm_rom_ctrl_intersig_mubi has 1 failures.
15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.53264923588102073211385787102116987085997018478143311004594059100511841366627
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest && /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319870051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3319870051
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 17 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_disable_rom_integrity_check has 2 failures.
16.pwrmgr_disable_rom_integrity_check.74691699469885935345317514280372713126896731958160987570111000175895010166637
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest/run.log
[make]: simulate
cd /workspace/16.pwrmgr_disable_rom_integrity_check/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060456301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.1060456301
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 17 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
19.pwrmgr_disable_rom_integrity_check.59394290771739861486251575690798432710185184876419293850213496737888694685020
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest/run.log
[make]: simulate
cd /workspace/19.pwrmgr_disable_rom_integrity_check/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432238428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.3432238428
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 17 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_sec_cm_rstmgr_intersig_mubi has 1 failures.
18.pwrmgr_sec_cm_rstmgr_intersig_mubi.8651371036985903330907296065379238750318230959768241287549201268597753572899
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157216291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.157216291
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 17 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_escalation_timeout has 1 failures.
19.pwrmgr_escalation_timeout.52039385564673032896561535074562436927407070673328901173748417905096737802701
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest/run.log
[make]: simulate
cd /workspace/19.pwrmgr_escalation_timeout/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479657933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1479657933
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 17 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr has 1 failures.
cov_merge
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/cov_merge/merged.vdb/cov_merge.log
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:220: cov_merge] Error 1
UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 1 failures:
9.pwrmgr_stress_all_with_rand_reset.84109259563416512023419584701205873581722185011052224504204000216548151947287
Line 6783, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8218331163 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8218331163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:
17.pwrmgr_lowpower_invalid.67980187325065631731888129256260515810777328592411574176145110846350413488799
Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest/run.log
UVM_FATAL @ 48354386 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
UVM_INFO @ 48354386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
31.pwrmgr_escalation_timeout.110311291292287869787914857902790184877003965542378112147085228536258301371460
Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest/run.log
Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
UVM_ERROR @ 96066933 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
UVM_INFO @ 96066933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: