PWRMGR Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.926us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	31.954us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	19.822us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.480s	273.942us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	153.276us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.480s	50.515us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	19.822us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	153.276us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.580s	306.532us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.580s	306.532us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.790s	52.783us	49	50	98.00
		pwrmgr_lowpower_invalid	0.770s	44.095us	50	50	100.00
V2	reset	pwrmgr_reset	1.400s	83.902us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	116.026us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.400s	83.902us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.870s	295.668us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.680s	277.258us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	65.091us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.040s	3.016ms	44	50	88.00
V2	intr_test	pwrmgr_intr_test	0.710s	17.445us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.690s	599.422us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.690s	599.422us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	31.954us	5	5	100.00
		pwrmgr_csr_rw	0.700s	19.822us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	153.276us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	33.914us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	31.954us	5	5	100.00
		pwrmgr_csr_rw	0.700s	19.822us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	153.276us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	33.914us	20	20	100.00
V2		TOTAL			533	540	98.70
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.780s	215.315us	20	20	100.00
		pwrmgr_sec_cm	1.700s	737.377us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.700s	737.377us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.700s	737.377us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.780s	215.315us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.150s	758.119us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.410s	850.958us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	71.160us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	40.455us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.700s	737.377us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.700s	737.377us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.700s	737.377us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.650s	74.169us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	50.092us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.640s	310.285us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	19.822us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	19.822us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	161.113us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	47.770s	10.227ms	29	50	58.00
V3		TOTAL			79	100	79.00
		TOTAL			1091	1120	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 27 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 20 failures.

    • 0.pwrmgr_stress_all_with_rand_reset.78505417171093064383487047304263197807492715849317241015314487747005389766855
      Line 8010, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7244118731 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 7244118731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.pwrmgr_stress_all_with_rand_reset.95254848711107233268491986952543652067598926327941212722099228952256871427301
      Line 687, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 366769614 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 366769614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test pwrmgr_stress_all has 6 failures.

    • 6.pwrmgr_stress_all.104998292797512560832101749614517540943488110040812452832716718497814772772216
      Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @  17745869 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  17745869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.pwrmgr_stress_all.11087435508599302135549662582950186640420611471508892087898175608777223790339
      Line 299, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @  49289760 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  49289760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

  • Test pwrmgr_aborted_low_power has 1 failures.

    • 48.pwrmgr_aborted_low_power.70115232644370729335661921698768611581939718425318005626544693046456430091529
      Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest/run.log

        UVM_ERROR @  53159579 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  53159579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 19.pwrmgr_stress_all_with_rand_reset.72932182114120428590378871789444233715338836095198444875929869589457347640613
      Line 4758, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3374541876 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 3374541876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.77244400868920630894126872826699598099745000906638442119732283630928643839278
      Line 734, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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