PWRMGR Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	31.243us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	27.023us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	19.649us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.750s	287.446us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	48.903us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.450s	230.660us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	19.649us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	48.903us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.600s	296.357us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.600s	296.357us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.840s	67.429us	45	50	90.00
		pwrmgr_lowpower_invalid	0.780s	43.120us	50	50	100.00
V2	reset	pwrmgr_reset	1.290s	65.821us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	107.591us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.290s	65.821us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.920s	367.442us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.500s	285.823us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.030s	51.054us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.370s	2.569ms	43	50	86.00
V2	intr_test	pwrmgr_intr_test	0.680s	48.811us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.810s	53.385us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.810s	53.385us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	27.023us	5	5	100.00
		pwrmgr_csr_rw	0.710s	19.649us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	48.903us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	42.704us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	27.023us	5	5	100.00
		pwrmgr_csr_rw	0.710s	19.649us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	48.903us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	42.704us	20	20	100.00
V2		TOTAL			528	540	97.78
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.680s	204.711us	20	20	100.00
		pwrmgr_sec_cm	2.230s	731.198us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.230s	731.198us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.230s	731.198us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.680s	204.711us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.510s	786.740us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.600s	937.636us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.090s	64.712us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.750s	28.802us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.230s	731.198us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.230s	731.198us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.230s	731.198us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	50.690us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	27.367us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.750s	241.883us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	19.649us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	19.649us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.260s	163.049us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	51.900s	20.078ms	28	50	56.00
V3		TOTAL			77	100	77.00
		TOTAL			1084	1120	96.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	8	88.89
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 31 failures:

Test pwrmgr_aborted_low_power has 5 failures.

0.pwrmgr_aborted_low_power.84476504774231165320421745750123994524199247598002605526996523846348832944717
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  23150007 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  23150007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_aborted_low_power.9324459978276772432382079906678557839415992096449352657036652652190613147946
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  55443540 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  55443540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test pwrmgr_stress_all_with_rand_reset has 19 failures.

1.pwrmgr_stress_all_with_rand_reset.20469878534795774045856921510556841797107864317715021109445514935134315545901
Line 1608, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2348523892 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2348523892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.pwrmgr_stress_all_with_rand_reset.11792948354741928109019775197132097753246900963436096183808312403890667493420
Line 1713, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2538887433 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2538887433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Test pwrmgr_stress_all has 7 failures.

7.pwrmgr_stress_all.36953559901317431072959069812362461758841750641880148603284716291901841775485
Line 1323, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 1220286707 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1220286707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_stress_all.105297706326587992390391178664798906017041438732960332552923993589168233450820
Line 504, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 343921200 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
  UVM_INFO @ 343921200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 2 failures:
- Test pwrmgr_stress_all_with_rand_reset has 2 failures.
  - 9.pwrmgr_stress_all_with_rand_reset.105711484512332646044831285179655652857667004546967726513118017176414782558069
    Line 4417, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19127027290 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 19127027290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.pwrmgr_stress_all_with_rand_reset.55605638398699792426532057126808718112756294082692641406309827293480440024733
    Line 867, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 771865705 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 771865705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 38.pwrmgr_escalation_timeout.103364964368475361583987514075240873790980880504137793882763444343630021425153
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1720033093 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1720033093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:99) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 41.pwrmgr_stress_all_with_rand_reset.26186810480674305562160261256088898548880277930725597460631082406128995290573
    Line 25615, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 20078057293 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
  UVM_INFO @ 20078057293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.
  - 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.19845850397958347139657467358786169121668476791899265436263745169709192681137
    Line 718, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
```
  UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```