93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0 | 50 | 0.00 | ||
| V2 | control_clks | pwrmgr_wakeup | 0 | 50 | 0.00 | ||
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 0 | 50 | 0.00 | ||
| pwrmgr_lowpower_invalid | 0 | 50 | 0.00 | ||||
| V2 | reset | pwrmgr_reset | 0 | 50 | 0.00 | ||
| pwrmgr_reset_invalid | 0 | 50 | 0.00 | ||||
| V2 | main_power_glitch_reset | pwrmgr_reset | 0 | 50 | 0.00 | ||
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0 | 50 | 0.00 | ||
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 0 | 50 | 0.00 | ||
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0 | 50 | 0.00 | ||
| V2 | stress_all | pwrmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | pwrmgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| pwrmgr_csr_rw | 0 | 20 | 0.00 | ||||
| pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| pwrmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| pwrmgr_csr_rw | 0 | 20 | 0.00 | ||||
| pwrmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| pwrmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 540 | 0.00 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| pwrmgr_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | prim_count_check | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 375 | 0.00 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 0 | 1120 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 12 | 12 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1122 failures:
0.pwrmgr_smoke.92045370039441788781237314370466740310752636103873334181840063713661726591521
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest/run.log
1.pwrmgr_smoke.90096804794796497971305158966574868609197353441720574420704207702259810431457
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest/run.log
... and 48 more failures.
0.pwrmgr_reset.94531250600512668814181263346209115535123807072720061238178326180900053543485
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset/latest/run.log
1.pwrmgr_reset.6266199768919224861447134174546178705327401410431398507913304273308174991256
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset/latest/run.log
... and 48 more failures.
0.pwrmgr_lowpower_wakeup_race.68602993961504287867959722116583334569547132739512071632440098161672159524469
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log
1.pwrmgr_lowpower_wakeup_race.31995995602362168243109610421539476047097527501189378347393094054141991029475
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log
... and 48 more failures.
0.pwrmgr_wakeup.44846703506807971314369336378249449597200286966306612174922795448987557118990
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
1.pwrmgr_wakeup.63790533509321960731120747595800963837549833632939482211768896845470392416976
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log
... and 48 more failures.
0.pwrmgr_wakeup_reset.78142267898639904975426067128525950165398990170911196172284670485769897536038
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
1.pwrmgr_wakeup_reset.61272225203979475445007439158611943167337901713308507346407871352641012594860
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
... and 48 more failures.
Job pwrmgr-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/default/build.log
Job ID: smart:e90ee41d-742e-44a7-83ba-447db923e6bb
Job pwrmgr-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/build.log
Job ID: smart:e381023d-4805-4f8f-97d9-0dc2c19f1c75