PWRMGR Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.810s	33.328us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	25.879us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	61.209us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.250s	602.483us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.090s	48.722us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	2.610s	165.365us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	61.209us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	48.722us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.440s	274.103us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.440s	274.103us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.850s	38.459us	46	50	92.00
		pwrmgr_lowpower_invalid	0.800s	42.442us	50	50	100.00
V2	reset	pwrmgr_reset	1.390s	70.754us	50	50	100.00
		pwrmgr_reset_invalid	1.160s	110.397us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.390s	70.754us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.750s	339.541us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.670s	289.610us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.990s	64.640us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.440s	2.003ms	45	50	90.00
V2	intr_test	pwrmgr_intr_test	0.710s	22.442us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.710s	229.693us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.710s	229.693us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	25.879us	5	5	100.00
		pwrmgr_csr_rw	0.710s	61.209us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	48.722us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	77.820us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	25.879us	5	5	100.00
		pwrmgr_csr_rw	0.710s	61.209us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	48.722us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	77.820us	20	20	100.00
V2		TOTAL			531	540	98.33
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.650s	191.086us	20	20	100.00
		pwrmgr_sec_cm	1.560s	923.579us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.560s	923.579us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.560s	923.579us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.650s	191.086us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.200s	716.227us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.580s	856.233us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	74.209us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	29.975us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.560s	923.579us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.560s	923.579us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.560s	923.579us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.780s	50.790us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	62.990us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.680s	236.921us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	61.209us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	61.209us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	161.225us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	46.410s	9.995ms	27	50	54.00
V3		TOTAL			76	100	76.00
		TOTAL			1087	1120	97.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 31 failures:

Test pwrmgr_stress_all_with_rand_reset has 22 failures.

0.pwrmgr_stress_all_with_rand_reset.62040977229421131097856774053447617593963477296835587550612319701967141616129
Line 850, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 710672096 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 710672096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_stress_all_with_rand_reset.61902658786675820634340531126851141924714682036874119388363387018734830046905
Line 435, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 185844467 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 185844467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Test pwrmgr_stress_all has 5 failures.

9.pwrmgr_stress_all.84663222880553130800630635746979522202456226499816552910562908461530012492869
Line 1267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 500945139 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 500945139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.pwrmgr_stress_all.8339494328278673104653859060463701877294394046295795095545428790336232975796
Line 957, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 817062631 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 817062631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test pwrmgr_aborted_low_power has 4 failures.

16.pwrmgr_aborted_low_power.52521141770606890237173410835406284380369829986991678592307955296022042842979
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  76035611 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  76035611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.pwrmgr_aborted_low_power.56928140281847787681796178321784673041233113898561339756598414981826013711662
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  39988421 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  39988421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 14.pwrmgr_stress_all_with_rand_reset.72582409786454551368762930140865949690657481590105407529278801737574269454932
    Line 2450, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 20990625205 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 20990625205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 34.pwrmgr_escalation_timeout.71912707554843358341941125480096635368544241598379274303186175599274265374940
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1232158256 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1232158256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```