PWRMGR Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	32.020us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	33.066us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	22.622us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.330s	212.520us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.010s	142.295us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.470s	79.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	22.622us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	142.295us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.290s	204.437us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.290s	204.437us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.110s	36.335us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	42.139us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	71.937us	50	50	100.00
		pwrmgr_reset_invalid	1.160s	108.388us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	71.937us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.510s	342.978us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	304.170us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.010s	60.174us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.360s	2.135ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.740s	21.956us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.610s	149.471us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.610s	149.471us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	33.066us	5	5	100.00
		pwrmgr_csr_rw	0.690s	22.622us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	142.295us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	67.258us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	33.066us	5	5	100.00
		pwrmgr_csr_rw	0.690s	22.622us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	142.295us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	67.258us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.790s	195.430us	20	20	100.00
		pwrmgr_sec_cm	2.240s	643.495us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.240s	643.495us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.240s	643.495us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.790s	195.430us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.300s	838.293us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.400s	943.176us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	90.881us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	29.413us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.240s	643.495us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.240s	643.495us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.240s	643.495us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	41.458us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	44.074us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.410s	293.047us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	22.622us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	22.622us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.090s	162.560us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.620s	17.059ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test pwrmgr_wakeup_reset has 1 failures.

    • 43.pwrmgr_wakeup_reset.62805045474729850732529082749884169348653258958613834522974024035043858207622
      Line 406, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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