PWRMGR Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	32.402us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	31.928us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	20.267us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.210s	431.097us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.940s	37.751us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.470s	58.275us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	20.267us	20	20	100.00
		pwrmgr_csr_aliasing	0.940s	37.751us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.370s	267.740us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.370s	267.740us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.020s	32.749us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	43.510us	50	50	100.00
V2	reset	pwrmgr_reset	1.080s	103.643us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	117.278us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.080s	103.643us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.420s	332.669us	48	50	96.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.330s	273.884us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	63.369us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.840s	2.189ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	22.030us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.100s	1.892ms	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.100s	1.892ms	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	31.928us	5	5	100.00
		pwrmgr_csr_rw	0.700s	20.267us	20	20	100.00
		pwrmgr_csr_aliasing	0.940s	37.751us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	89.812us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	31.928us	5	5	100.00
		pwrmgr_csr_rw	0.700s	20.267us	20	20	100.00
		pwrmgr_csr_aliasing	0.940s	37.751us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	89.812us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	208.177us	20	20	100.00
		pwrmgr_sec_cm	1.770s	676.328us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.770s	676.328us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.770s	676.328us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	208.177us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.500s	892.580us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.400s	861.987us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	66.592us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	30.544us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.770s	676.328us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.770s	676.328us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.770s	676.328us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	35.137us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.760s	54.373us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.480s	307.845us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	20.267us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	20.267us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.110s	163.445us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	35.460s	11.846ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.76078041178760564518952421849974975746248968419652831380304575087254846219601
      Line 605, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_wakeup_reset has 2 failures.

    • 18.pwrmgr_wakeup_reset.104748344886732371215441165760906548108078282804541082032588399848865461379595
      Line 413, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 42.pwrmgr_wakeup_reset.28398868794707397618327639975019505651701572476986949772627242813960112153920
      Line 389, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 23.pwrmgr_escalation_timeout.45107649885199684123997700735364365946020836839171934671314176687792100198982
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  98246869 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  98246869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.05.03_05.32.25
• 2024.05.01_04.48.30
• 2024.04.29_08.20.29
• 2024.04.26_08.14.20
• 2024.04.24_08.21.28