PWRMGR Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	28.451us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	29.177us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	47.340us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.370s	540.740us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	45.651us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.250s	64.033us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	47.340us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	45.651us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.340s	285.979us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.340s	285.979us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.090s	36.780us	50	50	100.00
		pwrmgr_lowpower_invalid	0.750s	45.471us	50	50	100.00
V2	reset	pwrmgr_reset	1.130s	105.104us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	107.142us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.130s	105.104us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.510s	310.937us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.240s	241.887us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	65.156us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.100s	2.111ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	50.298us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.660s	1.060ms	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.660s	1.060ms	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	29.177us	5	5	100.00
		pwrmgr_csr_rw	0.710s	47.340us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	45.651us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	180.757us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	29.177us	5	5	100.00
		pwrmgr_csr_rw	0.710s	47.340us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	45.651us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	180.757us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.700s	203.588us	20	20	100.00
		pwrmgr_sec_cm	2.070s	673.048us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.070s	673.048us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.070s	673.048us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.700s	203.588us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.330s	966.860us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.550s	930.387us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	103.769us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	27.795us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.070s	673.048us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.070s	673.048us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.070s	673.048us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	49.394us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	56.587us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.460s	276.558us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	47.340us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	47.340us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.020s	166.079us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	37.060s	11.811ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 29.pwrmgr_stress_all_with_rand_reset.77472363345466704138028421619912660076659369519306932874398897457360906649287
      Line 1985, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 11542983476 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 11542983476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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