PWRMGR Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	30.900us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	32.567us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	57.182us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.360s	641.970us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	24.949us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.560s	122.625us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	57.182us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.949us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.350s	262.411us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.350s	262.411us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.970s	46.988us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	40.741us	50	50	100.00
V2	reset	pwrmgr_reset	1.020s	90.590us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	108.341us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	90.590us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.460s	321.662us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.480s	252.621us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	63.895us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.880s	2.275ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	28.952us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.480s	50.395us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.480s	50.395us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	32.567us	5	5	100.00
		pwrmgr_csr_rw	0.740s	57.182us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.949us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	51.215us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	32.567us	5	5	100.00
		pwrmgr_csr_rw	0.740s	57.182us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.949us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	51.215us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.820s	479.932us	20	20	100.00
		pwrmgr_sec_cm	1.530s	722.128us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.530s	722.128us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.530s	722.128us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.820s	479.932us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.250s	870.851us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.490s	875.654us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	75.841us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	30.434us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.530s	722.128us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.530s	722.128us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.530s	722.128us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	49.484us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	63.226us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.460s	263.555us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	57.182us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	57.182us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.120s	159.231us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.830s	13.784ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 26.pwrmgr_stress_all_with_rand_reset.15989746507069025630916411560222426973465149137021177719515733294130025838715
      Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  64015964 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @  64015964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.04.29_08.20.29
• 2024.04.26_08.14.20
• 2024.04.24_08.21.28
• 2024.04.22_07.50.59
• 2024.04.19_05.30.14