PWRMGR Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	28.579us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	43.933us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	20.889us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.460s	621.539us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	24.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.260s	91.170us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	20.889us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	24.137us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.270s	249.436us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.270s	249.436us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.120s	34.316us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	44.735us	49	50	98.00
V2	reset	pwrmgr_reset	0.980s	81.812us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	109.213us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.980s	81.812us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.400s	315.500us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.390s	272.191us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	68.443us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.090s	1.841ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	30.916us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.630s	121.187us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.630s	121.187us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	43.933us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.889us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	24.137us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	144.833us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	43.933us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.889us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	24.137us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	144.833us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	180.039us	20	20	100.00
		pwrmgr_sec_cm	2.080s	674.743us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.080s	674.743us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.080s	674.743us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	180.039us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.500s	806.103us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.540s	810.586us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	66.318us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	28.549us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.080s	674.743us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.080s	674.743us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.080s	674.743us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	45.856us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	50.824us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.470s	256.069us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	20.889us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	20.889us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.090s	168.873us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	28.260s	22.390ms	42	50	84.00
V3		TOTAL			91	100	91.00
		TOTAL			1110	1120	99.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 4 failures:
- Test pwrmgr_stress_all_with_rand_reset has 4 failures.
  - 5.pwrmgr_stress_all_with_rand_reset.78446835689089074099266068996187728008450993515274508053073961482861523637906
    Line 3929, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6379554818 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 6379554818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.pwrmgr_stress_all_with_rand_reset.32226232618609856562285754819294049798673276922832463976449474106447353223846
    Line 2931, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7077001254 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 7077001254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 3 failures:
- Test pwrmgr_stress_all_with_rand_reset has 3 failures.
  - 4.pwrmgr_stress_all_with_rand_reset.39627084347647432394800063061810974460649095546811376550147336044141310445429
    Line 5213, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11483414055 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 11483414055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.pwrmgr_stress_all_with_rand_reset.48768887810207400651711551866405069589040585665541058400846347648167432118135
    Line 1503, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1845751869 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1845751869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 16.pwrmgr_escalation_timeout.64632702929592877095308704448060083041195854935579053508427836973629560389847
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1230540627 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1230540627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 25.pwrmgr_stress_all_with_rand_reset.104053443784528986075877341502611951185814757977252524695849871879554844544550
    Line 4607, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 19735418721 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 19735418721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:
- Test pwrmgr_lowpower_invalid has 1 failures.
  - 26.pwrmgr_lowpower_invalid.59911634660952719097510812338236240156015729512239405524626773481290576731400
    Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest/run.log
```
  UVM_FATAL @  40335452 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
  UVM_INFO @  40335452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

PWRMGR Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ae68723071`