PWRMGR Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	29.974us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	75.529us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	25.019us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.500s	1.208ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	49.188us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.630s	86.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	25.019us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	49.188us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.360s	270.261us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.360s	270.261us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.040s	29.636us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	37.760us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	81.811us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	112.633us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	81.811us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.620s	341.186us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.430s	292.162us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	69.886us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.100s	2.159ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.660s	144.352us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.030s	653.356us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.030s	653.356us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	75.529us	5	5	100.00
		pwrmgr_csr_rw	0.740s	25.019us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	49.188us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	66.700us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	75.529us	5	5	100.00
		pwrmgr_csr_rw	0.740s	25.019us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	49.188us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	66.700us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.690s	209.040us	20	20	100.00
		pwrmgr_sec_cm	2.310s	635.162us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.310s	635.162us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.310s	635.162us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.690s	209.040us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.370s	845.634us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.470s	860.301us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	65.152us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	30.097us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.310s	635.162us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.310s	635.162us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.310s	635.162us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	39.901us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	49.421us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.510s	293.201us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	25.019us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	25.019us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.100s	293.559us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	30.920s	7.990ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.18604741226943424805409323632955475295504887074999557854207681035256061944870
      Line 621, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 35.pwrmgr_stress_all_with_rand_reset.62954970097211428662469141126197790011292399469967727479701536405417463314411
      Line 838, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 3128413882 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 3128413882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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