PWRMGR Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	30.844us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	32.237us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	34.568us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.180s	816.305us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.950s	25.839us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.260s	44.510us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	34.568us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	25.839us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	227.778us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	227.778us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.160s	31.968us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	46.041us	50	50	100.00
V2	reset	pwrmgr_reset	0.980s	74.624us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	102.477us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.980s	74.624us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.600s	325.908us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	329.643us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.860s	52.712us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.330s	1.872ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	57.658us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.250s	266.092us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.250s	266.092us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	32.237us	5	5	100.00
		pwrmgr_csr_rw	0.710s	34.568us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	25.839us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	123.071us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	32.237us	5	5	100.00
		pwrmgr_csr_rw	0.710s	34.568us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	25.839us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	123.071us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.240s	540.889us	20	20	100.00
		pwrmgr_sec_cm	2.160s	629.319us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.160s	629.319us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.160s	629.319us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.240s	540.889us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.340s	897.646us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.520s	862.286us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.060s	74.722us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	28.876us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.160s	629.319us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.160s	629.319us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.160s	629.319us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	48.226us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.690s	43.912us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.500s	285.917us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	34.568us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	34.568us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	160.784us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	42.950s	12.095ms	49	50	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 24.pwrmgr_escalation_timeout.83165977690217546942587761034306730883761361630425014654876360498512540507142
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  96090184 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  96090184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 27.pwrmgr_stress_all_with_rand_reset.79136077119160480598361638149805789899721693665065833606376609421911093522458
      Line 7226, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 33119317401 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 33119317401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 29.pwrmgr_wakeup_reset.68592258566462057434113856991747570334632508811854697767713433194234057215940
      Line 381, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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