PWRMGR Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	31.421us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	63.485us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	59.724us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.440s	2.551ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	49.281us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.430s	73.916us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	59.724us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	49.281us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.280s	245.443us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.280s	245.443us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.070s	35.056us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	44.367us	50	50	100.00
V2	reset	pwrmgr_reset	1.040s	96.049us	50	50	100.00
		pwrmgr_reset_invalid	1.160s	106.722us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.040s	96.049us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.430s	294.459us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.450s	310.765us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	50.127us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.450s	2.575ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	39.432us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.770s	121.387us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.770s	121.387us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	63.485us	5	5	100.00
		pwrmgr_csr_rw	0.720s	59.724us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	49.281us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	50.554us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	63.485us	5	5	100.00
		pwrmgr_csr_rw	0.720s	59.724us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	49.281us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	50.554us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.810s	197.272us	20	20	100.00
		pwrmgr_sec_cm	1.940s	677.136us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.940s	677.136us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.940s	677.136us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.810s	197.272us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.360s	885.965us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.540s	924.015us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	75.521us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	28.412us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.940s	677.136us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.940s	677.136us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.940s	677.136us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.740s	35.887us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	53.462us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.570s	316.234us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	59.724us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	59.724us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	160.689us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	34.530s	10.387ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test pwrmgr_wakeup_reset has 1 failures.

    • 0.pwrmgr_wakeup_reset.75572408615202823700233465184679185717175631408177754322878995344966563989076
      Line 380, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.05.15_03.18.44
• 2024.05.13_04.07.16
• 2024.05.10_04.54.15
• 2024.05.08_04.03.29
• 2024.05.06_05.18.10