PWRMGR Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	52.164us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	139.379us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	21.121us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.260s	2.302ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	90.004us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.550s	105.921us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	21.121us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	90.004us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.480s	249.572us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.480s	249.572us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.140s	37.311us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	44.346us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	86.768us	50	50	100.00
		pwrmgr_reset_invalid	1.130s	102.777us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	86.768us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.580s	322.090us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.350s	290.608us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.930s	68.640us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	7.510s	1.921ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	17.769us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.520s	256.347us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.520s	256.347us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	139.379us	5	5	100.00
		pwrmgr_csr_rw	0.690s	21.121us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	90.004us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	44.412us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	139.379us	5	5	100.00
		pwrmgr_csr_rw	0.690s	21.121us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	90.004us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	44.412us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.670s	202.793us	20	20	100.00
		pwrmgr_sec_cm	2.110s	631.826us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.110s	631.826us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.110s	631.826us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.670s	202.793us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.350s	819.968us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.610s	802.145us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	74.749us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	28.405us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.110s	631.826us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.110s	631.826us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.110s	631.826us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	71.488us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	56.192us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.380s	239.221us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	21.121us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	21.121us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	167.533us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	45.310s	13.591ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:
  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 30.pwrmgr_disable_rom_integrity_check.97802197062941177878534694786776484831008505520390806853073054350192381892095
      Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  30022698 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  30022698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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