PWRMGR Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.258us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.750s	35.536us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	21.170us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.480s	1.427ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	174.195us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.470s	74.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	21.170us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	174.195us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.370s	267.908us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.370s	267.908us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.040s	36.573us	50	50	100.00
		pwrmgr_lowpower_invalid	0.820s	44.095us	50	50	100.00
V2	reset	pwrmgr_reset	1.020s	66.308us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	91.894us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	66.308us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.540s	332.905us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.280s	219.808us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.890s	67.263us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.710s	2.385ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	32.545us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.750s	124.673us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.750s	124.673us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.750s	35.536us	5	5	100.00
		pwrmgr_csr_rw	0.740s	21.170us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	174.195us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	40.251us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.750s	35.536us	5	5	100.00
		pwrmgr_csr_rw	0.740s	21.170us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	174.195us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	40.251us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.650s	434.064us	20	20	100.00
		pwrmgr_sec_cm	1.920s	603.360us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.920s	603.360us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.920s	603.360us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.650s	434.064us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.270s	781.380us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.470s	930.155us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.000s	70.793us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	29.506us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.920s	603.360us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.920s	603.360us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.920s	603.360us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	49.553us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	51.682us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.440s	283.540us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	21.170us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	21.170us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	197.491us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.170s	12.166ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 2.pwrmgr_stress_all_with_rand_reset.50291817420553644104409806610240328777079627179427468325535873663222858568873
      Line 738, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 1862310015 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 1862310015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 8.pwrmgr_stress_all_with_rand_reset.62128586595737382536358200047442990164596319663115628035362044095921110648356
      Line 1515, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 673732139 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 673732139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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