PWRMGR Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	40.077us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.740s	73.266us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	24.532us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.320s	816.861us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	134.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.710s	154.778us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	24.532us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	134.308us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.360s	217.146us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.360s	217.146us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.180s	36.480us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	37.465us	50	50	100.00
V2	reset	pwrmgr_reset	1.000s	67.183us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	101.674us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.000s	67.183us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.680s	313.997us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.410s	322.743us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	59.370us	48	50	96.00
V2	stress_all	pwrmgr_stress_all	6.850s	1.650ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.720s	34.649us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.440s	51.075us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.440s	51.075us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.740s	73.266us	5	5	100.00
		pwrmgr_csr_rw	0.730s	24.532us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	134.308us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	47.922us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.740s	73.266us	5	5	100.00
		pwrmgr_csr_rw	0.730s	24.532us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	134.308us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	47.922us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.280s	1.737ms	20	20	100.00
		pwrmgr_sec_cm	2.330s	799.923us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.330s	799.923us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.330s	799.923us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.280s	1.737ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.380s	931.726us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.460s	820.083us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.030s	69.975us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	30.399us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.330s	799.923us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.330s	799.923us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.330s	799.923us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.730s	42.896us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	40.728us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.400s	229.361us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	24.532us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	24.532us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	631.956us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	31.290s	9.932ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 2 failures:
  • Test pwrmgr_disable_rom_integrity_check has 2 failures.

    • 15.pwrmgr_disable_rom_integrity_check.32316034732511213310904694641217175037828891683186598983562837548213070207444
      Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  20845135 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  20845135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.pwrmgr_disable_rom_integrity_check.49868762523306941818553775165479086858674558944962591104089201732713483660018
      Line 286, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  33729270 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  33729270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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