PWRMGR Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	29.147us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.730s	35.306us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	21.533us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.490s	442.716us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.070s	163.438us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.460s	95.517us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	21.533us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	163.438us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.430s	292.657us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.430s	292.657us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.050s	46.640us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	42.967us	49	50	98.00
V2	reset	pwrmgr_reset	1.050s	106.851us	50	50	100.00
		pwrmgr_reset_invalid	1.130s	111.275us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.050s	106.851us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.510s	219.405us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.480s	277.771us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	59.786us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.460s	2.405ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.660s	18.080us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.660s	222.784us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.660s	222.784us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.730s	35.306us	5	5	100.00
		pwrmgr_csr_rw	0.740s	21.533us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	163.438us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	48.580us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.730s	35.306us	5	5	100.00
		pwrmgr_csr_rw	0.740s	21.533us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	163.438us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	48.580us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	209.003us	20	20	100.00
		pwrmgr_sec_cm	2.110s	686.020us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.110s	686.020us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.110s	686.020us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	209.003us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.330s	850.912us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.580s	818.769us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	63.546us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	29.612us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.110s	686.020us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.110s	686.020us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.110s	686.020us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	42.332us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	61.419us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.410s	267.774us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	21.533us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	21.533us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.160s	318.025us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	44.500s	13.337ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 15.pwrmgr_lowpower_invalid.89523526321118204013767949803663035751837246151077208360606437663038235516002
      Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  40631771 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  40631771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 33.pwrmgr_stress_all_with_rand_reset.52799799803396427344090748860099324773376076967518582996756376315453534961111
      Line 5169, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 18330495945 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 18330495945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.06.11_12.16.22
• 2024.06.10_07.08.59
• 2024.06.08_13.30.09
• 2024.06.07_05.13.56
• 2024.06.06_11.23.53