PWRMGR Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.770s 28.411us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.690s 32.499us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 19.573us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.880s 270.133us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.070s 72.436us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.290s 50.961us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 19.573us 20 20 100.00
pwrmgr_csr_aliasing 1.070s 72.436us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.330s 273.514us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.330s 273.514us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.120s 34.289us 50 50 100.00
pwrmgr_lowpower_invalid 0.760s 42.692us 50 50 100.00
V2 reset pwrmgr_reset 1.040s 81.889us 50 50 100.00
pwrmgr_reset_invalid 1.120s 106.969us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.040s 81.889us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.630s 308.455us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.460s 284.582us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.910s 61.064us 50 50 100.00
V2 stress_all pwrmgr_stress_all 8.210s 1.778ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.700s 20.099us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.920s 409.220us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.920s 409.220us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.690s 32.499us 5 5 100.00
pwrmgr_csr_rw 0.720s 19.573us 20 20 100.00
pwrmgr_csr_aliasing 1.070s 72.436us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 49.752us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.690s 32.499us 5 5 100.00
pwrmgr_csr_rw 0.720s 19.573us 20 20 100.00
pwrmgr_csr_aliasing 1.070s 72.436us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 49.752us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.840s 1.321ms 20 20 100.00
pwrmgr_sec_cm 2.060s 835.402us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.060s 835.402us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.060s 835.402us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.840s 1.321ms 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.330s 754.018us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.520s 885.950us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.020s 77.060us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.730s 30.554us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.060s 835.402us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.060s 835.402us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.060s 835.402us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.720s 38.385us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.700s 61.605us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.380s 284.172us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 19.573us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 19.573us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.060s 405.733us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 36.380s 10.811ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Past Results