PWRMGR Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	51.250us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	24.690us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	20.780us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.470s	325.846us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.110s	27.112us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.340s	67.219us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	20.780us	20	20	100.00
		pwrmgr_csr_aliasing	1.110s	27.112us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.400s	293.802us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.400s	293.802us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.160s	29.564us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	51.158us	50	50	100.00
V2	reset	pwrmgr_reset	1.080s	95.529us	50	50	100.00
		pwrmgr_reset_invalid	1.170s	95.922us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.080s	95.529us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.510s	302.208us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.450s	277.201us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.890s	52.470us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.710s	2.354ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	19.670us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.800s	77.845us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.800s	77.845us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	24.690us	5	5	100.00
		pwrmgr_csr_rw	0.700s	20.780us	20	20	100.00
		pwrmgr_csr_aliasing	1.110s	27.112us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	98.241us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	24.690us	5	5	100.00
		pwrmgr_csr_rw	0.700s	20.780us	20	20	100.00
		pwrmgr_csr_aliasing	1.110s	27.112us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	98.241us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.480s	1.135ms	20	20	100.00
		pwrmgr_sec_cm	1.500s	907.483us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.500s	907.483us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.500s	907.483us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.480s	1.135ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.250s	887.774us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.300s	870.330us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	75.532us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	31.698us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.500s	907.483us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.500s	907.483us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.500s	907.483us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	48.592us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	60.838us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.280s	295.950us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	20.780us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	20.780us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.030s	161.452us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	39.870s	11.060ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test pwrmgr_lowpower_wakeup_race has 1 failures.

    • 9.pwrmgr_lowpower_wakeup_race.110037120306647905777869746429231589050020164290000751097161042810695727213092
      Line 345, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.06.25_11.55.09
• 2024.06.24_08.53.59
• 2024.06.23_08.17.22
• 2024.06.22_11.55.01
• 2024.06.14_07.41.29