PWRMGR Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	31.394us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	26.555us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.780s	21.166us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.280s	2.510ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.090s	220.411us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.600s	127.115us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.780s	21.166us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	220.411us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.440s	313.973us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.440s	313.973us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.080s	34.053us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	39.030us	50	50	100.00
V2	reset	pwrmgr_reset	1.010s	71.343us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	101.234us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.010s	71.343us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.490s	287.875us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.260s	263.401us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	69.515us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.400s	2.744ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.720s	21.308us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.840s	519.502us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.840s	519.502us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	26.555us	5	5	100.00
		pwrmgr_csr_rw	0.780s	21.166us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	220.411us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	48.780us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	26.555us	5	5	100.00
		pwrmgr_csr_rw	0.780s	21.166us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	220.411us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	48.780us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.100s	412.505us	20	20	100.00
		pwrmgr_sec_cm	2.330s	691.078us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.330s	691.078us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.330s	691.078us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.100s	412.505us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.440s	959.943us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.540s	914.991us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.070s	66.755us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.069us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.330s	691.078us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.330s	691.078us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.330s	691.078us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	58.843us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	47.040us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.360s	258.849us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.780s	21.166us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.780s	21.166us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	170.418us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	32.480s	9.499ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.97940981633840525594837647474955395468096360025131753426934985276828775473646
      Line 630, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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