PWRMGR Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	30.668us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	23.263us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	23.347us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.590s	275.331us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	226.189us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.530s	126.419us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	23.347us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	226.189us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	298.604us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	298.604us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.130s	32.455us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	37.248us	50	50	100.00
V2	reset	pwrmgr_reset	1.040s	97.373us	50	50	100.00
		pwrmgr_reset_invalid	1.080s	106.689us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.040s	97.373us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.470s	265.239us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.360s	285.664us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	57.523us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.480s	2.425ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	25.496us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.920s	154.459us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.920s	154.459us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	23.263us	5	5	100.00
		pwrmgr_csr_rw	0.690s	23.347us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	226.189us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	63.201us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	23.263us	5	5	100.00
		pwrmgr_csr_rw	0.690s	23.347us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	226.189us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	63.201us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.660s	190.915us	20	20	100.00
		pwrmgr_sec_cm	2.060s	640.816us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.060s	640.816us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.060s	640.816us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.660s	190.915us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.410s	849.604us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.410s	917.641us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	75.522us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	30.757us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.060s	640.816us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.060s	640.816us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.060s	640.816us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	47.635us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	53.775us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.350s	293.124us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	23.347us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	23.347us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	157.981us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	37.730s	13.375ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 11.pwrmgr_wakeup_reset.107113246607268105556326751970036779441205044954374364418927834677180873006307
      Line 380, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.91167962184911162082221906046978436753911277708947525513782354832240578035382
      Line 629, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 12.pwrmgr_escalation_timeout.83200942176222560086065256915641021036435181495501409957165150488994894279653
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  95556916 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  95556916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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