PWRMGR Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.760s 29.853us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.730s 73.169us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.730s 32.538us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.330s 271.637us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.050s 44.052us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.330s 52.663us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.730s 32.538us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 44.052us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.340s 291.564us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.340s 291.564us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.150s 36.947us 50 50 100.00
pwrmgr_lowpower_invalid 0.750s 45.178us 50 50 100.00
V2 reset pwrmgr_reset 1.020s 77.983us 50 50 100.00
pwrmgr_reset_invalid 1.140s 95.870us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.020s 77.983us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.540s 285.487us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.320s 302.887us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.920s 68.245us 50 50 100.00
V2 stress_all pwrmgr_stress_all 8.020s 2.378ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.710s 23.107us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.560s 111.778us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.560s 111.778us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.730s 73.169us 5 5 100.00
pwrmgr_csr_rw 0.730s 32.538us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 44.052us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 69.062us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.730s 73.169us 5 5 100.00
pwrmgr_csr_rw 0.730s 32.538us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 44.052us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 69.062us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.860s 307.574us 20 20 100.00
pwrmgr_sec_cm 2.170s 640.406us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.170s 640.406us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.170s 640.406us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.860s 307.574us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.470s 868.502us 49 50 98.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.580s 882.710us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.990s 65.965us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.680s 32.436us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.170s 640.406us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.170s 640.406us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.170s 640.406us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.680s 50.153us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.720s 59.645us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.400s 315.706us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.730s 32.538us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.730s 32.538us 20 20 100.00
V2S TOTAL 374 375 99.73
V3 escalation_timeout pwrmgr_escalation_timeout 1.160s 610.097us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 36.860s 17.236ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1119 1120 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 8 88.89
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Failure Buckets

Past Results