PWRMGR Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.609us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	42.914us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.750s	24.537us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.150s	853.920us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.960s	127.979us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.820s	55.537us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.750s	24.537us	20	20	100.00
		pwrmgr_csr_aliasing	0.960s	127.979us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	301.235us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	301.235us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.000s	54.671us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	66.837us	50	50	100.00
V2	reset	pwrmgr_reset	0.960s	77.038us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	113.201us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.960s	77.038us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.530s	296.268us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.410s	295.685us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.870s	67.158us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.290s	1.799ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.710s	60.482us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.700s	257.490us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.700s	257.490us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	42.914us	5	5	100.00
		pwrmgr_csr_rw	0.750s	24.537us	20	20	100.00
		pwrmgr_csr_aliasing	0.960s	127.979us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	123.384us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	42.914us	5	5	100.00
		pwrmgr_csr_rw	0.750s	24.537us	20	20	100.00
		pwrmgr_csr_aliasing	0.960s	127.979us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	123.384us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.780s	203.396us	20	20	100.00
		pwrmgr_sec_cm	1.670s	711.014us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.670s	711.014us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.670s	711.014us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.780s	203.396us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.320s	878.226us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.470s	890.587us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	69.427us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	32.739us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.670s	711.014us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.670s	711.014us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.670s	711.014us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	42.629us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	30.387us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.350s	300.087us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.750s	24.537us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.750s	24.537us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.030s	623.813us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	33.130s	9.862ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:749) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.52367460316637722868760011677575235181968782129888902341054933815819175272286
      Line 3268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2745603837 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2745603837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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