PWRMGR Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	30.182us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	25.823us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	73.308us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.530s	1.170ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.090s	53.305us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.370s	114.582us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	73.308us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	53.305us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.340s	259.251us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.340s	259.251us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.110s	33.651us	50	50	100.00
		pwrmgr_lowpower_invalid	0.750s	41.089us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	93.918us	50	50	100.00
		pwrmgr_reset_invalid	1.090s	93.228us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	93.918us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.560s	312.135us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.290s	297.449us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.850s	58.140us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.630s	1.751ms	49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.680s	22.159us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.370s	1.243ms	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.370s	1.243ms	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	25.823us	5	5	100.00
		pwrmgr_csr_rw	0.710s	73.308us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	53.305us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	365.185us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	25.823us	5	5	100.00
		pwrmgr_csr_rw	0.710s	73.308us	20	20	100.00
		pwrmgr_csr_aliasing	1.090s	53.305us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	365.185us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.860s	212.479us	20	20	100.00
		pwrmgr_sec_cm	2.170s	639.972us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.170s	639.972us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.170s	639.972us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.860s	212.479us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.260s	833.766us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.430s	831.320us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	67.311us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	28.555us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.170s	639.972us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.170s	639.972us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.170s	639.972us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	46.251us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.690s	39.006us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.330s	318.292us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	73.308us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	73.308us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	179.758us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	35.250s	11.277ms	49	50	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.69	98.23	96.58	90.98	96.00	96.37	100.00	98.69

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:752) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 44.pwrmgr_stress_all_with_rand_reset.102889769947124778064209457307452964434475586306386243261593205059207481484969
      Line 1094, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1254797953 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1254797953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all has 1 failures.

    • 44.pwrmgr_stress_all.5402927812471627002636508389991053729523523696911464494210220760475042696306
      Line 675, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 1851578602 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 1851578602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 45.pwrmgr_escalation_timeout.24710038243714296508005368787557412650739581706525933876487818091400346065961
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  94802942 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  94802942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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