PWRMGR Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.304us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.740s	62.990us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	19.369us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.410s	1.101ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	158.293us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.500s	55.974us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	19.369us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	158.293us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.310s	193.955us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.310s	193.955us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.990s	82.796us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	44.610us	50	50	100.00
V2	reset	pwrmgr_reset	1.010s	89.140us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	97.605us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.010s	89.140us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.560s	295.444us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.380s	300.610us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	55.139us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.430s	2.153ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	25.077us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.040s	685.485us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.040s	685.485us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.740s	62.990us	5	5	100.00
		pwrmgr_csr_rw	0.730s	19.369us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	158.293us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	226.803us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.740s	62.990us	5	5	100.00
		pwrmgr_csr_rw	0.730s	19.369us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	158.293us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	226.803us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.780s	233.831us	20	20	100.00
		pwrmgr_sec_cm	2.260s	619.768us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.260s	619.768us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.260s	619.768us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.780s	233.831us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.360s	819.694us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.360s	888.071us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	73.498us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.161us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.260s	619.768us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.260s	619.768us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.260s	619.768us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	68.095us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	47.272us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.340s	297.722us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	19.369us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	19.369us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.120s	166.886us	48	50	96.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	37.630s	10.170ms	48	50	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:752) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 9.pwrmgr_stress_all_with_rand_reset.36397126713877113062133094169746132916302108786456974232686316431169283509454
      Line 4328, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7121270605 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7121270605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.pwrmgr_stress_all_with_rand_reset.69665910346038037962072528159064318679269690316111579182455643999441488241242
      Line 5442, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14036390313 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 14036390313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 2 failures:

  • Test pwrmgr_escalation_timeout has 2 failures.

    • 46.pwrmgr_escalation_timeout.85022864148069763809811709605527047896718800281598709758728182644458410402185
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @ 230858432 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @ 230858432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 48.pwrmgr_escalation_timeout.43606148019123784842122014756547681462808485523132670603473738941835806743740
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  94666091 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  94666091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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