PWRMGR Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.780s 29.877us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.680s 27.807us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 18.043us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.370s 1.264ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.040s 166.317us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.530s 55.005us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 18.043us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 166.317us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.320s 257.165us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.320s 257.165us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.110s 35.842us 50 50 100.00
pwrmgr_lowpower_invalid 0.770s 43.028us 50 50 100.00
V2 reset pwrmgr_reset 1.140s 97.760us 50 50 100.00
pwrmgr_reset_invalid 1.170s 111.558us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.140s 97.760us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.480s 321.947us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.180s 277.389us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.890s 59.560us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.490s 3.027ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.760s 18.768us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.730s 1.144ms 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.730s 1.144ms 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.680s 27.807us 5 5 100.00
pwrmgr_csr_rw 0.720s 18.043us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 166.317us 5 5 100.00
pwrmgr_same_csr_outstanding 0.920s 34.962us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.680s 27.807us 5 5 100.00
pwrmgr_csr_rw 0.720s 18.043us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 166.317us 5 5 100.00
pwrmgr_same_csr_outstanding 0.920s 34.962us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.740s 230.888us 20 20 100.00
pwrmgr_sec_cm 1.510s 875.458us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.510s 875.458us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.510s 875.458us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.740s 230.888us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.350s 858.941us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.490s 938.451us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.010s 73.027us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.710s 29.079us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.510s 875.458us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.510s 875.458us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.510s 875.458us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.730s 37.127us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.740s 54.872us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.340s 241.392us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 18.043us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 18.043us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.100s 184.991us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 42.650s 12.291ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Past Results