PWRMGR Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.730s 35.830us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.710s 31.649us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 22.828us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.620s 313.695us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.030s 220.349us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.240s 45.037us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 22.828us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 220.349us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.390s 325.598us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.390s 325.598us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.070s 31.145us 50 50 100.00
pwrmgr_lowpower_invalid 0.810s 43.639us 50 50 100.00
V2 reset pwrmgr_reset 1.040s 78.961us 50 50 100.00
pwrmgr_reset_invalid 1.210s 103.699us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.040s 78.961us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.710s 321.984us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.350s 267.488us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.900s 71.489us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.800s 1.942ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.700s 62.790us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.830s 2.185ms 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.830s 2.185ms 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.710s 31.649us 5 5 100.00
pwrmgr_csr_rw 0.720s 22.828us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 220.349us 5 5 100.00
pwrmgr_same_csr_outstanding 0.990s 37.765us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.710s 31.649us 5 5 100.00
pwrmgr_csr_rw 0.720s 22.828us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 220.349us 5 5 100.00
pwrmgr_same_csr_outstanding 0.990s 37.765us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 2.250s 457.694us 20 20 100.00
pwrmgr_sec_cm 2.090s 652.480us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.090s 652.480us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.090s 652.480us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 2.250s 457.694us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.310s 852.169us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.410s 922.326us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.990s 67.042us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.720s 30.465us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.090s 652.480us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.090s 652.480us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.090s 652.480us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.750s 52.490us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.700s 54.612us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.350s 280.128us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 22.828us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 22.828us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.150s 166.881us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 36.100s 10.677ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.93 98.23 96.43 99.44 96.00 96.37 100.00 99.02

Past Results