PWRMGR Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.760s 33.011us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.730s 61.412us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.740s 25.245us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.110s 220.946us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.970s 84.947us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.220s 84.893us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.740s 25.245us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 84.947us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.470s 294.027us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.470s 294.027us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.160s 34.894us 50 50 100.00
pwrmgr_lowpower_invalid 0.770s 43.103us 50 50 100.00
V2 reset pwrmgr_reset 1.010s 138.676us 50 50 100.00
pwrmgr_reset_invalid 1.120s 104.582us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.010s 138.676us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.810s 341.781us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.380s 296.411us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.940s 53.629us 49 50 98.00
V2 stress_all pwrmgr_stress_all 8.060s 2.497ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.720s 20.192us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 3.070s 145.376us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 3.070s 145.376us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.730s 61.412us 5 5 100.00
pwrmgr_csr_rw 0.740s 25.245us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 84.947us 5 5 100.00
pwrmgr_same_csr_outstanding 0.980s 136.015us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.730s 61.412us 5 5 100.00
pwrmgr_csr_rw 0.740s 25.245us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 84.947us 5 5 100.00
pwrmgr_same_csr_outstanding 0.980s 136.015us 20 20 100.00
V2 TOTAL 539 540 99.81
V2S tl_intg_err pwrmgr_tl_intg_err 1.760s 203.806us 20 20 100.00
pwrmgr_sec_cm 2.030s 681.010us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.030s 681.010us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.030s 681.010us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.760s 203.806us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.370s 873.580us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.400s 946.862us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.020s 200.988us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.710s 29.423us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.030s 681.010us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.030s 681.010us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.030s 681.010us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.710s 50.312us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.730s 49.706us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.300s 261.759us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.740s 25.245us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.740s 25.245us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.050s 160.948us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 39.480s 12.904ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1119 1120 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 11 91.67
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Failure Buckets

Past Results