PWRMGR Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.770s 42.101us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.770s 26.675us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.690s 35.074us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.230s 664.916us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.010s 26.330us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.020s 43.157us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.690s 35.074us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 26.330us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.260s 276.051us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.260s 276.051us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.970s 29.764us 50 50 100.00
pwrmgr_lowpower_invalid 0.780s 41.108us 50 50 100.00
V2 reset pwrmgr_reset 1.060s 77.089us 50 50 100.00
pwrmgr_reset_invalid 1.110s 111.334us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.060s 77.089us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.670s 346.458us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.430s 316.443us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.890s 55.848us 50 50 100.00
V2 stress_all pwrmgr_stress_all 8.290s 2.475ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.730s 25.672us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.720s 50.229us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.720s 50.229us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.770s 26.675us 5 5 100.00
pwrmgr_csr_rw 0.690s 35.074us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 26.330us 5 5 100.00
pwrmgr_same_csr_outstanding 1.010s 150.244us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.770s 26.675us 5 5 100.00
pwrmgr_csr_rw 0.690s 35.074us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 26.330us 5 5 100.00
pwrmgr_same_csr_outstanding 1.010s 150.244us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.880s 199.419us 20 20 100.00
pwrmgr_sec_cm 2.210s 671.245us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.210s 671.245us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.210s 671.245us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.880s 199.419us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.440s 827.207us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.610s 804.829us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.990s 77.783us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.700s 29.474us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.210s 671.245us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.210s 671.245us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.210s 671.245us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.760s 49.244us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.780s 100.759us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.450s 264.362us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.690s 35.074us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.690s 35.074us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.120s 165.661us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 37.350s 11.502ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Past Results