PWRMGR Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.770s 29.228us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.770s 32.995us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.710s 76.357us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.490s 1.426ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.040s 50.090us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.310s 110.394us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.710s 76.357us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 50.090us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.360s 305.685us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.360s 305.685us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.180s 36.214us 50 50 100.00
pwrmgr_lowpower_invalid 0.820s 45.634us 50 50 100.00
V2 reset pwrmgr_reset 1.020s 104.754us 50 50 100.00
pwrmgr_reset_invalid 1.130s 102.084us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.020s 104.754us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.490s 300.379us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.310s 295.549us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.950s 73.655us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.430s 2.142ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.690s 119.814us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.850s 614.730us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.850s 614.730us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.770s 32.995us 5 5 100.00
pwrmgr_csr_rw 0.710s 76.357us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 50.090us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 38.931us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.770s 32.995us 5 5 100.00
pwrmgr_csr_rw 0.710s 76.357us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 50.090us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 38.931us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.680s 162.385us 20 20 100.00
pwrmgr_sec_cm 2.130s 699.923us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.130s 699.923us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.130s 699.923us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.680s 162.385us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.500s 754.619us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.560s 920.332us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.000s 66.700us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.730s 30.015us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.130s 699.923us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.130s 699.923us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.130s 699.923us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.720s 41.018us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.730s 51.645us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.390s 284.230us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.710s 76.357us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.710s 76.357us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.130s 298.103us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 35.360s 9.661ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.74 98.23 96.58 90.98 96.00 96.37 100.00 99.02

Past Results