PWRMGR Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	29.529us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	76.843us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	19.687us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.700s	1.214ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	44.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.410s	115.614us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	19.687us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	44.718us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.340s	230.232us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.340s	230.232us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.140s	33.431us	50	50	100.00
		pwrmgr_lowpower_invalid	0.820s	45.513us	50	50	100.00
V2	reset	pwrmgr_reset	1.010s	66.331us	50	50	100.00
		pwrmgr_reset_invalid	1.190s	104.620us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.010s	66.331us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.530s	316.294us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.370s	293.104us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	52.509us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.520s	2.971ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.710s	19.339us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.900s	1.314ms	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.900s	1.314ms	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	76.843us	5	5	100.00
		pwrmgr_csr_rw	0.710s	19.687us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	44.718us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	60.682us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	76.843us	5	5	100.00
		pwrmgr_csr_rw	0.710s	19.687us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	44.718us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	60.682us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.710s	222.307us	20	20	100.00
		pwrmgr_sec_cm	1.650s	775.365us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.650s	775.365us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.650s	775.365us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.710s	222.307us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.450s	850.763us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.480s	877.346us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	66.731us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	29.654us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.650s	775.365us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.650s	775.365us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.650s	775.365us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	38.583us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	53.559us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.480s	294.683us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	19.687us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	19.687us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	162.206us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	32.500s	10.071ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 46.pwrmgr_stress_all_with_rand_reset.34994521538680413112829563804412211449392137410434874207828131378469457444630
      Line 6555, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 61587530672 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 61587530672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 47.pwrmgr_wakeup_reset.46988619553836911702571178958795193160724419335237461075465821299685165390663
      Line 406, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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