PWRMGR Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.780s	31.729us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	55.417us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.680s	61.978us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.470s	1.397ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	25.960us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.740s	60.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.680s	61.978us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	25.960us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.350s	256.198us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.350s	256.198us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.080s	47.441us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	44.493us	50	50	100.00
V2	reset	pwrmgr_reset	1.080s	79.770us	50	50	100.00
		pwrmgr_reset_invalid	1.170s	112.443us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.080s	79.770us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.640s	326.895us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.430s	327.606us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	67.797us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.670s	2.180ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	57.082us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.630s	473.331us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.630s	473.331us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	55.417us	5	5	100.00
		pwrmgr_csr_rw	0.680s	61.978us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	25.960us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	39.134us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	55.417us	5	5	100.00
		pwrmgr_csr_rw	0.680s	61.978us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	25.960us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	39.134us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.670s	200.224us	20	20	100.00
		pwrmgr_sec_cm	2.010s	645.481us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.010s	645.481us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.010s	645.481us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.670s	200.224us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.430s	827.949us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.380s	839.269us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	67.758us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	29.853us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.010s	645.481us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.010s	645.481us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.010s	645.481us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	127.662us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	63.570us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.160s	203.838us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.680s	61.978us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.680s	61.978us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.110s	297.158us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.600s	11.121ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_lowpower_wakeup_race has 1 failures.

    • 8.pwrmgr_lowpower_wakeup_race.76521504737418581752987304742293732000652034037727630833654783899798224181108
      Line 349, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:104) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 22.pwrmgr_stress_all_with_rand_reset.10391730160240946924703369302491697186448346708238947906108355918080439555371
      Line 3173, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 21580947637 ps: (cip_base_vseq.sv:104) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 21580947637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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