PWRMGR Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.730s 30.223us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.730s 66.684us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.700s 22.583us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.970s 77.932us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.040s 145.214us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.520s 123.693us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.700s 22.583us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 145.214us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.340s 261.227us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.340s 261.227us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.080s 34.970us 50 50 100.00
pwrmgr_lowpower_invalid 0.790s 46.773us 50 50 100.00
V2 reset pwrmgr_reset 1.020s 81.219us 50 50 100.00
pwrmgr_reset_invalid 1.110s 104.975us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.020s 81.219us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.540s 329.135us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.340s 271.167us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.950s 64.223us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.650s 2.387ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.710s 23.795us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 3.500s 176.126us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 3.500s 176.126us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.730s 66.684us 5 5 100.00
pwrmgr_csr_rw 0.700s 22.583us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 145.214us 5 5 100.00
pwrmgr_same_csr_outstanding 0.950s 48.944us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.730s 66.684us 5 5 100.00
pwrmgr_csr_rw 0.700s 22.583us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 145.214us 5 5 100.00
pwrmgr_same_csr_outstanding 0.950s 48.944us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.890s 449.500us 20 20 100.00
pwrmgr_sec_cm 2.130s 685.485us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.130s 685.485us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.130s 685.485us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.890s 449.500us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.290s 847.756us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.480s 883.642us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.020s 73.969us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.690s 29.788us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.130s 685.485us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.130s 685.485us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.130s 685.485us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.730s 44.327us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.760s 57.166us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.430s 265.024us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.700s 22.583us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.700s 22.583us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.070s 1.351ms 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 49.300s 13.809ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Past Results