PWRMGR Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.740s 31.409us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.690s 108.113us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.700s 19.860us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.650s 642.649us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.040s 37.149us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.070s 66.219us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.700s 19.860us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 37.149us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.250s 273.934us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.250s 273.934us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.130s 32.235us 50 50 100.00
pwrmgr_lowpower_invalid 0.760s 83.071us 50 50 100.00
V2 reset pwrmgr_reset 1.040s 85.762us 50 50 100.00
pwrmgr_reset_invalid 1.160s 106.944us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.040s 85.762us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.590s 331.574us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.390s 258.350us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 1.040s 76.040us 50 50 100.00
V2 stress_all pwrmgr_stress_all 5.900s 1.829ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.690s 28.623us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.760s 131.070us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.760s 131.070us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.690s 108.113us 5 5 100.00
pwrmgr_csr_rw 0.700s 19.860us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 37.149us 5 5 100.00
pwrmgr_same_csr_outstanding 0.890s 41.495us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.690s 108.113us 5 5 100.00
pwrmgr_csr_rw 0.700s 19.860us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 37.149us 5 5 100.00
pwrmgr_same_csr_outstanding 0.890s 41.495us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.820s 205.863us 20 20 100.00
pwrmgr_sec_cm 2.260s 654.005us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.260s 654.005us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.260s 654.005us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.820s 205.863us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.230s 816.801us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.380s 899.517us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.000s 70.012us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.690s 35.641us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.260s 654.005us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.260s 654.005us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.260s 654.005us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 41.336us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.740s 50.219us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.260s 230.614us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.700s 19.860us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.700s 19.860us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.070s 611.405us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 42.480s 13.686ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Past Results