PWRMGR Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.730s 47.735us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.770s 31.450us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 19.470us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.330s 282.208us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.080s 42.152us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.540s 56.374us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 19.470us 20 20 100.00
pwrmgr_csr_aliasing 1.080s 42.152us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.210s 280.982us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.210s 280.982us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.060s 37.309us 50 50 100.00
pwrmgr_lowpower_invalid 0.840s 42.869us 50 50 100.00
V2 reset pwrmgr_reset 1.050s 79.507us 50 50 100.00
pwrmgr_reset_invalid 1.090s 99.103us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.050s 79.507us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.520s 342.326us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.230s 254.605us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.890s 69.175us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.210s 1.972ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.690s 51.465us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.660s 637.019us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.660s 637.019us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.770s 31.450us 5 5 100.00
pwrmgr_csr_rw 0.720s 19.470us 20 20 100.00
pwrmgr_csr_aliasing 1.080s 42.152us 5 5 100.00
pwrmgr_same_csr_outstanding 0.970s 128.203us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.770s 31.450us 5 5 100.00
pwrmgr_csr_rw 0.720s 19.470us 20 20 100.00
pwrmgr_csr_aliasing 1.080s 42.152us 5 5 100.00
pwrmgr_same_csr_outstanding 0.970s 128.203us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.940s 205.968us 20 20 100.00
pwrmgr_sec_cm 1.710s 736.331us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.710s 736.331us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.710s 736.331us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.940s 205.968us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.150s 853.831us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.440s 865.138us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.970s 76.190us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.690s 31.497us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.710s 736.331us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.710s 736.331us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.710s 736.331us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.700s 70.814us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.750s 46.278us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.330s 280.344us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 19.470us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 19.470us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.130s 165.735us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 30.270s 9.342ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Past Results