PWRMGR Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.720s 31.426us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.730s 61.792us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 22.476us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.650s 323.683us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.020s 60.993us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.830s 60.366us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 22.476us 20 20 100.00
pwrmgr_csr_aliasing 1.020s 60.993us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.220s 189.037us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.220s 189.037us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.940s 39.661us 50 50 100.00
pwrmgr_lowpower_invalid 0.780s 44.641us 50 50 100.00
V2 reset pwrmgr_reset 1.080s 82.970us 50 50 100.00
pwrmgr_reset_invalid 1.120s 103.030us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.080s 82.970us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.350s 246.619us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.410s 279.447us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.900s 74.403us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.820s 1.888ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.700s 21.209us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 3.440s 378.686us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 3.440s 378.686us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.730s 61.792us 5 5 100.00
pwrmgr_csr_rw 0.720s 22.476us 20 20 100.00
pwrmgr_csr_aliasing 1.020s 60.993us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 89.411us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.730s 61.792us 5 5 100.00
pwrmgr_csr_rw 0.720s 22.476us 20 20 100.00
pwrmgr_csr_aliasing 1.020s 60.993us 5 5 100.00
pwrmgr_same_csr_outstanding 0.940s 89.411us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.730s 200.745us 20 20 100.00
pwrmgr_sec_cm 2.270s 677.570us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.270s 677.570us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.270s 677.570us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.730s 200.745us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.370s 915.892us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.300s 868.094us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.030s 75.213us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.680s 29.454us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.270s 677.570us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.270s 677.570us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.270s 677.570us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 32.470us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.710s 50.867us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.370s 276.750us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 22.476us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 22.476us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.020s 316.728us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 37.730s 11.456ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Past Results