PWRMGR Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.780s	31.863us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.730s	29.785us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	56.056us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.970s	73.594us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	88.131us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.670s	123.303us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	56.056us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	88.131us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.410s	248.419us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.410s	248.419us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.150s	35.993us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	44.379us	50	50	100.00
V2	reset	pwrmgr_reset	1.100s	74.786us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	111.963us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.100s	74.786us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.470s	274.376us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	289.415us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.870s	59.705us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.080s	2.440ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.720s	38.620us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.570s	681.330us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.570s	681.330us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.730s	29.785us	5	5	100.00
		pwrmgr_csr_rw	0.730s	56.056us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	88.131us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	49.823us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.730s	29.785us	5	5	100.00
		pwrmgr_csr_rw	0.730s	56.056us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	88.131us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	49.823us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.770s	206.141us	20	20	100.00
		pwrmgr_sec_cm	2.340s	675.743us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.340s	675.743us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.340s	675.743us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.770s	206.141us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.390s	931.018us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.540s	918.109us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	75.891us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	32.253us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.340s	675.743us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.340s	675.743us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.340s	675.743us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	48.175us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	61.965us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.390s	241.284us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	56.056us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	56.056us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.140s	300.691us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	19.810s	5.422ms	46	50	92.00
V3		TOTAL			95	100	95.00
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 3 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 3 failures.

    • 10.pwrmgr_stress_all_with_rand_reset.23070015444977148867784890767993804796196502572409185624168941938990644324744
      Line 2546, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 12934252782 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 12934252782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.pwrmgr_stress_all_with_rand_reset.47212465784951095603436342952552098687460961755254433774824675556029848196837
      Line 2815, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 13091339162 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 13091339162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:767) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 5.pwrmgr_stress_all_with_rand_reset.62445432042024070354939932342059562070831233998197071207394159063471160931627
      Line 1573, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2035179408 ps: (cip_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2035179408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 25.pwrmgr_escalation_timeout.8349981806341677308081779419042506531897976165378218456733797807204739207445
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  94175202 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  94175202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_lowpower_wakeup_race has 1 failures.

    • 40.pwrmgr_lowpower_wakeup_race.55770332961004052659616114024920405098083057945887715200593120767036613340461
      Line 353, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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