Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.89 98.23 96.58 99.62 96.00 96.37 99.74 98.69


Total test records in report: 1100
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1011 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.852298964 Aug 27 05:19:42 AM UTC 24 Aug 27 05:19:57 AM UTC 24 19557337 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4026569937 Aug 27 05:19:42 AM UTC 24 Aug 27 05:19:57 AM UTC 24 36976932 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3879898892 Aug 27 05:19:27 AM UTC 24 Aug 27 05:19:57 AM UTC 24 98730920 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.205095531 Aug 27 05:19:07 AM UTC 24 Aug 27 05:19:57 AM UTC 24 28066500 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.191271644 Aug 27 05:19:42 AM UTC 24 Aug 27 05:19:57 AM UTC 24 46764570 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1153781818 Aug 27 05:19:18 AM UTC 24 Aug 27 05:19:57 AM UTC 24 23838183 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1584219701 Aug 27 05:19:08 AM UTC 24 Aug 27 05:19:57 AM UTC 24 143668432 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.757253205 Aug 27 05:19:37 AM UTC 24 Aug 27 05:19:57 AM UTC 24 203260531 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.333595299 Aug 27 05:19:42 AM UTC 24 Aug 27 05:19:57 AM UTC 24 61829978 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1330228235 Aug 27 05:19:42 AM UTC 24 Aug 27 05:19:57 AM UTC 24 56271248 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3609649744 Aug 27 05:19:27 AM UTC 24 Aug 27 05:19:57 AM UTC 24 252529685 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2601855486 Aug 27 05:19:28 AM UTC 24 Aug 27 05:19:57 AM UTC 24 39405262 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3651918592 Aug 27 05:19:42 AM UTC 24 Aug 27 05:19:57 AM UTC 24 217494056 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3292171646 Aug 27 05:19:07 AM UTC 24 Aug 27 05:19:57 AM UTC 24 111817029 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1087978888 Aug 27 05:19:28 AM UTC 24 Aug 27 05:19:57 AM UTC 24 201362278 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.609190081 Aug 27 05:19:29 AM UTC 24 Aug 27 05:20:00 AM UTC 24 100677327 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3128006009 Aug 27 05:19:07 AM UTC 24 Aug 27 05:19:58 AM UTC 24 32885204 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.869006686 Aug 27 05:19:46 AM UTC 24 Aug 27 05:19:58 AM UTC 24 51680263 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3384144799 Aug 27 05:19:56 AM UTC 24 Aug 27 05:19:58 AM UTC 24 35106631 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.685690543 Aug 27 05:19:29 AM UTC 24 Aug 27 05:19:59 AM UTC 24 329063282 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3493293920 Aug 27 05:19:27 AM UTC 24 Aug 27 05:19:59 AM UTC 24 835626144 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.636904329 Aug 27 05:19:22 AM UTC 24 Aug 27 05:19:59 AM UTC 24 109645943 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1299426870 Aug 27 05:19:22 AM UTC 24 Aug 27 05:19:59 AM UTC 24 82352155 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.1449455324 Aug 27 05:19:29 AM UTC 24 Aug 27 05:19:59 AM UTC 24 57032783 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3592883664 Aug 27 05:19:23 AM UTC 24 Aug 27 05:19:59 AM UTC 24 44060861 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.865232199 Aug 27 05:19:22 AM UTC 24 Aug 27 05:20:00 AM UTC 24 45066497 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2937662168 Aug 27 05:19:23 AM UTC 24 Aug 27 05:20:00 AM UTC 24 148281392 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.384851670 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 18121601 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.243442227 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 41712462 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2373026713 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 50209386 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1686550248 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 91434046 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3707022069 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 108078452 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1157256352 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 27204651 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.2569901981 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:00 AM UTC 24 56717261 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.72684752 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 313838096 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2648039468 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 104900942 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1216632128 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 110344697 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2415416512 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 27350476 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1067447404 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 43455394 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1760617517 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 52931236 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1426225627 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 47942510 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.707768383 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:01 AM UTC 24 21824867 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.550277016 Aug 27 05:19:59 AM UTC 24 Aug 27 05:20:02 AM UTC 24 42679624 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.4181466818 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 48775437 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.657862869 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 53216673 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1281267652 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 274067993 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.756826768 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 51672554 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2203040294 Aug 27 05:19:59 AM UTC 24 Aug 27 05:20:02 AM UTC 24 21848295 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2909100896 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 39080570 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2675881322 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 128894763 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.566360644 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 286486910 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2230090216 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 130697037 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3649776861 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:02 AM UTC 24 270959628 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1650338557 Aug 27 05:19:59 AM UTC 24 Aug 27 05:20:02 AM UTC 24 1412734205 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1218439249 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:03 AM UTC 24 136672944 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.4171194088 Aug 27 05:19:58 AM UTC 24 Aug 27 05:20:03 AM UTC 24 234236616 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3474550962 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:03 AM UTC 24 27094183 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.702141589 Aug 27 05:20:01 AM UTC 24 Aug 27 05:20:04 AM UTC 24 93892637 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.4039161097 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 37614100 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3198265639 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 70920189 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.936767314 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 19842205 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2337946755 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 130893006 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.1774966743 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 20067182 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3887444683 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 33140868 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.3790417759 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 37537713 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3540944943 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 40826584 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.3028808698 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 19995732 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.753016459 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 69287024 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1314897401 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 38185443 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2452606008 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 40815043 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2734292343 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 111558863 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.1655176786 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 46331971 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3516270024 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 107495840 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2029871058 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 112200343 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2598058255 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 24776687 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2596227634 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 48321849 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3916794976 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 37047748 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.991593558 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 46578755 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.422204863 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 96435838 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.795628657 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 21784549 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.1119904807 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 18413115 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3787621013 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 217270790 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1062622215 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 48519443 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.679651823 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 15396170 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.3284709783 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:05 AM UTC 24 78565464 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.1367544917 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 41519828 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3977350992 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 43285607 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.567780200 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 60216779 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.4243535266 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 59206350 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3686984634 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 18764861 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.1486586486 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 62454644 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.1309831309 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 24709177 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.975304615 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 29863374 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.4059164227 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:04 AM UTC 24 61532354 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1095799769 Aug 27 05:20:02 AM UTC 24 Aug 27 05:20:05 AM UTC 24 201407755 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.4290240827 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 32961911 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.3825515974 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 38338476 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.3356995196 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 16445904 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.1354885257 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 47930209 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.628242494 Aug 27 05:20:47 AM UTC 24 Aug 27 05:20:48 AM UTC 24 29915655 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2998145796
Short name T9
Test name
Test status
Simulation time 383616499 ps
CPU time 0.86 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998145796 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2998145796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2146110427
Short name T17
Test name
Test status
Simulation time 475230483 ps
CPU time 1.52 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 210452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146110427 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.2146110427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.8524589
Short name T29
Test name
Test status
Simulation time 90448541 ps
CPU time 0.86 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 220156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8524589 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.8524589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.1203406746
Short name T13
Test name
Test status
Simulation time 728761739 ps
CPU time 1.61 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 236880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203406746 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1203406746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1588859138
Short name T23
Test name
Test status
Simulation time 371218395 ps
CPU time 1.97 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 210476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1588859138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr
_stress_all_with_rand_reset.1588859138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2647612517
Short name T28
Test name
Test status
Simulation time 1606773651 ps
CPU time 2.07 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647612517 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2647612517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.552217382
Short name T33
Test name
Test status
Simulation time 58941958 ps
CPU time 0.67 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552217382 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.552217382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2062359468
Short name T97
Test name
Test status
Simulation time 183600293 ps
CPU time 1.46 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:27 AM UTC 24
Peak memory 211108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062359468 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.2062359468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.4150750895
Short name T82
Test name
Test status
Simulation time 46967750 ps
CPU time 0.55 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150750895 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.4150750895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2532589034
Short name T99
Test name
Test status
Simulation time 190995459 ps
CPU time 0.8 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532589034 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.2532589034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.258153484
Short name T154
Test name
Test status
Simulation time 23889297 ps
CPU time 0.58 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 206820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258153484 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.258153484
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3772840539
Short name T11
Test name
Test status
Simulation time 208556006 ps
CPU time 0.81 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772840539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3772840539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2249103949
Short name T103
Test name
Test status
Simulation time 275495515 ps
CPU time 1.54 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249103949 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2249103949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.139102429
Short name T62
Test name
Test status
Simulation time 90940380 ps
CPU time 0.76 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139102429 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.139102429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.650943527
Short name T57
Test name
Test status
Simulation time 9946418362 ps
CPU time 12.25 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:12 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=650943527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr
_stress_all_with_rand_reset.650943527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2343981153
Short name T117
Test name
Test status
Simulation time 885946536 ps
CPU time 3.06 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:52 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343981153 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2343981153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1299426870
Short name T79
Test name
Test status
Simulation time 82352155 ps
CPU time 0.85 seconds
Started Aug 27 05:19:22 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299426870 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1299426870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3545350200
Short name T5
Test name
Test status
Simulation time 22909150 ps
CPU time 0.57 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545350200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3545350200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1157256352
Short name T158
Test name
Test status
Simulation time 27204651 ps
CPU time 0.54 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157256352 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1157256352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1087978888
Short name T151
Test name
Test status
Simulation time 201362278 ps
CPU time 1.32 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 210964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087978888 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.1087978888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.906362293
Short name T146
Test name
Test status
Simulation time 68238528 ps
CPU time 0.91 seconds
Started Aug 27 05:16:12 AM UTC 24
Finished Aug 27 05:16:14 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906362293 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.906362293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3383988160
Short name T144
Test name
Test status
Simulation time 58182028 ps
CPU time 0.69 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383988160 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.3383988160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4171887062
Short name T113
Test name
Test status
Simulation time 136275284 ps
CPU time 0.93 seconds
Started Aug 27 05:19:43 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171887062 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.4171887062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.1455695041
Short name T18
Test name
Test status
Simulation time 55823013 ps
CPU time 0.87 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455695041 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1455695041
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.1263138408
Short name T56
Test name
Test status
Simulation time 2508279129 ps
CPU time 10.01 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1263138408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg
r_stress_all_with_rand_reset.1263138408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.865232199
Short name T1031
Test name
Test status
Simulation time 45066497 ps
CPU time 1.48 seconds
Started Aug 27 05:19:22 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 209288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865232199 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.865232199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1584219701
Short name T1017
Test name
Test status
Simulation time 143668432 ps
CPU time 0.65 seconds
Started Aug 27 05:19:08 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584219701 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1584219701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3592883664
Short name T1030
Test name
Test status
Simulation time 44060861 ps
CPU time 1.06 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3592883664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w
ith_rand_reset.3592883664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1153781818
Short name T1016
Test name
Test status
Simulation time 23838183 ps
CPU time 0.54 seconds
Started Aug 27 05:19:18 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153781818 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1153781818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.205095531
Short name T1014
Test name
Test status
Simulation time 28066500 ps
CPU time 0.64 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205095531 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.205095531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.636904329
Short name T1028
Test name
Test status
Simulation time 109645943 ps
CPU time 0.67 seconds
Started Aug 27 05:19:22 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 210056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636904329 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.636904329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3128006009
Short name T1024
Test name
Test status
Simulation time 32885204 ps
CPU time 1.37 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:58 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128006009 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3128006009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3292171646
Short name T150
Test name
Test status
Simulation time 111817029 ps
CPU time 1.08 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292171646 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.3292171646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3527548598
Short name T106
Test name
Test status
Simulation time 172019975 ps
CPU time 0.72 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 209488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527548598 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3527548598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3087027792
Short name T988
Test name
Test status
Simulation time 440318558 ps
CPU time 2.8 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:28 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087027792 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3087027792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.768349757
Short name T94
Test name
Test status
Simulation time 29996849 ps
CPU time 0.62 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 208440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768349757 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.768349757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2675884893
Short name T125
Test name
Test status
Simulation time 59991479 ps
CPU time 0.78 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2675884893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_w
ith_rand_reset.2675884893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1745652775
Short name T101
Test name
Test status
Simulation time 24447738 ps
CPU time 0.54 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 208348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745652775 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1745652775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.458909405
Short name T159
Test name
Test status
Simulation time 145805474 ps
CPU time 0.52 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:45 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458909405 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.458909405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.908194043
Short name T84
Test name
Test status
Simulation time 45992181 ps
CPU time 0.61 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908194043 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.908194043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2937662168
Short name T1032
Test name
Test status
Simulation time 148281392 ps
CPU time 1.7 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937662168 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2937662168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.742327862
Short name T107
Test name
Test status
Simulation time 156398990 ps
CPU time 1.33 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:46 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742327862 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.742327862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4026569937
Short name T1012
Test name
Test status
Simulation time 36976932 ps
CPU time 0.73 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4026569937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_
with_rand_reset.4026569937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3799388601
Short name T86
Test name
Test status
Simulation time 42242594 ps
CPU time 0.53 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 206688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799388601 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3799388601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3661271410
Short name T1010
Test name
Test status
Simulation time 246054205 ps
CPU time 0.78 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661271410 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.3661271410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3808603990
Short name T1008
Test name
Test status
Simulation time 69112513 ps
CPU time 1.32 seconds
Started Aug 27 05:19:37 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808603990 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3808603990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.757253205
Short name T152
Test name
Test status
Simulation time 203260531 ps
CPU time 1.48 seconds
Started Aug 27 05:19:37 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757253205 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.757253205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.333595299
Short name T1018
Test name
Test status
Simulation time 61829978 ps
CPU time 0.74 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=333595299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_w
ith_rand_reset.333595299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.852298964
Short name T1011
Test name
Test status
Simulation time 19557337 ps
CPU time 0.63 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 208028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852298964 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.852298964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.2206444472
Short name T1006
Test name
Test status
Simulation time 21105671 ps
CPU time 0.66 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206444472 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2206444472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.191271644
Short name T1015
Test name
Test status
Simulation time 46764570 ps
CPU time 0.64 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 209092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191271644 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.191271644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1330228235
Short name T1019
Test name
Test status
Simulation time 56271248 ps
CPU time 1.12 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330228235 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1330228235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3651918592
Short name T1022
Test name
Test status
Simulation time 217494056 ps
CPU time 1.02 seconds
Started Aug 27 05:19:42 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651918592 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.3651918592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2373026713
Short name T1034
Test name
Test status
Simulation time 50209386 ps
CPU time 0.68 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2373026713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_
with_rand_reset.2373026713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3023013465
Short name T78
Test name
Test status
Simulation time 17208662 ps
CPU time 0.53 seconds
Started Aug 27 05:19:47 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 208508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023013465 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3023013465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.869006686
Short name T157
Test name
Test status
Simulation time 51680263 ps
CPU time 0.5 seconds
Started Aug 27 05:19:46 AM UTC 24
Finished Aug 27 05:19:58 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869006686 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.869006686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3384144799
Short name T1025
Test name
Test status
Simulation time 35106631 ps
CPU time 0.83 seconds
Started Aug 27 05:19:56 AM UTC 24
Finished Aug 27 05:19:58 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384144799 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.3384144799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2825227619
Short name T995
Test name
Test status
Simulation time 62747704 ps
CPU time 1.29 seconds
Started Aug 27 05:19:43 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825227619 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2825227619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1686550248
Short name T1035
Test name
Test status
Simulation time 91434046 ps
CPU time 0.71 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1686550248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_
with_rand_reset.1686550248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.243442227
Short name T80
Test name
Test status
Simulation time 41712462 ps
CPU time 0.6 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243442227 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.243442227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.384851670
Short name T1033
Test name
Test status
Simulation time 18121601 ps
CPU time 0.5 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384851670 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.384851670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3707022069
Short name T1036
Test name
Test status
Simulation time 108078452 ps
CPU time 0.78 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707022069 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.3707022069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1281267652
Short name T1047
Test name
Test status
Simulation time 274067993 ps
CPU time 2.22 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281267652 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1281267652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.72684752
Short name T1038
Test name
Test status
Simulation time 313838096 ps
CPU time 1.32 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72684752 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.72684752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1067447404
Short name T1042
Test name
Test status
Simulation time 43455394 ps
CPU time 0.67 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1067447404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_
with_rand_reset.1067447404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.2569901981
Short name T1037
Test name
Test status
Simulation time 56717261 ps
CPU time 0.59 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569901981 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.2569901981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2415416512
Short name T1041
Test name
Test status
Simulation time 27350476 ps
CPU time 0.66 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415416512 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.2415416512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1216632128
Short name T1040
Test name
Test status
Simulation time 110344697 ps
CPU time 1.28 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216632128 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1216632128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2648039468
Short name T1039
Test name
Test status
Simulation time 104900942 ps
CPU time 1.06 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648039468 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.2648039468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2675881322
Short name T1051
Test name
Test status
Simulation time 128894763 ps
CPU time 1.2 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2675881322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_
with_rand_reset.2675881322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1760617517
Short name T81
Test name
Test status
Simulation time 52931236 ps
CPU time 0.6 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 209572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760617517 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1760617517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1426225627
Short name T1043
Test name
Test status
Simulation time 47942510 ps
CPU time 0.58 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 206936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426225627 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1426225627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.707768383
Short name T1044
Test name
Test status
Simulation time 21824867 ps
CPU time 0.7 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:01 AM UTC 24
Peak memory 209032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707768383 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.707768383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1218439249
Short name T1055
Test name
Test status
Simulation time 136672944 ps
CPU time 2.24 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:03 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218439249 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1218439249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.566360644
Short name T114
Test name
Test status
Simulation time 286486910 ps
CPU time 1.37 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566360644 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.566360644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2909100896
Short name T1050
Test name
Test status
Simulation time 39080570 ps
CPU time 0.67 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2909100896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_
with_rand_reset.2909100896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.4181466818
Short name T83
Test name
Test status
Simulation time 48775437 ps
CPU time 0.57 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181466818 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.4181466818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.657862869
Short name T1046
Test name
Test status
Simulation time 53216673 ps
CPU time 0.53 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 205952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657862869 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.657862869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.756826768
Short name T1048
Test name
Test status
Simulation time 51672554 ps
CPU time 0.59 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 209412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756826768 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.756826768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2230090216
Short name T1052
Test name
Test status
Simulation time 130697037 ps
CPU time 1.44 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230090216 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.2230090216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3649776861
Short name T1053
Test name
Test status
Simulation time 270959628 ps
CPU time 1.42 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649776861 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.3649776861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3198265639
Short name T1060
Test name
Test status
Simulation time 70920189 ps
CPU time 0.78 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 209592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3198265639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_
with_rand_reset.3198265639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2203040294
Short name T1049
Test name
Test status
Simulation time 21848295 ps
CPU time 0.58 seconds
Started Aug 27 05:19:59 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203040294 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2203040294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.550277016
Short name T1045
Test name
Test status
Simulation time 42679624 ps
CPU time 0.52 seconds
Started Aug 27 05:19:59 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 206940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550277016 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.550277016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.702141589
Short name T1058
Test name
Test status
Simulation time 93892637 ps
CPU time 0.64 seconds
Started Aug 27 05:20:01 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 209088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702141589 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.702141589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.4171194088
Short name T1056
Test name
Test status
Simulation time 234236616 ps
CPU time 2.02 seconds
Started Aug 27 05:19:58 AM UTC 24
Finished Aug 27 05:20:03 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171194088 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.4171194088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1650338557
Short name T1054
Test name
Test status
Simulation time 1412734205 ps
CPU time 1.35 seconds
Started Aug 27 05:19:59 AM UTC 24
Finished Aug 27 05:20:02 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650338557 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.1650338557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3540944943
Short name T1066
Test name
Test status
Simulation time 40826584 ps
CPU time 0.68 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3540944943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_
with_rand_reset.3540944943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.4039161097
Short name T1059
Test name
Test status
Simulation time 37614100 ps
CPU time 0.61 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039161097 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.4039161097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3474550962
Short name T1057
Test name
Test status
Simulation time 27094183 ps
CPU time 0.5 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:03 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474550962 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3474550962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.753016459
Short name T1068
Test name
Test status
Simulation time 69287024 ps
CPU time 0.81 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 210316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753016459 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.753016459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1095799769
Short name T1095
Test name
Test status
Simulation time 201407755 ps
CPU time 2.25 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:05 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095799769 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1095799769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3787621013
Short name T1082
Test name
Test status
Simulation time 217270790 ps
CPU time 1.32 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787621013 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.3787621013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2029871058
Short name T1074
Test name
Test status
Simulation time 112200343 ps
CPU time 0.8 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2029871058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_
with_rand_reset.2029871058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.3790417759
Short name T1065
Test name
Test status
Simulation time 37537713 ps
CPU time 0.57 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790417759 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3790417759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.936767314
Short name T1061
Test name
Test status
Simulation time 19842205 ps
CPU time 0.54 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936767314 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.936767314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2734292343
Short name T1071
Test name
Test status
Simulation time 111558863 ps
CPU time 0.72 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734292343 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.2734292343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.3284709783
Short name T1085
Test name
Test status
Simulation time 78565464 ps
CPU time 1.38 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:05 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284709783 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3284709783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.422204863
Short name T1079
Test name
Test status
Simulation time 96435838 ps
CPU time 0.98 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422204863 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.422204863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1558403155
Short name T74
Test name
Test status
Simulation time 28007760 ps
CPU time 0.86 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558403155 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1558403155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1641936510
Short name T990
Test name
Test status
Simulation time 1221604093 ps
CPU time 3.11 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:28 AM UTC 24
Peak memory 210120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641936510 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1641936510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1294783779
Short name T105
Test name
Test status
Simulation time 24258967 ps
CPU time 0.57 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294783779 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1294783779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1229873837
Short name T52
Test name
Test status
Simulation time 56441638 ps
CPU time 0.85 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1229873837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_w
ith_rand_reset.1229873837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.1526066940
Short name T85
Test name
Test status
Simulation time 18767810 ps
CPU time 0.54 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526066940 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.1526066940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.1398136221
Short name T95
Test name
Test status
Simulation time 17778780 ps
CPU time 0.52 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398136221 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1398136221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2555390721
Short name T87
Test name
Test status
Simulation time 81364094 ps
CPU time 0.64 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 209460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555390721 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.2555390721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2210977063
Short name T49
Test name
Test status
Simulation time 101870896 ps
CPU time 1.04 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210977063 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.2210977063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2337946755
Short name T1062
Test name
Test status
Simulation time 130893006 ps
CPU time 0.54 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337946755 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2337946755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.1774966743
Short name T1063
Test name
Test status
Simulation time 20067182 ps
CPU time 0.57 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774966743 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.1774966743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.3028808698
Short name T1067
Test name
Test status
Simulation time 19995732 ps
CPU time 0.59 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028808698 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.3028808698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2598058255
Short name T1075
Test name
Test status
Simulation time 24776687 ps
CPU time 0.55 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598058255 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2598058255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2452606008
Short name T1070
Test name
Test status
Simulation time 40815043 ps
CPU time 0.53 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452606008 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2452606008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.1655176786
Short name T1072
Test name
Test status
Simulation time 46331971 ps
CPU time 0.52 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655176786 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1655176786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1314897401
Short name T1069
Test name
Test status
Simulation time 38185443 ps
CPU time 0.51 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314897401 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1314897401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3916794976
Short name T1077
Test name
Test status
Simulation time 37047748 ps
CPU time 0.56 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916794976 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3916794976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3516270024
Short name T1073
Test name
Test status
Simulation time 107495840 ps
CPU time 0.51 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516270024 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3516270024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2596227634
Short name T1076
Test name
Test status
Simulation time 48321849 ps
CPU time 0.56 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596227634 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.2596227634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1850040770
Short name T75
Test name
Test status
Simulation time 45112233 ps
CPU time 0.88 seconds
Started Aug 27 05:19:24 AM UTC 24
Finished Aug 27 05:19:27 AM UTC 24
Peak memory 209032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850040770 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1850040770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1451661985
Short name T989
Test name
Test status
Simulation time 980277512 ps
CPU time 2.84 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:28 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451661985 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1451661985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1427600210
Short name T73
Test name
Test status
Simulation time 68008316 ps
CPU time 0.58 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 208376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427600210 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.1427600210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4268991682
Short name T987
Test name
Test status
Simulation time 33850267 ps
CPU time 0.68 seconds
Started Aug 27 05:19:24 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4268991682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_w
ith_rand_reset.4268991682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1629613013
Short name T153
Test name
Test status
Simulation time 19315413 ps
CPU time 0.54 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 207024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629613013 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1629613013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3066611531
Short name T88
Test name
Test status
Simulation time 27306803 ps
CPU time 0.76 seconds
Started Aug 27 05:19:24 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066611531 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.3066611531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.2574493984
Short name T102
Test name
Test status
Simulation time 61928528 ps
CPU time 0.88 seconds
Started Aug 27 05:19:23 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 209568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574493984 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2574493984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.795628657
Short name T1080
Test name
Test status
Simulation time 21784549 ps
CPU time 0.59 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795628657 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.795628657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.991593558
Short name T1078
Test name
Test status
Simulation time 46578755 ps
CPU time 0.56 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991593558 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.991593558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.679651823
Short name T1084
Test name
Test status
Simulation time 15396170 ps
CPU time 0.57 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679651823 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.679651823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.567780200
Short name T1088
Test name
Test status
Simulation time 60216779 ps
CPU time 0.52 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567780200 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.567780200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1062622215
Short name T1083
Test name
Test status
Simulation time 48519443 ps
CPU time 0.52 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062622215 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1062622215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.4243535266
Short name T1089
Test name
Test status
Simulation time 59206350 ps
CPU time 0.54 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243535266 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.4243535266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.1309831309
Short name T1092
Test name
Test status
Simulation time 24709177 ps
CPU time 0.51 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309831309 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.1309831309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.1486586486
Short name T1091
Test name
Test status
Simulation time 62454644 ps
CPU time 0.57 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486586486 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1486586486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.975304615
Short name T1093
Test name
Test status
Simulation time 29863374 ps
CPU time 0.54 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975304615 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.975304615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.4059164227
Short name T1094
Test name
Test status
Simulation time 61532354 ps
CPU time 0.54 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059164227 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.4059164227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1087914987
Short name T1003
Test name
Test status
Simulation time 37368998 ps
CPU time 0.71 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 210956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087914987 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1087914987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3493293920
Short name T1027
Test name
Test status
Simulation time 835626144 ps
CPU time 2.91 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 211316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493293920 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.3493293920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3693321477
Short name T76
Test name
Test status
Simulation time 41124452 ps
CPU time 0.52 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:36 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693321477 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3693321477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3879898892
Short name T1013
Test name
Test status
Simulation time 98730920 ps
CPU time 1.08 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3879898892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w
ith_rand_reset.3879898892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.1169840019
Short name T997
Test name
Test status
Simulation time 46919467 ps
CPU time 0.53 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 206780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169840019 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1169840019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.4131821528
Short name T998
Test name
Test status
Simulation time 18039319 ps
CPU time 0.58 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 206184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131821528 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.4131821528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1465403264
Short name T1000
Test name
Test status
Simulation time 45514633 ps
CPU time 0.62 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 209332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465403264 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.1465403264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.482403777
Short name T111
Test name
Test status
Simulation time 64629616 ps
CPU time 1.23 seconds
Started Aug 27 05:19:24 AM UTC 24
Finished Aug 27 05:19:27 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482403777 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.482403777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3025485867
Short name T98
Test name
Test status
Simulation time 184265694 ps
CPU time 1.38 seconds
Started Aug 27 05:19:24 AM UTC 24
Finished Aug 27 05:19:27 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025485867 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.3025485867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3686984634
Short name T1090
Test name
Test status
Simulation time 18764861 ps
CPU time 0.57 seconds
Started Aug 27 05:20:02 AM UTC 24
Finished Aug 27 05:20:04 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686984634 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3686984634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.1119904807
Short name T1081
Test name
Test status
Simulation time 18413115 ps
CPU time 0.53 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119904807 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1119904807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3977350992
Short name T1087
Test name
Test status
Simulation time 43285607 ps
CPU time 0.53 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977350992 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3977350992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.1367544917
Short name T1086
Test name
Test status
Simulation time 41519828 ps
CPU time 0.53 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367544917 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1367544917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.4290240827
Short name T1096
Test name
Test status
Simulation time 32961911 ps
CPU time 0.53 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290240827 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.4290240827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.3825515974
Short name T1097
Test name
Test status
Simulation time 38338476 ps
CPU time 0.54 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825515974 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3825515974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.1354885257
Short name T1099
Test name
Test status
Simulation time 47930209 ps
CPU time 0.54 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354885257 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1354885257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3887444683
Short name T1064
Test name
Test status
Simulation time 33140868 ps
CPU time 0.54 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 206944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887444683 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.3887444683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.628242494
Short name T1100
Test name
Test status
Simulation time 29915655 ps
CPU time 0.59 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628242494 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.628242494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.3356995196
Short name T1098
Test name
Test status
Simulation time 16445904 ps
CPU time 0.56 seconds
Started Aug 27 05:20:47 AM UTC 24
Finished Aug 27 05:20:48 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356995196 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3356995196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2601855486
Short name T1021
Test name
Test status
Simulation time 39405262 ps
CPU time 0.93 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2601855486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_w
ith_rand_reset.2601855486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.2055692668
Short name T1002
Test name
Test status
Simulation time 36861810 ps
CPU time 0.6 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055692668 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.2055692668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.588587682
Short name T999
Test name
Test status
Simulation time 151896056 ps
CPU time 0.53 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588587682 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.588587682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1122389233
Short name T1005
Test name
Test status
Simulation time 73530267 ps
CPU time 0.66 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122389233 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.1122389233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3609649744
Short name T1020
Test name
Test status
Simulation time 252529685 ps
CPU time 1.34 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609649744 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3609649744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.292686357
Short name T1009
Test name
Test status
Simulation time 157305300 ps
CPU time 0.92 seconds
Started Aug 27 05:19:27 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292686357 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.292686357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3730614886
Short name T991
Test name
Test status
Simulation time 48205231 ps
CPU time 0.97 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3730614886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_w
ith_rand_reset.3730614886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.4063859057
Short name T89
Test name
Test status
Simulation time 30757681 ps
CPU time 0.58 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:30 AM UTC 24
Peak memory 208540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063859057 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.4063859057
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.2390017085
Short name T1007
Test name
Test status
Simulation time 19104376 ps
CPU time 0.57 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390017085 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2390017085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2109809815
Short name T90
Test name
Test status
Simulation time 44872801 ps
CPU time 0.66 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:30 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109809815 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.2109809815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.74600030
Short name T48
Test name
Test status
Simulation time 37015569 ps
CPU time 1.36 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74600030 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.74600030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2345022147
Short name T993
Test name
Test status
Simulation time 387697693 ps
CPU time 0.84 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2345022147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_w
ith_rand_reset.2345022147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.2954303279
Short name T77
Test name
Test status
Simulation time 18815210 ps
CPU time 0.56 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:40 AM UTC 24
Peak memory 209896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954303279 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2954303279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.3277160217
Short name T155
Test name
Test status
Simulation time 38364674 ps
CPU time 0.5 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:40 AM UTC 24
Peak memory 207024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277160217 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3277160217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3708518637
Short name T91
Test name
Test status
Simulation time 93893915 ps
CPU time 0.65 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708518637 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.3708518637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.3008981686
Short name T108
Test name
Test status
Simulation time 104321357 ps
CPU time 1.25 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008981686 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3008981686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.39789031
Short name T112
Test name
Test status
Simulation time 112299052 ps
CPU time 1.06 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39789031 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.39789031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.1449455324
Short name T1029
Test name
Test status
Simulation time 57032783 ps
CPU time 1.36 seconds
Started Aug 27 05:19:29 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1449455324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w
ith_rand_reset.1449455324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2308172279
Short name T1001
Test name
Test status
Simulation time 19062240 ps
CPU time 0.56 seconds
Started Aug 27 05:19:29 AM UTC 24
Finished Aug 27 05:19:58 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308172279 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2308172279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.552673500
Short name T156
Test name
Test status
Simulation time 17985466 ps
CPU time 0.55 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552673500 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.552673500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.685690543
Short name T1026
Test name
Test status
Simulation time 329063282 ps
CPU time 0.65 seconds
Started Aug 27 05:19:29 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 209624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685690543 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.685690543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.2377701837
Short name T109
Test name
Test status
Simulation time 105672444 ps
CPU time 1.28 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377701837 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2377701837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3611648481
Short name T104
Test name
Test status
Simulation time 246524512 ps
CPU time 1.32 seconds
Started Aug 27 05:19:28 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611648481 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.3611648481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2017892485
Short name T994
Test name
Test status
Simulation time 52336205 ps
CPU time 0.81 seconds
Started Aug 27 05:19:37 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2017892485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w
ith_rand_reset.2017892485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.1564196538
Short name T996
Test name
Test status
Simulation time 20499344 ps
CPU time 0.57 seconds
Started Aug 27 05:19:31 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 209728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564196538 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1564196538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.370283615
Short name T992
Test name
Test status
Simulation time 18237325 ps
CPU time 0.55 seconds
Started Aug 27 05:19:29 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370283615 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.370283615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1406360917
Short name T1004
Test name
Test status
Simulation time 23917402 ps
CPU time 0.72 seconds
Started Aug 27 05:19:31 AM UTC 24
Finished Aug 27 05:19:56 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406360917 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.1406360917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.609190081
Short name T1023
Test name
Test status
Simulation time 100677327 ps
CPU time 1.91 seconds
Started Aug 27 05:19:29 AM UTC 24
Finished Aug 27 05:20:00 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609190081 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.609190081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2679307221
Short name T149
Test name
Test status
Simulation time 108188398 ps
CPU time 0.99 seconds
Started Aug 27 05:19:29 AM UTC 24
Finished Aug 27 05:19:41 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679307221 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.2679307221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1093329101
Short name T15
Test name
Test status
Simulation time 73405360 ps
CPU time 0.83 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093329101 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.1093329101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1532742192
Short name T6
Test name
Test status
Simulation time 38337957 ps
CPU time 0.56 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532742192 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.1532742192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.714171537
Short name T32
Test name
Test status
Simulation time 49573586 ps
CPU time 0.58 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 206180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714171537 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.714171537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3797120728
Short name T8
Test name
Test status
Simulation time 32068692 ps
CPU time 0.54 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797120728 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3797120728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.3921669793
Short name T3
Test name
Test status
Simulation time 105889743 ps
CPU time 0.58 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921669793 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.3921669793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.1606507605
Short name T2
Test name
Test status
Simulation time 61117248 ps
CPU time 0.68 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606507605 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.1606507605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.533435123
Short name T21
Test name
Test status
Simulation time 636147298 ps
CPU time 2.13 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:52 AM UTC 24
Peak memory 239164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533435123 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.533435123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.753171214
Short name T10
Test name
Test status
Simulation time 79030987 ps
CPU time 0.6 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753171214 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.753171214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1021540809
Short name T14
Test name
Test status
Simulation time 70001170 ps
CPU time 0.8 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021540809 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1021540809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1021527971
Short name T1
Test name
Test status
Simulation time 28987164 ps
CPU time 0.61 seconds
Started Aug 27 05:15:35 AM UTC 24
Finished Aug 27 05:15:37 AM UTC 24
Peak memory 210424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021527971 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1021527971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3407349915
Short name T24
Test name
Test status
Simulation time 1169430239 ps
CPU time 4.57 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3407349915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr
_stress_all_with_rand_reset.3407349915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.742344102
Short name T34
Test name
Test status
Simulation time 224392191 ps
CPU time 1.06 seconds
Started Aug 27 05:15:48 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742344102 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.742344102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.4140351115
Short name T16
Test name
Test status
Simulation time 34692999 ps
CPU time 0.86 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140351115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4140351115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.109713841
Short name T27
Test name
Test status
Simulation time 67309456 ps
CPU time 0.7 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109713841 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.109713841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4168703813
Short name T12
Test name
Test status
Simulation time 60229225 ps
CPU time 0.62 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168703813 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.4168703813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3366342504
Short name T40
Test name
Test status
Simulation time 594363245 ps
CPU time 0.72 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366342504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3366342504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.1251424930
Short name T41
Test name
Test status
Simulation time 96926638 ps
CPU time 0.57 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251424930 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1251424930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3324440728
Short name T44
Test name
Test status
Simulation time 104897347 ps
CPU time 0.77 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324440728 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.3324440728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3402747113
Short name T118
Test name
Test status
Simulation time 215283728 ps
CPU time 1.2 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402747113 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.3402747113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.550074728
Short name T37
Test name
Test status
Simulation time 80152983 ps
CPU time 0.97 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550074728 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.550074728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.2111909170
Short name T38
Test name
Test status
Simulation time 166796727 ps
CPU time 0.89 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111909170 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2111909170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.4252265997
Short name T22
Test name
Test status
Simulation time 307391151 ps
CPU time 1.37 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 236876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252265997 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.4252265997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.671721596
Short name T116
Test name
Test status
Simulation time 950331463 ps
CPU time 2.33 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:52 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671721596 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.671721596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2052267230
Short name T164
Test name
Test status
Simulation time 829585579 ps
CPU time 2.94 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 210968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052267230 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2052267230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2671155559
Short name T161
Test name
Test status
Simulation time 64749659 ps
CPU time 0.88 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671155559 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2671155559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1085156807
Short name T35
Test name
Test status
Simulation time 36240416 ps
CPU time 0.6 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085156807 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1085156807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.726444393
Short name T42
Test name
Test status
Simulation time 6612839741 ps
CPU time 3.9 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:56 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726444393 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.726444393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.422546060
Short name T36
Test name
Test status
Simulation time 178539163 ps
CPU time 0.71 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422546060 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.422546060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.3845418163
Short name T39
Test name
Test status
Simulation time 198622117 ps
CPU time 1.1 seconds
Started Aug 27 05:15:49 AM UTC 24
Finished Aug 27 05:15:51 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845418163 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.3845418163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.4248814543
Short name T279
Test name
Test status
Simulation time 112712838 ps
CPU time 0.93 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248814543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.4248814543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.2702734908
Short name T274
Test name
Test status
Simulation time 55010824 ps
CPU time 0.8 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702734908 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.2702734908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.883649826
Short name T266
Test name
Test status
Simulation time 28227206 ps
CPU time 0.6 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883649826 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.883649826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.3230438147
Short name T284
Test name
Test status
Simulation time 115858020 ps
CPU time 0.94 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230438147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3230438147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3655703371
Short name T267
Test name
Test status
Simulation time 62235325 ps
CPU time 0.57 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655703371 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3655703371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.394706738
Short name T272
Test name
Test status
Simulation time 43872973 ps
CPU time 0.7 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394706738 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.394706738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.1176957481
Short name T282
Test name
Test status
Simulation time 43518310 ps
CPU time 0.76 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176957481 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.1176957481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.935843822
Short name T271
Test name
Test status
Simulation time 73391322 ps
CPU time 0.92 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935843822 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.935843822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.1543370533
Short name T265
Test name
Test status
Simulation time 25776542 ps
CPU time 0.69 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543370533 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.1543370533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3506988054
Short name T278
Test name
Test status
Simulation time 156442622 ps
CPU time 0.71 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506988054 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3506988054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2784613209
Short name T276
Test name
Test status
Simulation time 287811769 ps
CPU time 0.86 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784613209 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.2784613209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1230827958
Short name T297
Test name
Test status
Simulation time 908516433 ps
CPU time 2 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230827958 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1230827958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3544000480
Short name T299
Test name
Test status
Simulation time 922374781 ps
CPU time 2.46 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:14 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544000480 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3544000480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1254078121
Short name T275
Test name
Test status
Simulation time 70304456 ps
CPU time 0.92 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254078121 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1254078121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.804505000
Short name T264
Test name
Test status
Simulation time 29583763 ps
CPU time 0.57 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804505000 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.804505000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.1088589354
Short name T295
Test name
Test status
Simulation time 641650467 ps
CPU time 1.58 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088589354 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.1088589354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2785323809
Short name T277
Test name
Test status
Simulation time 197388665 ps
CPU time 1.05 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785323809 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.2785323809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3529023505
Short name T268
Test name
Test status
Simulation time 600375904 ps
CPU time 0.95 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529023505 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3529023505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1369608491
Short name T291
Test name
Test status
Simulation time 30009728 ps
CPU time 1.04 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369608491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1369608491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.59906524
Short name T283
Test name
Test status
Simulation time 28060494 ps
CPU time 0.62 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 206160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59906524 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.59906524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.1604559034
Short name T290
Test name
Test status
Simulation time 395510356 ps
CPU time 0.74 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604559034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1604559034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.3824684313
Short name T285
Test name
Test status
Simulation time 58305009 ps
CPU time 0.53 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824684313 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.3824684313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.3126633665
Short name T288
Test name
Test status
Simulation time 33814670 ps
CPU time 0.68 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126633665 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.3126633665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.3278052686
Short name T269
Test name
Test status
Simulation time 53487664 ps
CPU time 0.73 seconds
Started Aug 27 05:16:12 AM UTC 24
Finished Aug 27 05:16:14 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278052686 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.3278052686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.3620970020
Short name T289
Test name
Test status
Simulation time 565586559 ps
CPU time 0.9 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620970020 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.3620970020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1555399779
Short name T292
Test name
Test status
Simulation time 76374893 ps
CPU time 1.05 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555399779 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1555399779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.1089230829
Short name T298
Test name
Test status
Simulation time 290861778 ps
CPU time 0.74 seconds
Started Aug 27 05:16:12 AM UTC 24
Finished Aug 27 05:16:14 AM UTC 24
Peak memory 219840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089230829 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1089230829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.1306440426
Short name T294
Test name
Test status
Simulation time 110665799 ps
CPU time 1.03 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306440426 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.1306440426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3208757597
Short name T300
Test name
Test status
Simulation time 938919369 ps
CPU time 2.31 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:14 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208757597 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3208757597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1976760991
Short name T301
Test name
Test status
Simulation time 849785343 ps
CPU time 2.99 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:15 AM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976760991 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1976760991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.368393190
Short name T293
Test name
Test status
Simulation time 109755737 ps
CPU time 0.87 seconds
Started Aug 27 05:16:11 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368393190 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.368393190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2210288308
Short name T280
Test name
Test status
Simulation time 35514892 ps
CPU time 0.64 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210288308 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2210288308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.1930537900
Short name T245
Test name
Test status
Simulation time 985935415 ps
CPU time 2.85 seconds
Started Aug 27 05:16:12 AM UTC 24
Finished Aug 27 05:16:16 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930537900 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1930537900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.1590493367
Short name T55
Test name
Test status
Simulation time 3972378303 ps
CPU time 7.75 seconds
Started Aug 27 05:16:12 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1590493367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg
r_stress_all_with_rand_reset.1590493367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.560627269
Short name T286
Test name
Test status
Simulation time 338625968 ps
CPU time 0.82 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560627269 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.560627269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.477159237
Short name T281
Test name
Test status
Simulation time 126287187 ps
CPU time 0.7 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477159237 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.477159237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.4243601944
Short name T310
Test name
Test status
Simulation time 77019176 ps
CPU time 0.76 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243601944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.4243601944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1790305758
Short name T315
Test name
Test status
Simulation time 56111447 ps
CPU time 0.66 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 210424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790305758 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.1790305758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3892054806
Short name T303
Test name
Test status
Simulation time 39059384 ps
CPU time 0.53 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892054806 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.3892054806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.1417200049
Short name T313
Test name
Test status
Simulation time 378993942 ps
CPU time 0.78 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417200049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1417200049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.2598975426
Short name T306
Test name
Test status
Simulation time 59883003 ps
CPU time 0.54 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598975426 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.2598975426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1423636038
Short name T311
Test name
Test status
Simulation time 24981001 ps
CPU time 0.58 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423636038 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1423636038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.454846322
Short name T314
Test name
Test status
Simulation time 51257656 ps
CPU time 0.66 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454846322 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.454846322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.32923913
Short name T308
Test name
Test status
Simulation time 340174764 ps
CPU time 0.97 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32923913 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.32923913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1517301288
Short name T273
Test name
Test status
Simulation time 482854914 ps
CPU time 0.85 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517301288 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1517301288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.1061824684
Short name T316
Test name
Test status
Simulation time 254134205 ps
CPU time 0.69 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061824684 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.1061824684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.3328291205
Short name T302
Test name
Test status
Simulation time 75724748 ps
CPU time 0.59 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328291205 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.3328291205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3521837532
Short name T337
Test name
Test status
Simulation time 1130871222 ps
CPU time 2.07 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521837532 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3521837532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2915692446
Short name T338
Test name
Test status
Simulation time 1313682462 ps
CPU time 2.12 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915692446 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2915692446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1704734346
Short name T312
Test name
Test status
Simulation time 77084872 ps
CPU time 0.8 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704734346 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1704734346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.343282830
Short name T270
Test name
Test status
Simulation time 52691559 ps
CPU time 0.59 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343282830 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.343282830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.1387570145
Short name T327
Test name
Test status
Simulation time 295747318 ps
CPU time 1.09 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387570145 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.1387570145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1003401839
Short name T121
Test name
Test status
Simulation time 3788543722 ps
CPU time 11.47 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:29 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1003401839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmg
r_stress_all_with_rand_reset.1003401839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.4262893508
Short name T305
Test name
Test status
Simulation time 66194287 ps
CPU time 0.74 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262893508 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.4262893508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.3141231585
Short name T309
Test name
Test status
Simulation time 126182112 ps
CPU time 0.83 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141231585 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3141231585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.2722829950
Short name T324
Test name
Test status
Simulation time 40559928 ps
CPU time 0.83 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722829950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2722829950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.582255054
Short name T330
Test name
Test status
Simulation time 59827180 ps
CPU time 0.79 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582255054 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.582255054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2978006719
Short name T321
Test name
Test status
Simulation time 32537685 ps
CPU time 0.61 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 206108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978006719 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.2978006719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.941376837
Short name T334
Test name
Test status
Simulation time 115788229 ps
CPU time 0.93 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941376837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.941376837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.1500719959
Short name T325
Test name
Test status
Simulation time 33713006 ps
CPU time 0.56 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 206192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500719959 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.1500719959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.1089736844
Short name T323
Test name
Test status
Simulation time 22075076 ps
CPU time 0.58 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 206204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089736844 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1089736844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.837687221
Short name T331
Test name
Test status
Simulation time 53623795 ps
CPU time 0.73 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 210976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837687221 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.837687221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.376168639
Short name T320
Test name
Test status
Simulation time 291178544 ps
CPU time 0.78 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376168639 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.376168639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.1854533664
Short name T322
Test name
Test status
Simulation time 65970035 ps
CPU time 0.81 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854533664 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.1854533664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.3023753832
Short name T336
Test name
Test status
Simulation time 97179477 ps
CPU time 0.92 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023753832 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3023753832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3058477086
Short name T328
Test name
Test status
Simulation time 114856066 ps
CPU time 0.82 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058477086 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.3058477086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.340243571
Short name T339
Test name
Test status
Simulation time 1001329254 ps
CPU time 1.87 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340243571 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.340243571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3820323393
Short name T349
Test name
Test status
Simulation time 867606261 ps
CPU time 3.33 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820323393 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3820323393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3997406408
Short name T326
Test name
Test status
Simulation time 86065478 ps
CPU time 0.84 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997406408 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3997406408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.3504886801
Short name T317
Test name
Test status
Simulation time 31835069 ps
CPU time 0.67 seconds
Started Aug 27 05:16:16 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504886801 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.3504886801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.2572908866
Short name T340
Test name
Test status
Simulation time 708289669 ps
CPU time 1.77 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 210812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572908866 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2572908866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.1703015092
Short name T120
Test name
Test status
Simulation time 12486965407 ps
CPU time 9.99 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:28 AM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1703015092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg
r_stress_all_with_rand_reset.1703015092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.1568876668
Short name T318
Test name
Test status
Simulation time 44619763 ps
CPU time 0.65 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:18 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568876668 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.1568876668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.508765185
Short name T333
Test name
Test status
Simulation time 271068870 ps
CPU time 1.12 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508765185 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.508765185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.3565513935
Short name T341
Test name
Test status
Simulation time 31060770 ps
CPU time 0.63 seconds
Started Aug 27 05:16:18 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565513935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3565513935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.608452437
Short name T147
Test name
Test status
Simulation time 98422903 ps
CPU time 0.61 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608452437 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.608452437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.137423581
Short name T342
Test name
Test status
Simulation time 28686823 ps
CPU time 0.63 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137423581 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.137423581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.2519091092
Short name T348
Test name
Test status
Simulation time 403703450 ps
CPU time 0.82 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519091092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2519091092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.2062875397
Short name T353
Test name
Test status
Simulation time 77891883 ps
CPU time 0.52 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062875397 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2062875397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.848897939
Short name T345
Test name
Test status
Simulation time 78571261 ps
CPU time 0.54 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848897939 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.848897939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.671646445
Short name T354
Test name
Test status
Simulation time 64638846 ps
CPU time 0.62 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671646445 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.671646445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.1896408541
Short name T343
Test name
Test status
Simulation time 467587139 ps
CPU time 0.72 seconds
Started Aug 27 05:16:18 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896408541 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.1896408541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.174334936
Short name T329
Test name
Test status
Simulation time 125696083 ps
CPU time 0.76 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174334936 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.174334936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.3119517489
Short name T355
Test name
Test status
Simulation time 153817370 ps
CPU time 0.67 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119517489 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3119517489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.916892844
Short name T350
Test name
Test status
Simulation time 405173740 ps
CPU time 1.09 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916892844 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.916892844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4245796568
Short name T351
Test name
Test status
Simulation time 1335576205 ps
CPU time 1.96 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245796568 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4245796568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1873019978
Short name T352
Test name
Test status
Simulation time 1437836097 ps
CPU time 1.97 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873019978 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1873019978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3970748503
Short name T347
Test name
Test status
Simulation time 51611982 ps
CPU time 0.81 seconds
Started Aug 27 05:16:19 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970748503 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3970748503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.2956929698
Short name T332
Test name
Test status
Simulation time 31563538 ps
CPU time 0.72 seconds
Started Aug 27 05:16:17 AM UTC 24
Finished Aug 27 05:16:19 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956929698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2956929698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.158842962
Short name T373
Test name
Test status
Simulation time 1914727955 ps
CPU time 4.4 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:26 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158842962 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.158842962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.2162008388
Short name T123
Test name
Test status
Simulation time 4273032926 ps
CPU time 13.91 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:36 AM UTC 24
Peak memory 220980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2162008388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmg
r_stress_all_with_rand_reset.2162008388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2362406147
Short name T346
Test name
Test status
Simulation time 266064363 ps
CPU time 0.99 seconds
Started Aug 27 05:16:18 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362406147 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2362406147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.11221717
Short name T344
Test name
Test status
Simulation time 117892083 ps
CPU time 0.78 seconds
Started Aug 27 05:16:18 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11221717 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.11221717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.1348571939
Short name T360
Test name
Test status
Simulation time 68469809 ps
CPU time 0.73 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348571939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1348571939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.203361053
Short name T364
Test name
Test status
Simulation time 129272985 ps
CPU time 0.61 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203361053 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.203361053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.4106777783
Short name T358
Test name
Test status
Simulation time 32268231 ps
CPU time 0.59 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106777783 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.4106777783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.3249436315
Short name T367
Test name
Test status
Simulation time 929880094 ps
CPU time 0.75 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249436315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3249436315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.3147442337
Short name T363
Test name
Test status
Simulation time 89600100 ps
CPU time 0.55 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147442337 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3147442337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.366095703
Short name T359
Test name
Test status
Simulation time 54744487 ps
CPU time 0.51 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366095703 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.366095703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.2782786007
Short name T304
Test name
Test status
Simulation time 37463170 ps
CPU time 0.71 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782786007 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.2782786007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.2293024408
Short name T362
Test name
Test status
Simulation time 258024543 ps
CPU time 0.89 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293024408 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.2293024408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.912380529
Short name T361
Test name
Test status
Simulation time 77305005 ps
CPU time 0.84 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912380529 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.912380529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.2793034823
Short name T369
Test name
Test status
Simulation time 150812347 ps
CPU time 0.7 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793034823 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2793034823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.225388191
Short name T365
Test name
Test status
Simulation time 238298474 ps
CPU time 0.83 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225388191 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.225388191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1488911652
Short name T371
Test name
Test status
Simulation time 745234928 ps
CPU time 2.74 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:25 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488911652 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1488911652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.433837829
Short name T372
Test name
Test status
Simulation time 867393843 ps
CPU time 2.93 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:25 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433837829 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.433837829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3278100605
Short name T368
Test name
Test status
Simulation time 76119712 ps
CPU time 0.91 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278100605 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3278100605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.3846859969
Short name T357
Test name
Test status
Simulation time 40377696 ps
CPU time 0.59 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:22 AM UTC 24
Peak memory 210892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846859969 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3846859969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.1863524862
Short name T374
Test name
Test status
Simulation time 1712162918 ps
CPU time 5.37 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:28 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863524862 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.1863524862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1170198987
Short name T122
Test name
Test status
Simulation time 2955695739 ps
CPU time 9.79 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:32 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1170198987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg
r_stress_all_with_rand_reset.1170198987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1823107000
Short name T319
Test name
Test status
Simulation time 234625666 ps
CPU time 1.14 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823107000 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1823107000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1488334721
Short name T366
Test name
Test status
Simulation time 265721181 ps
CPU time 0.96 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488334721 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.1488334721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.3323048240
Short name T417
Test name
Test status
Simulation time 32545397 ps
CPU time 0.62 seconds
Started Aug 27 05:16:24 AM UTC 24
Finished Aug 27 05:16:57 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323048240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.3323048240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.3779033145
Short name T375
Test name
Test status
Simulation time 52969720 ps
CPU time 0.73 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:30 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779033145 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.3779033145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.3670099220
Short name T416
Test name
Test status
Simulation time 42044320 ps
CPU time 0.63 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 210980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670099220 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.3670099220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.3783441269
Short name T356
Test name
Test status
Simulation time 96238345 ps
CPU time 0.74 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783441269 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.3783441269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.2872919079
Short name T307
Test name
Test status
Simulation time 103894685 ps
CPU time 0.97 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:24 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872919079 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2872919079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.807950473
Short name T418
Test name
Test status
Simulation time 99324642 ps
CPU time 0.82 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:57 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807950473 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.807950473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.946940256
Short name T335
Test name
Test status
Simulation time 54727097 ps
CPU time 0.57 seconds
Started Aug 27 05:16:21 AM UTC 24
Finished Aug 27 05:16:23 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946940256 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.946940256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.3640115521
Short name T443
Test name
Test status
Simulation time 5216634009 ps
CPU time 6.36 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:02 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3640115521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmg
r_stress_all_with_rand_reset.3640115521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2116601691
Short name T419
Test name
Test status
Simulation time 189518976 ps
CPU time 0.67 seconds
Started Aug 27 05:16:24 AM UTC 24
Finished Aug 27 05:16:57 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116601691 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2116601691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.3596875965
Short name T420
Test name
Test status
Simulation time 293207856 ps
CPU time 0.79 seconds
Started Aug 27 05:16:24 AM UTC 24
Finished Aug 27 05:16:57 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596875965 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3596875965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.3896219675
Short name T397
Test name
Test status
Simulation time 122968318 ps
CPU time 0.79 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896219675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3896219675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.587452146
Short name T426
Test name
Test status
Simulation time 62870350 ps
CPU time 0.77 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587452146 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.587452146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3225852990
Short name T394
Test name
Test status
Simulation time 29730658 ps
CPU time 0.57 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225852990 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.3225852990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.3651294879
Short name T425
Test name
Test status
Simulation time 114874192 ps
CPU time 0.8 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651294879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3651294879
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.1781006110
Short name T423
Test name
Test status
Simulation time 51374203 ps
CPU time 0.51 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781006110 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1781006110
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.1042695507
Short name T395
Test name
Test status
Simulation time 70754660 ps
CPU time 0.55 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042695507 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1042695507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.2850003233
Short name T424
Test name
Test status
Simulation time 158741123 ps
CPU time 0.61 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850003233 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.2850003233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.2671544834
Short name T422
Test name
Test status
Simulation time 71056494 ps
CPU time 0.6 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671544834 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.2671544834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.3661210706
Short name T479
Test name
Test status
Simulation time 121103110 ps
CPU time 0.87 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661210706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3661210706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.981824132
Short name T429
Test name
Test status
Simulation time 147196408 ps
CPU time 0.71 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 219672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981824132 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.981824132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.1020724871
Short name T396
Test name
Test status
Simulation time 167827200 ps
CPU time 0.66 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020724871 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.1020724871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2354644352
Short name T452
Test name
Test status
Simulation time 842604731 ps
CPU time 2.65 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:12 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354644352 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2354644352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1596705239
Short name T403
Test name
Test status
Simulation time 1294001597 ps
CPU time 2.03 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:51 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596705239 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1596705239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1119835698
Short name T393
Test name
Test status
Simulation time 55330344 ps
CPU time 0.79 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119835698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1119835698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.2422256385
Short name T471
Test name
Test status
Simulation time 40775895 ps
CPU time 0.58 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422256385 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2422256385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.1443148444
Short name T444
Test name
Test status
Simulation time 2576007043 ps
CPU time 3.47 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:03 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443148444 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.1443148444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3393441048
Short name T427
Test name
Test status
Simulation time 265658164 ps
CPU time 0.84 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393441048 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.3393441048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.681516090
Short name T432
Test name
Test status
Simulation time 305178385 ps
CPU time 1.3 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681516090 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.681516090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.832821211
Short name T389
Test name
Test status
Simulation time 33547636 ps
CPU time 0.89 seconds
Started Aug 27 05:16:27 AM UTC 24
Finished Aug 27 05:16:47 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832821211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.832821211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.1823306756
Short name T388
Test name
Test status
Simulation time 192252160 ps
CPU time 0.56 seconds
Started Aug 27 05:16:34 AM UTC 24
Finished Aug 27 05:16:46 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823306756 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.1823306756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1944514094
Short name T377
Test name
Test status
Simulation time 38139309 ps
CPU time 0.48 seconds
Started Aug 27 05:16:30 AM UTC 24
Finished Aug 27 05:16:35 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944514094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.1944514094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2255456335
Short name T385
Test name
Test status
Simulation time 111047127 ps
CPU time 0.78 seconds
Started Aug 27 05:16:30 AM UTC 24
Finished Aug 27 05:16:46 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255456335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2255456335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.802042811
Short name T381
Test name
Test status
Simulation time 105342068 ps
CPU time 0.5 seconds
Started Aug 27 05:16:32 AM UTC 24
Finished Aug 27 05:16:41 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802042811 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.802042811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.4284286301
Short name T382
Test name
Test status
Simulation time 30159159 ps
CPU time 0.52 seconds
Started Aug 27 05:16:30 AM UTC 24
Finished Aug 27 05:16:42 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284286301 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.4284286301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.2096335191
Short name T379
Test name
Test status
Simulation time 38937133 ps
CPU time 0.6 seconds
Started Aug 27 05:16:36 AM UTC 24
Finished Aug 27 05:16:41 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096335191 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.2096335191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.4014540780
Short name T514
Test name
Test status
Simulation time 198488403 ps
CPU time 0.98 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014540780 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.4014540780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.1927716774
Short name T430
Test name
Test status
Simulation time 107635351 ps
CPU time 0.68 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927716774 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1927716774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.1831097878
Short name T380
Test name
Test status
Simulation time 130365321 ps
CPU time 0.68 seconds
Started Aug 27 05:16:36 AM UTC 24
Finished Aug 27 05:16:41 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831097878 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1831097878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.713844204
Short name T384
Test name
Test status
Simulation time 40690251 ps
CPU time 0.55 seconds
Started Aug 27 05:16:30 AM UTC 24
Finished Aug 27 05:16:45 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713844204 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.713844204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1210105065
Short name T390
Test name
Test status
Simulation time 1110441863 ps
CPU time 1.82 seconds
Started Aug 27 05:16:27 AM UTC 24
Finished Aug 27 05:16:48 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210105065 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1210105065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.678152790
Short name T391
Test name
Test status
Simulation time 1123563229 ps
CPU time 1.86 seconds
Started Aug 27 05:16:27 AM UTC 24
Finished Aug 27 05:16:48 AM UTC 24
Peak memory 210352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678152790 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.678152790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.409637212
Short name T376
Test name
Test status
Simulation time 73480127 ps
CPU time 0.82 seconds
Started Aug 27 05:16:28 AM UTC 24
Finished Aug 27 05:16:32 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409637212 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.409637212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.1275154519
Short name T428
Test name
Test status
Simulation time 39637844 ps
CPU time 0.54 seconds
Started Aug 27 05:16:25 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275154519 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.1275154519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.4127874027
Short name T383
Test name
Test status
Simulation time 1994683543 ps
CPU time 4.01 seconds
Started Aug 27 05:16:37 AM UTC 24
Finished Aug 27 05:16:45 AM UTC 24
Peak memory 211588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127874027 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.4127874027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.31715205
Short name T392
Test name
Test status
Simulation time 3009180101 ps
CPU time 6.6 seconds
Started Aug 27 05:16:37 AM UTC 24
Finished Aug 27 05:16:48 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=31715205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_
stress_all_with_rand_reset.31715205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.2213349346
Short name T370
Test name
Test status
Simulation time 381958039 ps
CPU time 0.72 seconds
Started Aug 27 05:16:27 AM UTC 24
Finished Aug 27 05:16:35 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213349346 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.2213349346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.1421229321
Short name T378
Test name
Test status
Simulation time 208361193 ps
CPU time 1.03 seconds
Started Aug 27 05:16:27 AM UTC 24
Finished Aug 27 05:16:36 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421229321 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.1421229321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.1097269783
Short name T404
Test name
Test status
Simulation time 49406163 ps
CPU time 0.68 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097269783 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.1097269783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1659062756
Short name T413
Test name
Test status
Simulation time 32038337 ps
CPU time 0.51 seconds
Started Aug 27 05:16:47 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 205984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659062756 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.1659062756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.2589443732
Short name T402
Test name
Test status
Simulation time 134130274 ps
CPU time 0.76 seconds
Started Aug 27 05:16:49 AM UTC 24
Finished Aug 27 05:16:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589443732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2589443732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.415675465
Short name T401
Test name
Test status
Simulation time 33090642 ps
CPU time 0.53 seconds
Started Aug 27 05:16:49 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415675465 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.415675465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.2206145031
Short name T399
Test name
Test status
Simulation time 36487615 ps
CPU time 0.54 seconds
Started Aug 27 05:16:49 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206145031 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2206145031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.3736512793
Short name T405
Test name
Test status
Simulation time 68951405 ps
CPU time 0.58 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736512793 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.3736512793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.3686482401
Short name T400
Test name
Test status
Simulation time 247560718 ps
CPU time 1.07 seconds
Started Aug 27 05:16:42 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686482401 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.3686482401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.3773322446
Short name T398
Test name
Test status
Simulation time 97606891 ps
CPU time 0.84 seconds
Started Aug 27 05:16:42 AM UTC 24
Finished Aug 27 05:16:50 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773322446 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.3773322446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.2518670921
Short name T406
Test name
Test status
Simulation time 169642258 ps
CPU time 0.69 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518670921 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2518670921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1269096559
Short name T414
Test name
Test status
Simulation time 203442031 ps
CPU time 0.64 seconds
Started Aug 27 05:16:48 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269096559 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.1269096559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3150647396
Short name T415
Test name
Test status
Simulation time 87846891 ps
CPU time 0.7 seconds
Started Aug 27 05:16:47 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150647396 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3150647396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.2121619290
Short name T386
Test name
Test status
Simulation time 29167493 ps
CPU time 0.59 seconds
Started Aug 27 05:16:41 AM UTC 24
Finished Aug 27 05:16:46 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121619290 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.2121619290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.3109381218
Short name T421
Test name
Test status
Simulation time 2271579811 ps
CPU time 4.23 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:59 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109381218 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3109381218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.3248562480
Short name T441
Test name
Test status
Simulation time 12523336093 ps
CPU time 7.06 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:17:02 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3248562480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmg
r_stress_all_with_rand_reset.3248562480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.1746294273
Short name T387
Test name
Test status
Simulation time 125474810 ps
CPU time 0.61 seconds
Started Aug 27 05:16:43 AM UTC 24
Finished Aug 27 05:16:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746294273 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1746294273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.4162224656
Short name T68
Test name
Test status
Simulation time 26459998 ps
CPU time 0.86 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162224656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.4162224656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3967917633
Short name T133
Test name
Test status
Simulation time 81559433 ps
CPU time 0.54 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967917633 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.3967917633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.4047381092
Short name T126
Test name
Test status
Simulation time 115179613 ps
CPU time 0.96 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047381092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.4047381092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.750053725
Short name T167
Test name
Test status
Simulation time 67308042 ps
CPU time 0.65 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750053725 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.750053725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.2305248902
Short name T165
Test name
Test status
Simulation time 37662404 ps
CPU time 0.58 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305248902 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2305248902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2437543208
Short name T45
Test name
Test status
Simulation time 100054110 ps
CPU time 0.72 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437543208 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.2437543208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1702795505
Short name T163
Test name
Test status
Simulation time 270524348 ps
CPU time 0.88 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 207924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702795505 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.1702795505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.3894977653
Short name T166
Test name
Test status
Simulation time 98602923 ps
CPU time 0.97 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894977653 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3894977653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1778494024
Short name T171
Test name
Test status
Simulation time 106313556 ps
CPU time 1.1 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778494024 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1778494024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2538354311
Short name T100
Test name
Test status
Simulation time 230455156 ps
CPU time 1.12 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538354311 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.2538354311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1702728739
Short name T46
Test name
Test status
Simulation time 1193106954 ps
CPU time 1.93 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702728739 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1702728739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1039470752
Short name T60
Test name
Test status
Simulation time 1348973929 ps
CPU time 2.09 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039470752 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1039470752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387906928
Short name T168
Test name
Test status
Simulation time 231142648 ps
CPU time 0.91 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387906928 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387906928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1952748148
Short name T162
Test name
Test status
Simulation time 42675480 ps
CPU time 0.59 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952748148 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.1952748148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.4286296788
Short name T69
Test name
Test status
Simulation time 826165399 ps
CPU time 3.01 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286296788 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.4286296788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.187120359
Short name T51
Test name
Test status
Simulation time 4755845142 ps
CPU time 19.88 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:16:14 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=187120359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_
stress_all_with_rand_reset.187120359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1319683830
Short name T170
Test name
Test status
Simulation time 219876359 ps
CPU time 1.17 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319683830 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1319683830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.46109846
Short name T169
Test name
Test status
Simulation time 340917595 ps
CPU time 1.12 seconds
Started Aug 27 05:15:51 AM UTC 24
Finished Aug 27 05:15:53 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46109846 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.46109846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.4085334132
Short name T412
Test name
Test status
Simulation time 49426306 ps
CPU time 0.68 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085334132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.4085334132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.4222806905
Short name T469
Test name
Test status
Simulation time 66604107 ps
CPU time 0.68 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222806905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.4222806905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1360987644
Short name T463
Test name
Test status
Simulation time 390218573 ps
CPU time 0.79 seconds
Started Aug 27 05:16:57 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360987644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1360987644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.3972608088
Short name T457
Test name
Test status
Simulation time 68899393 ps
CPU time 0.53 seconds
Started Aug 27 05:16:57 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972608088 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.3972608088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.2660702452
Short name T455
Test name
Test status
Simulation time 45955795 ps
CPU time 0.52 seconds
Started Aug 27 05:16:57 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660702452 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2660702452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.2239666494
Short name T467
Test name
Test status
Simulation time 43188795 ps
CPU time 0.63 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239666494 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.2239666494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.816442238
Short name T408
Test name
Test status
Simulation time 116107171 ps
CPU time 0.61 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816442238 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.816442238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.486919693
Short name T410
Test name
Test status
Simulation time 54041104 ps
CPU time 0.74 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486919693 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.486919693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.2308441504
Short name T476
Test name
Test status
Simulation time 100338002 ps
CPU time 0.88 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308441504 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.2308441504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1860027381
Short name T439
Test name
Test status
Simulation time 783804743 ps
CPU time 2.12 seconds
Started Aug 27 05:16:52 AM UTC 24
Finished Aug 27 05:17:02 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860027381 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1860027381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2124596162
Short name T541
Test name
Test status
Simulation time 923566365 ps
CPU time 2.58 seconds
Started Aug 27 05:16:56 AM UTC 24
Finished Aug 27 05:17:40 AM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124596162 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2124596162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2789066256
Short name T438
Test name
Test status
Simulation time 151513477 ps
CPU time 0.74 seconds
Started Aug 27 05:16:56 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 207964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789066256 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2789066256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.2428258500
Short name T407
Test name
Test status
Simulation time 39097039 ps
CPU time 0.57 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428258500 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.2428258500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.69684278
Short name T440
Test name
Test status
Simulation time 630248267 ps
CPU time 2.31 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:02 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69684278 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.69684278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.1140224470
Short name T520
Test name
Test status
Simulation time 4552127320 ps
CPU time 12.76 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:29 AM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1140224470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmg
r_stress_all_with_rand_reset.1140224470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.355320245
Short name T411
Test name
Test status
Simulation time 566067666 ps
CPU time 0.75 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355320245 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.355320245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.3776632019
Short name T409
Test name
Test status
Simulation time 39175749 ps
CPU time 0.56 seconds
Started Aug 27 05:16:51 AM UTC 24
Finished Aug 27 05:16:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776632019 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.3776632019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.287880365
Short name T434
Test name
Test status
Simulation time 27499539 ps
CPU time 0.6 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287880365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.287880365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.3204034625
Short name T447
Test name
Test status
Simulation time 83496231 ps
CPU time 0.59 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204034625 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.3204034625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2386015515
Short name T445
Test name
Test status
Simulation time 29597861 ps
CPU time 0.57 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386015515 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.2386015515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.2040443664
Short name T451
Test name
Test status
Simulation time 108437403 ps
CPU time 0.77 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040443664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2040443664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1649084938
Short name T442
Test name
Test status
Simulation time 30367401 ps
CPU time 0.63 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 206812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649084938 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1649084938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.3778343831
Short name T446
Test name
Test status
Simulation time 38724738 ps
CPU time 0.53 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778343831 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3778343831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.3522163934
Short name T454
Test name
Test status
Simulation time 51004507 ps
CPU time 0.59 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522163934 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.3522163934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.1936114948
Short name T433
Test name
Test status
Simulation time 123834595 ps
CPU time 0.7 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936114948 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.1936114948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.2434880279
Short name T435
Test name
Test status
Simulation time 52106589 ps
CPU time 0.7 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434880279 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2434880279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.2011124042
Short name T448
Test name
Test status
Simulation time 154552180 ps
CPU time 0.75 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 219908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011124042 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2011124042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2953875582
Short name T449
Test name
Test status
Simulation time 103419983 ps
CPU time 0.76 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953875582 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.2953875582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1568596792
Short name T621
Test name
Test status
Simulation time 835271079 ps
CPU time 2.47 seconds
Started Aug 27 05:17:00 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568596792 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1568596792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1197933984
Short name T623
Test name
Test status
Simulation time 762784334 ps
CPU time 2.83 seconds
Started Aug 27 05:17:00 AM UTC 24
Finished Aug 27 05:18:01 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197933984 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1197933984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.269893429
Short name T450
Test name
Test status
Simulation time 53113583 ps
CPU time 0.79 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269893429 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.269893429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.2468906130
Short name T431
Test name
Test status
Simulation time 27888887 ps
CPU time 0.6 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:00 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468906130 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2468906130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1461380844
Short name T482
Test name
Test status
Simulation time 741967027 ps
CPU time 3.06 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:19 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461380844 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1461380844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2255491496
Short name T65
Test name
Test status
Simulation time 13880585733 ps
CPU time 14.56 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:30 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2255491496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmg
r_stress_all_with_rand_reset.2255491496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.2266731368
Short name T436
Test name
Test status
Simulation time 252766943 ps
CPU time 0.7 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266731368 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2266731368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.797242296
Short name T437
Test name
Test status
Simulation time 132497087 ps
CPU time 0.8 seconds
Started Aug 27 05:16:58 AM UTC 24
Finished Aug 27 05:17:01 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797242296 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.797242296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.2273080861
Short name T462
Test name
Test status
Simulation time 60658098 ps
CPU time 0.71 seconds
Started Aug 27 05:17:03 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273080861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.2273080861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.222710672
Short name T472
Test name
Test status
Simulation time 71929339 ps
CPU time 0.61 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222710672 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.222710672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.544558773
Short name T456
Test name
Test status
Simulation time 36510875 ps
CPU time 0.52 seconds
Started Aug 27 05:17:04 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544558773 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.544558773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.1538032351
Short name T477
Test name
Test status
Simulation time 200546898 ps
CPU time 0.85 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538032351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.1538032351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.4118599056
Short name T468
Test name
Test status
Simulation time 45937760 ps
CPU time 0.51 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118599056 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.4118599056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.4258441463
Short name T459
Test name
Test status
Simulation time 21375880 ps
CPU time 0.54 seconds
Started Aug 27 05:17:04 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258441463 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.4258441463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.3255179951
Short name T473
Test name
Test status
Simulation time 42384284 ps
CPU time 0.64 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255179951 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.3255179951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.2017796901
Short name T466
Test name
Test status
Simulation time 278757945 ps
CPU time 0.89 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017796901 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.2017796901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.213963117
Short name T461
Test name
Test status
Simulation time 54165709 ps
CPU time 0.7 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213963117 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.213963117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1573304055
Short name T478
Test name
Test status
Simulation time 90491841 ps
CPU time 0.87 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573304055 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1573304055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.981833828
Short name T474
Test name
Test status
Simulation time 365919493 ps
CPU time 0.9 seconds
Started Aug 27 05:17:04 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981833828 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.981833828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.491753058
Short name T480
Test name
Test status
Simulation time 850613090 ps
CPU time 2.34 seconds
Started Aug 27 05:17:04 AM UTC 24
Finished Aug 27 05:17:18 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491753058 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.491753058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.767940118
Short name T481
Test name
Test status
Simulation time 814012838 ps
CPU time 2.81 seconds
Started Aug 27 05:17:04 AM UTC 24
Finished Aug 27 05:17:19 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767940118 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.767940118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.126111728
Short name T470
Test name
Test status
Simulation time 72998146 ps
CPU time 0.81 seconds
Started Aug 27 05:17:04 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126111728 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.126111728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.4018752873
Short name T458
Test name
Test status
Simulation time 32362369 ps
CPU time 0.61 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:16 AM UTC 24
Peak memory 209512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018752873 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.4018752873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.540629113
Short name T498
Test name
Test status
Simulation time 1999593590 ps
CPU time 3.18 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:29 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540629113 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.540629113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3408395635
Short name T58
Test name
Test status
Simulation time 6739642336 ps
CPU time 7.07 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:23 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3408395635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmg
r_stress_all_with_rand_reset.3408395635
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.1870521189
Short name T465
Test name
Test status
Simulation time 164280899 ps
CPU time 0.72 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870521189 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.1870521189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.1178427152
Short name T475
Test name
Test status
Simulation time 233147781 ps
CPU time 1.1 seconds
Started Aug 27 05:17:01 AM UTC 24
Finished Aug 27 05:17:17 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178427152 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.1178427152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.113660968
Short name T503
Test name
Test status
Simulation time 30793291 ps
CPU time 0.71 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113660968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.113660968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.2801590319
Short name T495
Test name
Test status
Simulation time 70018321 ps
CPU time 0.63 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801590319 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.2801590319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3597610693
Short name T499
Test name
Test status
Simulation time 29025561 ps
CPU time 0.56 seconds
Started Aug 27 05:17:12 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597610693 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.3597610693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.1098416149
Short name T485
Test name
Test status
Simulation time 387294194 ps
CPU time 0.78 seconds
Started Aug 27 05:17:16 AM UTC 24
Finished Aug 27 05:17:25 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098416149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1098416149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.2514489465
Short name T483
Test name
Test status
Simulation time 48536231 ps
CPU time 0.57 seconds
Started Aug 27 05:17:17 AM UTC 24
Finished Aug 27 05:17:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514489465 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2514489465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.1083261287
Short name T484
Test name
Test status
Simulation time 52425315 ps
CPU time 0.63 seconds
Started Aug 27 05:17:16 AM UTC 24
Finished Aug 27 05:17:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083261287 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.1083261287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.1766530174
Short name T489
Test name
Test status
Simulation time 51118416 ps
CPU time 0.58 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766530174 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.1766530174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2345157033
Short name T488
Test name
Test status
Simulation time 44661992 ps
CPU time 0.57 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345157033 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.2345157033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.3155416174
Short name T492
Test name
Test status
Simulation time 59926042 ps
CPU time 0.76 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155416174 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3155416174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1795677174
Short name T490
Test name
Test status
Simulation time 107793765 ps
CPU time 1.18 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795677174 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.1795677174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.1488197500
Short name T502
Test name
Test status
Simulation time 126358305 ps
CPU time 0.62 seconds
Started Aug 27 05:17:12 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488197500 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.1488197500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.534472033
Short name T519
Test name
Test status
Simulation time 904109167 ps
CPU time 2.15 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:29 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534472033 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.534472033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.942600255
Short name T518
Test name
Test status
Simulation time 962012918 ps
CPU time 2.28 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:29 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942600255 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.942600255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3686852963
Short name T505
Test name
Test status
Simulation time 53591995 ps
CPU time 0.84 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686852963 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3686852963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.2281603030
Short name T487
Test name
Test status
Simulation time 67459951 ps
CPU time 0.55 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281603030 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2281603030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.723625317
Short name T464
Test name
Test status
Simulation time 2225553750 ps
CPU time 3.03 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:30 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723625317 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.723625317
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1259944399
Short name T59
Test name
Test status
Simulation time 891830527 ps
CPU time 1.38 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1259944399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg
r_stress_all_with_rand_reset.1259944399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.3291961467
Short name T500
Test name
Test status
Simulation time 218992843 ps
CPU time 1.1 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291961467 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.3291961467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.1986845394
Short name T494
Test name
Test status
Simulation time 222642944 ps
CPU time 0.82 seconds
Started Aug 27 05:17:08 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 210464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986845394 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.1986845394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.4206789377
Short name T507
Test name
Test status
Simulation time 76083679 ps
CPU time 0.75 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206789377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.4206789377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.4174759029
Short name T512
Test name
Test status
Simulation time 60044657 ps
CPU time 0.63 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174759029 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.4174759029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3573369062
Short name T506
Test name
Test status
Simulation time 31015255 ps
CPU time 0.67 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573369062 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.3573369062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.2965103009
Short name T515
Test name
Test status
Simulation time 383540622 ps
CPU time 0.74 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965103009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2965103009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.1189382807
Short name T510
Test name
Test status
Simulation time 33648885 ps
CPU time 0.67 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189382807 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.1189382807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.942511380
Short name T504
Test name
Test status
Simulation time 44303086 ps
CPU time 0.63 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942511380 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.942511380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.3649822221
Short name T509
Test name
Test status
Simulation time 40651264 ps
CPU time 0.61 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649822221 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.3649822221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.293625901
Short name T516
Test name
Test status
Simulation time 232875956 ps
CPU time 1.13 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293625901 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.293625901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.1891708919
Short name T501
Test name
Test status
Simulation time 141667529 ps
CPU time 0.71 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891708919 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1891708919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.2367501350
Short name T493
Test name
Test status
Simulation time 96110813 ps
CPU time 1.07 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367501350 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2367501350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1466463177
Short name T517
Test name
Test status
Simulation time 67105566 ps
CPU time 0.88 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466463177 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.1466463177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3584143177
Short name T522
Test name
Test status
Simulation time 805790947 ps
CPU time 2.82 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:30 AM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584143177 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3584143177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.244565692
Short name T521
Test name
Test status
Simulation time 1174329700 ps
CPU time 2.1 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:29 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244565692 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.244565692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.179093125
Short name T511
Test name
Test status
Simulation time 257692553 ps
CPU time 0.76 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179093125 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.179093125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.591231872
Short name T496
Test name
Test status
Simulation time 40554488 ps
CPU time 0.57 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591231872 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.591231872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.495913218
Short name T634
Test name
Test status
Simulation time 1783560016 ps
CPU time 5.81 seconds
Started Aug 27 05:17:20 AM UTC 24
Finished Aug 27 05:18:04 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495913218 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.495913218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.2951261481
Short name T523
Test name
Test status
Simulation time 3427052144 ps
CPU time 4.77 seconds
Started Aug 27 05:17:19 AM UTC 24
Finished Aug 27 05:17:32 AM UTC 24
Peak memory 211632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2951261481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmg
r_stress_all_with_rand_reset.2951261481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.1779800304
Short name T497
Test name
Test status
Simulation time 78338192 ps
CPU time 0.71 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:27 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779800304 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.1779800304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.834699642
Short name T513
Test name
Test status
Simulation time 201252482 ps
CPU time 1 seconds
Started Aug 27 05:17:18 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834699642 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.834699642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2068933169
Short name T491
Test name
Test status
Simulation time 92622693 ps
CPU time 0.67 seconds
Started Aug 27 05:17:26 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068933169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2068933169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.1587367318
Short name T548
Test name
Test status
Simulation time 61958456 ps
CPU time 0.72 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:48 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587367318 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.1587367318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.586643653
Short name T525
Test name
Test status
Simulation time 38621425 ps
CPU time 0.54 seconds
Started Aug 27 05:17:27 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586643653 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.586643653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.2071178560
Short name T556
Test name
Test status
Simulation time 394129871 ps
CPU time 0.75 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:55 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071178560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2071178560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.1660232784
Short name T553
Test name
Test status
Simulation time 59146811 ps
CPU time 0.53 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:55 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660232784 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1660232784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.79362458
Short name T543
Test name
Test status
Simulation time 43043981 ps
CPU time 0.55 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:41 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79362458 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.79362458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.4071506319
Short name T526
Test name
Test status
Simulation time 89566599 ps
CPU time 0.59 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071506319 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.4071506319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.2860266394
Short name T486
Test name
Test status
Simulation time 192074865 ps
CPU time 0.7 seconds
Started Aug 27 05:17:24 AM UTC 24
Finished Aug 27 05:17:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860266394 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.2860266394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.1609689959
Short name T598
Test name
Test status
Simulation time 158709013 ps
CPU time 0.73 seconds
Started Aug 27 05:17:20 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609689959 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1609689959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.2683116852
Short name T584
Test name
Test status
Simulation time 164253324 ps
CPU time 0.72 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683116852 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2683116852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.4003354825
Short name T533
Test name
Test status
Simulation time 159759924 ps
CPU time 0.75 seconds
Started Aug 27 05:17:27 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003354825 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.4003354825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1874866724
Short name T537
Test name
Test status
Simulation time 779730637 ps
CPU time 2.75 seconds
Started Aug 27 05:17:26 AM UTC 24
Finished Aug 27 05:17:37 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874866724 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1874866724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.674274986
Short name T538
Test name
Test status
Simulation time 1379242558 ps
CPU time 2.09 seconds
Started Aug 27 05:17:27 AM UTC 24
Finished Aug 27 05:17:38 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674274986 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.674274986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.557000170
Short name T534
Test name
Test status
Simulation time 134432092 ps
CPU time 0.82 seconds
Started Aug 27 05:17:27 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557000170 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.557000170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.1050997925
Short name T592
Test name
Test status
Simulation time 33168284 ps
CPU time 0.58 seconds
Started Aug 27 05:17:20 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050997925 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1050997925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.1203615590
Short name T555
Test name
Test status
Simulation time 2437057401 ps
CPU time 3.48 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203615590 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1203615590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3998807481
Short name T694
Test name
Test status
Simulation time 9251915299 ps
CPU time 11.81 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:18:07 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3998807481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmg
r_stress_all_with_rand_reset.3998807481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.1290763048
Short name T460
Test name
Test status
Simulation time 79640226 ps
CPU time 0.55 seconds
Started Aug 27 05:17:26 AM UTC 24
Finished Aug 27 05:17:28 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290763048 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.1290763048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.2985968915
Short name T508
Test name
Test status
Simulation time 61040445 ps
CPU time 0.58 seconds
Started Aug 27 05:17:26 AM UTC 24
Finished Aug 27 05:17:35 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985968915 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2985968915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.3394640367
Short name T562
Test name
Test status
Simulation time 35616997 ps
CPU time 0.74 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394640367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3394640367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.937312642
Short name T589
Test name
Test status
Simulation time 32011114 ps
CPU time 0.54 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 206052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937312642 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.937312642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.3703297617
Short name T597
Test name
Test status
Simulation time 201254065 ps
CPU time 0.76 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703297617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3703297617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.3886908551
Short name T551
Test name
Test status
Simulation time 36674982 ps
CPU time 0.49 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886908551 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3886908551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.499262084
Short name T591
Test name
Test status
Simulation time 40114974 ps
CPU time 0.52 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499262084 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.499262084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.810347987
Short name T594
Test name
Test status
Simulation time 40935043 ps
CPU time 0.6 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810347987 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.810347987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.2321021339
Short name T573
Test name
Test status
Simulation time 199851178 ps
CPU time 1.06 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321021339 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.2321021339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.2588803008
Short name T560
Test name
Test status
Simulation time 79268254 ps
CPU time 0.64 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588803008 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2588803008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1039613763
Short name T596
Test name
Test status
Simulation time 460361291 ps
CPU time 0.68 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039613763 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1039613763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.185864831
Short name T595
Test name
Test status
Simulation time 267864687 ps
CPU time 0.97 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185864831 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.185864831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2261472750
Short name T622
Test name
Test status
Simulation time 830722548 ps
CPU time 2.71 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:18:01 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261472750 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2261472750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1341782307
Short name T615
Test name
Test status
Simulation time 1450374646 ps
CPU time 1.94 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 209768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341782307 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1341782307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3652212523
Short name T593
Test name
Test status
Simulation time 52674001 ps
CPU time 0.77 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652212523 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3652212523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.1997302089
Short name T557
Test name
Test status
Simulation time 35518571 ps
CPU time 0.58 seconds
Started Aug 27 05:17:29 AM UTC 24
Finished Aug 27 05:17:55 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997302089 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1997302089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.1535030392
Short name T619
Test name
Test status
Simulation time 479652791 ps
CPU time 1.76 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535030392 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.1535030392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.933718646
Short name T620
Test name
Test status
Simulation time 14582381092 ps
CPU time 9.41 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=933718646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr
_stress_all_with_rand_reset.933718646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.2577639185
Short name T568
Test name
Test status
Simulation time 325949214 ps
CPU time 0.87 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577639185 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2577639185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.2588761489
Short name T590
Test name
Test status
Simulation time 86009758 ps
CPU time 0.7 seconds
Started Aug 27 05:17:30 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588761489 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.2588761489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.812280418
Short name T529
Test name
Test status
Simulation time 20302896 ps
CPU time 0.54 seconds
Started Aug 27 05:17:32 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812280418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.812280418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.3097128843
Short name T572
Test name
Test status
Simulation time 117079932 ps
CPU time 0.7 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097128843 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.3097128843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.3284175359
Short name T531
Test name
Test status
Simulation time 39353345 ps
CPU time 0.5 seconds
Started Aug 27 05:17:32 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284175359 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.3284175359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.2487796777
Short name T569
Test name
Test status
Simulation time 48525738 ps
CPU time 0.66 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487796777 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2487796777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.2633736525
Short name T563
Test name
Test status
Simulation time 63549879 ps
CPU time 0.58 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633736525 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2633736525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.801635983
Short name T565
Test name
Test status
Simulation time 42799855 ps
CPU time 0.65 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801635983 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.801635983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.1346936983
Short name T528
Test name
Test status
Simulation time 62407272 ps
CPU time 0.52 seconds
Started Aug 27 05:17:31 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346936983 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.1346936983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.1506439616
Short name T530
Test name
Test status
Simulation time 37795212 ps
CPU time 0.62 seconds
Started Aug 27 05:17:31 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 210944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506439616 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1506439616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.2647192603
Short name T571
Test name
Test status
Simulation time 191484139 ps
CPU time 0.68 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647192603 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2647192603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2478690408
Short name T524
Test name
Test status
Simulation time 153874701 ps
CPU time 0.84 seconds
Started Aug 27 05:17:33 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478690408 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.2478690408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3635529644
Short name T540
Test name
Test status
Simulation time 842551259 ps
CPU time 2.6 seconds
Started Aug 27 05:17:32 AM UTC 24
Finished Aug 27 05:17:38 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635529644 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3635529644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.66894111
Short name T539
Test name
Test status
Simulation time 967755823 ps
CPU time 2.35 seconds
Started Aug 27 05:17:32 AM UTC 24
Finished Aug 27 05:17:38 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66894111 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.66894111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.111763844
Short name T535
Test name
Test status
Simulation time 107691209 ps
CPU time 0.77 seconds
Started Aug 27 05:17:32 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111763844 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.111763844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.3495505317
Short name T453
Test name
Test status
Simulation time 29139525 ps
CPU time 0.59 seconds
Started Aug 27 05:17:31 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495505317 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3495505317
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3570585156
Short name T582
Test name
Test status
Simulation time 1245727263 ps
CPU time 2.31 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570585156 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3570585156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.2214410164
Short name T124
Test name
Test status
Simulation time 1000829247 ps
CPU time 1.86 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:57 AM UTC 24
Peak memory 210476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2214410164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmg
r_stress_all_with_rand_reset.2214410164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.2730798897
Short name T532
Test name
Test status
Simulation time 321000704 ps
CPU time 0.83 seconds
Started Aug 27 05:17:31 AM UTC 24
Finished Aug 27 05:17:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730798897 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2730798897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.905968460
Short name T536
Test name
Test status
Simulation time 281321965 ps
CPU time 1 seconds
Started Aug 27 05:17:31 AM UTC 24
Finished Aug 27 05:17:37 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905968460 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.905968460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.2736945733
Short name T544
Test name
Test status
Simulation time 42839119 ps
CPU time 0.76 seconds
Started Aug 27 05:17:38 AM UTC 24
Finished Aug 27 05:17:41 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736945733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2736945733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.741191815
Short name T561
Test name
Test status
Simulation time 73558319 ps
CPU time 0.59 seconds
Started Aug 27 05:17:41 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741191815 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.741191815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.4434115
Short name T549
Test name
Test status
Simulation time 41256237 ps
CPU time 0.48 seconds
Started Aug 27 05:17:39 AM UTC 24
Finished Aug 27 05:17:51 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4434115 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.4434115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.1488144871
Short name T564
Test name
Test status
Simulation time 112973224 ps
CPU time 0.74 seconds
Started Aug 27 05:17:41 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488144871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1488144871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.156598981
Short name T558
Test name
Test status
Simulation time 55603553 ps
CPU time 0.61 seconds
Started Aug 27 05:17:41 AM UTC 24
Finished Aug 27 05:17:55 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156598981 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.156598981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.1996656381
Short name T554
Test name
Test status
Simulation time 115855588 ps
CPU time 0.5 seconds
Started Aug 27 05:17:41 AM UTC 24
Finished Aug 27 05:17:55 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996656381 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.1996656381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.1916678784
Short name T583
Test name
Test status
Simulation time 48361059 ps
CPU time 0.63 seconds
Started Aug 27 05:17:42 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916678784 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.1916678784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.2367475883
Short name T575
Test name
Test status
Simulation time 332751499 ps
CPU time 0.61 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367475883 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.2367475883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.12045201
Short name T566
Test name
Test status
Simulation time 66781049 ps
CPU time 0.63 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12045201 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.12045201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.2013034640
Short name T578
Test name
Test status
Simulation time 133325413 ps
CPU time 0.66 seconds
Started Aug 27 05:17:42 AM UTC 24
Finished Aug 27 05:17:57 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013034640 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.2013034640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.3641685636
Short name T559
Test name
Test status
Simulation time 134466130 ps
CPU time 0.71 seconds
Started Aug 27 05:17:41 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641685636 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.3641685636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.657630294
Short name T547
Test name
Test status
Simulation time 936578815 ps
CPU time 1.98 seconds
Started Aug 27 05:17:38 AM UTC 24
Finished Aug 27 05:17:42 AM UTC 24
Peak memory 210416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657630294 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.657630294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1891272845
Short name T546
Test name
Test status
Simulation time 991534970 ps
CPU time 1.71 seconds
Started Aug 27 05:17:38 AM UTC 24
Finished Aug 27 05:17:42 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891272845 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1891272845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.176750563
Short name T550
Test name
Test status
Simulation time 166554670 ps
CPU time 0.75 seconds
Started Aug 27 05:17:39 AM UTC 24
Finished Aug 27 05:17:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176750563 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.176750563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.2724254875
Short name T567
Test name
Test status
Simulation time 39042600 ps
CPU time 0.56 seconds
Started Aug 27 05:17:37 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724254875 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2724254875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.1249186840
Short name T552
Test name
Test status
Simulation time 2361401221 ps
CPU time 3.24 seconds
Started Aug 27 05:17:42 AM UTC 24
Finished Aug 27 05:17:53 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249186840 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.1249186840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.2228929232
Short name T545
Test name
Test status
Simulation time 625266026 ps
CPU time 0.72 seconds
Started Aug 27 05:17:38 AM UTC 24
Finished Aug 27 05:17:41 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228929232 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2228929232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.1216903348
Short name T542
Test name
Test status
Simulation time 138555824 ps
CPU time 0.61 seconds
Started Aug 27 05:17:38 AM UTC 24
Finished Aug 27 05:17:41 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216903348 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.1216903348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.206378435
Short name T579
Test name
Test status
Simulation time 63234271 ps
CPU time 0.65 seconds
Started Aug 27 05:17:52 AM UTC 24
Finished Aug 27 05:17:57 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206378435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.206378435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.3066826601
Short name T603
Test name
Test status
Simulation time 52455969 ps
CPU time 0.65 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066826601 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.3066826601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2772627062
Short name T602
Test name
Test status
Simulation time 37824972 ps
CPU time 0.57 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772627062 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.2772627062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.4038336345
Short name T608
Test name
Test status
Simulation time 722493454 ps
CPU time 0.79 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038336345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.4038336345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.140988829
Short name T601
Test name
Test status
Simulation time 61618570 ps
CPU time 0.58 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140988829 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.140988829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.3881283767
Short name T600
Test name
Test status
Simulation time 81110653 ps
CPU time 0.59 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881283767 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3881283767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.2823084279
Short name T604
Test name
Test status
Simulation time 88617598 ps
CPU time 0.61 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823084279 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.2823084279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.478378833
Short name T588
Test name
Test status
Simulation time 458287862 ps
CPU time 0.92 seconds
Started Aug 27 05:17:49 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478378833 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.478378833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.953384514
Short name T576
Test name
Test status
Simulation time 93301444 ps
CPU time 0.72 seconds
Started Aug 27 05:17:43 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953384514 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.953384514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.3029525856
Short name T606
Test name
Test status
Simulation time 112167082 ps
CPU time 0.73 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029525856 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3029525856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.3108838792
Short name T599
Test name
Test status
Simulation time 73098326 ps
CPU time 0.58 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108838792 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.3108838792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2604091948
Short name T586
Test name
Test status
Simulation time 771038232 ps
CPU time 2.69 seconds
Started Aug 27 05:17:54 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604091948 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2604091948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2292986918
Short name T527
Test name
Test status
Simulation time 1525901108 ps
CPU time 1.59 seconds
Started Aug 27 05:17:56 AM UTC 24
Finished Aug 27 05:17:58 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292986918 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2292986918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2855275874
Short name T581
Test name
Test status
Simulation time 80684638 ps
CPU time 0.88 seconds
Started Aug 27 05:17:56 AM UTC 24
Finished Aug 27 05:17:57 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855275874 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2855275874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.1704175940
Short name T574
Test name
Test status
Simulation time 29981503 ps
CPU time 0.59 seconds
Started Aug 27 05:17:43 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704175940 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1704175940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.892197021
Short name T637
Test name
Test status
Simulation time 2793130503 ps
CPU time 3.09 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892197021 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.892197021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.1327911710
Short name T66
Test name
Test status
Simulation time 6470172289 ps
CPU time 12.97 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:18:12 AM UTC 24
Peak memory 211652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1327911710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmg
r_stress_all_with_rand_reset.1327911710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.83097992
Short name T577
Test name
Test status
Simulation time 245205148 ps
CPU time 1.05 seconds
Started Aug 27 05:17:51 AM UTC 24
Finished Aug 27 05:17:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83097992 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.83097992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.489902762
Short name T580
Test name
Test status
Simulation time 235095929 ps
CPU time 0.88 seconds
Started Aug 27 05:17:52 AM UTC 24
Finished Aug 27 05:17:57 AM UTC 24
Peak memory 210056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489902762 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.489902762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.1139986272
Short name T26
Test name
Test status
Simulation time 43580946 ps
CPU time 0.81 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139986272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1139986272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2824748175
Short name T137
Test name
Test status
Simulation time 62474049 ps
CPU time 0.71 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824748175 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.2824748175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.4261793324
Short name T134
Test name
Test status
Simulation time 46059147 ps
CPU time 0.56 seconds
Started Aug 27 05:15:55 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261793324 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.4261793324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.872972414
Short name T127
Test name
Test status
Simulation time 386314355 ps
CPU time 0.82 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872972414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.872972414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1833249706
Short name T19
Test name
Test status
Simulation time 60837335 ps
CPU time 0.56 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833249706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1833249706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.2616386076
Short name T173
Test name
Test status
Simulation time 80097456 ps
CPU time 0.65 seconds
Started Aug 27 05:15:55 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616386076 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2616386076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.4035365288
Short name T174
Test name
Test status
Simulation time 77166814 ps
CPU time 0.57 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035365288 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.4035365288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.1212067254
Short name T7
Test name
Test status
Simulation time 308334685 ps
CPU time 1.33 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212067254 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.1212067254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3049276035
Short name T63
Test name
Test status
Simulation time 99431696 ps
CPU time 0.73 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049276035 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3049276035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.2847077922
Short name T43
Test name
Test status
Simulation time 117029486 ps
CPU time 0.84 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847077922 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2847077922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.1885797980
Short name T30
Test name
Test status
Simulation time 370952081 ps
CPU time 1.38 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 236888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885797980 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1885797980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2028359851
Short name T160
Test name
Test status
Simulation time 169424224 ps
CPU time 1.03 seconds
Started Aug 27 05:15:55 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028359851 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.2028359851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3594698720
Short name T142
Test name
Test status
Simulation time 868261684 ps
CPU time 2.26 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:56 AM UTC 24
Peak memory 211576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594698720 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3594698720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1372712085
Short name T136
Test name
Test status
Simulation time 1018379145 ps
CPU time 1.83 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:56 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372712085 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1372712085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1604565765
Short name T172
Test name
Test status
Simulation time 68921085 ps
CPU time 0.75 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604565765 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1604565765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.1492619225
Short name T61
Test name
Test status
Simulation time 48766188 ps
CPU time 0.62 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492619225 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1492619225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.305155745
Short name T70
Test name
Test status
Simulation time 1026839907 ps
CPU time 1.7 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305155745 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.305155745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2806770847
Short name T25
Test name
Test status
Simulation time 7283144313 ps
CPU time 9.32 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2806770847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr
_stress_all_with_rand_reset.2806770847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3248485309
Short name T64
Test name
Test status
Simulation time 211915493 ps
CPU time 0.77 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248485309 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.3248485309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3669103597
Short name T4
Test name
Test status
Simulation time 117986792 ps
CPU time 0.93 seconds
Started Aug 27 05:15:53 AM UTC 24
Finished Aug 27 05:15:55 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669103597 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3669103597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.1560950658
Short name T611
Test name
Test status
Simulation time 71722886 ps
CPU time 0.76 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560950658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1560950658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.3252080767
Short name T627
Test name
Test status
Simulation time 92170806 ps
CPU time 0.6 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252080767 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.3252080767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3848913628
Short name T610
Test name
Test status
Simulation time 29657995 ps
CPU time 0.55 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 205560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848913628 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.3848913628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.984347537
Short name T618
Test name
Test status
Simulation time 112379219 ps
CPU time 0.75 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984347537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.984347537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.2544658126
Short name T625
Test name
Test status
Simulation time 37011950 ps
CPU time 0.53 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544658126 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2544658126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.1502427225
Short name T612
Test name
Test status
Simulation time 31413724 ps
CPU time 0.56 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502427225 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1502427225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.1637590778
Short name T626
Test name
Test status
Simulation time 43324418 ps
CPU time 0.61 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:01 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637590778 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.1637590778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.3355006466
Short name T613
Test name
Test status
Simulation time 93218790 ps
CPU time 0.74 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355006466 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.3355006466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.812312689
Short name T609
Test name
Test status
Simulation time 116452689 ps
CPU time 0.85 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812312689 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.812312689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.31873162
Short name T630
Test name
Test status
Simulation time 175366754 ps
CPU time 0.65 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31873162 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.31873162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1789827064
Short name T614
Test name
Test status
Simulation time 207027976 ps
CPU time 0.71 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789827064 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.1789827064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3442054332
Short name T629
Test name
Test status
Simulation time 889301496 ps
CPU time 2.66 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442054332 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3442054332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2482457039
Short name T638
Test name
Test status
Simulation time 880442101 ps
CPU time 2.98 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482457039 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2482457039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1123837867
Short name T617
Test name
Test status
Simulation time 66729677 ps
CPU time 0.73 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123837867 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1123837867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.595207030
Short name T605
Test name
Test status
Simulation time 76303808 ps
CPU time 0.56 seconds
Started Aug 27 05:17:57 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595207030 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.595207030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.3940874993
Short name T640
Test name
Test status
Simulation time 67106567 ps
CPU time 1 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 210668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940874993 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3940874993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1726213707
Short name T657
Test name
Test status
Simulation time 1149018566 ps
CPU time 2.9 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:04 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1726213707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg
r_stress_all_with_rand_reset.1726213707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.795616849
Short name T616
Test name
Test status
Simulation time 692466623 ps
CPU time 0.79 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:18:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795616849 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.795616849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.2971267026
Short name T607
Test name
Test status
Simulation time 96580916 ps
CPU time 0.65 seconds
Started Aug 27 05:17:58 AM UTC 24
Finished Aug 27 05:17:59 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971267026 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.2971267026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3488885301
Short name T646
Test name
Test status
Simulation time 32669830 ps
CPU time 1 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 210884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488885301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3488885301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.1562506289
Short name T645
Test name
Test status
Simulation time 51262565 ps
CPU time 0.65 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562506289 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.1562506289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2970070014
Short name T636
Test name
Test status
Simulation time 41891901 ps
CPU time 0.52 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 206028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970070014 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.2970070014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.3604370218
Short name T649
Test name
Test status
Simulation time 200755813 ps
CPU time 0.84 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604370218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.3604370218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.739026600
Short name T643
Test name
Test status
Simulation time 31456700 ps
CPU time 0.61 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739026600 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.739026600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.800546047
Short name T639
Test name
Test status
Simulation time 28920529 ps
CPU time 0.56 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800546047 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.800546047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.1716907956
Short name T650
Test name
Test status
Simulation time 89518657 ps
CPU time 0.67 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716907956 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.1716907956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.3077694402
Short name T651
Test name
Test status
Simulation time 297121532 ps
CPU time 1.3 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077694402 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.3077694402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.142266577
Short name T632
Test name
Test status
Simulation time 64945877 ps
CPU time 0.6 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142266577 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.142266577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3018356772
Short name T652
Test name
Test status
Simulation time 278862645 ps
CPU time 0.72 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018356772 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3018356772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1154520114
Short name T644
Test name
Test status
Simulation time 210992149 ps
CPU time 0.75 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154520114 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.1154520114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2413418290
Short name T656
Test name
Test status
Simulation time 875694883 ps
CPU time 2.1 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:03 AM UTC 24
Peak memory 211640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413418290 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2413418290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3652021024
Short name T655
Test name
Test status
Simulation time 2128208812 ps
CPU time 1.87 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:03 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652021024 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3652021024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1779934596
Short name T647
Test name
Test status
Simulation time 73511291 ps
CPU time 0.9 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779934596 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1779934596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.3396069929
Short name T628
Test name
Test status
Simulation time 62351550 ps
CPU time 0.54 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:01 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396069929 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3396069929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.674968757
Short name T587
Test name
Test status
Simulation time 1840454704 ps
CPU time 2.69 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:04 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674968757 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.674968757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.638319565
Short name T115
Test name
Test status
Simulation time 5072473267 ps
CPU time 13.59 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:15 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=638319565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr
_stress_all_with_rand_reset.638319565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.3172270902
Short name T642
Test name
Test status
Simulation time 215997055 ps
CPU time 0.85 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172270902 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.3172270902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.2133009934
Short name T633
Test name
Test status
Simulation time 53730774 ps
CPU time 0.66 seconds
Started Aug 27 05:18:00 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133009934 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.2133009934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.2803885246
Short name T631
Test name
Test status
Simulation time 46962366 ps
CPU time 0.57 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 207908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803885246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2803885246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.3196519552
Short name T662
Test name
Test status
Simulation time 88396090 ps
CPU time 0.62 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196519552 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.3196519552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1609893739
Short name T624
Test name
Test status
Simulation time 40052154 ps
CPU time 0.54 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 206076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609893739 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.1609893739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.2392425902
Short name T665
Test name
Test status
Simulation time 208880922 ps
CPU time 0.77 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392425902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2392425902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2257997575
Short name T660
Test name
Test status
Simulation time 42776551 ps
CPU time 0.57 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257997575 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2257997575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1725557026
Short name T658
Test name
Test status
Simulation time 274071789 ps
CPU time 0.52 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725557026 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1725557026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.4119637487
Short name T663
Test name
Test status
Simulation time 72306515 ps
CPU time 0.55 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119637487 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.4119637487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.3566402355
Short name T648
Test name
Test status
Simulation time 45634882 ps
CPU time 0.57 seconds
Started Aug 27 05:18:01 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566402355 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.3566402355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.2607932281
Short name T654
Test name
Test status
Simulation time 138234976 ps
CPU time 0.76 seconds
Started Aug 27 05:18:01 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607932281 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2607932281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.2143745389
Short name T664
Test name
Test status
Simulation time 160536838 ps
CPU time 0.67 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143745389 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2143745389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.2935366352
Short name T659
Test name
Test status
Simulation time 36446069 ps
CPU time 0.59 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 208084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935366352 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.2935366352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4188139154
Short name T679
Test name
Test status
Simulation time 923423811 ps
CPU time 1.76 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188139154 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4188139154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.674184264
Short name T692
Test name
Test status
Simulation time 1222945966 ps
CPU time 2.1 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674184264 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.674184264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3591963122
Short name T661
Test name
Test status
Simulation time 184324065 ps
CPU time 0.75 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591963122 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3591963122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.1569626491
Short name T653
Test name
Test status
Simulation time 57870370 ps
CPU time 0.64 seconds
Started Aug 27 05:18:01 AM UTC 24
Finished Aug 27 05:18:02 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569626491 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1569626491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.3465476944
Short name T710
Test name
Test status
Simulation time 2304188455 ps
CPU time 4.12 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465476944 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3465476944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3730806012
Short name T47
Test name
Test status
Simulation time 6595122723 ps
CPU time 12.75 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:18 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3730806012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg
r_stress_all_with_rand_reset.3730806012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.1749194896
Short name T635
Test name
Test status
Simulation time 218366070 ps
CPU time 0.77 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749194896 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.1749194896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.2028023471
Short name T641
Test name
Test status
Simulation time 536554613 ps
CPU time 0.8 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028023471 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.2028023471
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.906213997
Short name T669
Test name
Test status
Simulation time 75452997 ps
CPU time 0.62 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906213997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.906213997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2814051795
Short name T685
Test name
Test status
Simulation time 57374274 ps
CPU time 0.87 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814051795 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.2814051795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2258226175
Short name T672
Test name
Test status
Simulation time 38471575 ps
CPU time 0.56 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258226175 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.2258226175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.1882022472
Short name T684
Test name
Test status
Simulation time 206057745 ps
CPU time 0.83 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882022472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1882022472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.1644327969
Short name T675
Test name
Test status
Simulation time 53425829 ps
CPU time 0.6 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644327969 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.1644327969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.2088064306
Short name T674
Test name
Test status
Simulation time 31626616 ps
CPU time 0.53 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088064306 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2088064306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.3298361243
Short name T678
Test name
Test status
Simulation time 64416644 ps
CPU time 0.6 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298361243 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.3298361243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.2211146620
Short name T670
Test name
Test status
Simulation time 456844775 ps
CPU time 0.69 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211146620 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.2211146620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.2693422392
Short name T666
Test name
Test status
Simulation time 51317147 ps
CPU time 0.7 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 210964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693422392 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2693422392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.372441235
Short name T687
Test name
Test status
Simulation time 104415190 ps
CPU time 0.94 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372441235 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.372441235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1402624095
Short name T682
Test name
Test status
Simulation time 219354469 ps
CPU time 1.02 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402624095 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.1402624095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2375527415
Short name T695
Test name
Test status
Simulation time 840640725 ps
CPU time 2.11 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:07 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375527415 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2375527415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.739118455
Short name T697
Test name
Test status
Simulation time 838989041 ps
CPU time 2.64 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739118455 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.739118455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3969345994
Short name T677
Test name
Test status
Simulation time 88724214 ps
CPU time 0.72 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969345994 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3969345994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.1699079016
Short name T667
Test name
Test status
Simulation time 84725712 ps
CPU time 0.58 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:05 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699079016 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1699079016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.4213360531
Short name T715
Test name
Test status
Simulation time 1904930527 ps
CPU time 3.79 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213360531 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.4213360531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.963743132
Short name T762
Test name
Test status
Simulation time 5508312048 ps
CPU time 15.08 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:20 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=963743132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr
_stress_all_with_rand_reset.963743132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.1024094469
Short name T673
Test name
Test status
Simulation time 272035516 ps
CPU time 0.76 seconds
Started Aug 27 05:18:03 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024094469 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.1024094469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.2415710272
Short name T671
Test name
Test status
Simulation time 154384480 ps
CPU time 0.7 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415710272 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.2415710272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.4044469535
Short name T681
Test name
Test status
Simulation time 46969607 ps
CPU time 0.6 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 209576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044469535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.4044469535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2849093655
Short name T701
Test name
Test status
Simulation time 70983477 ps
CPU time 0.73 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849093655 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.2849093655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.768177836
Short name T683
Test name
Test status
Simulation time 39123087 ps
CPU time 0.52 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768177836 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.768177836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.2612116330
Short name T703
Test name
Test status
Simulation time 111655170 ps
CPU time 0.87 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612116330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2612116330
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.453031127
Short name T699
Test name
Test status
Simulation time 46743416 ps
CPU time 0.61 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453031127 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.453031127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.3244578550
Short name T698
Test name
Test status
Simulation time 46729271 ps
CPU time 0.64 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244578550 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3244578550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.1265579759
Short name T700
Test name
Test status
Simulation time 256509517 ps
CPU time 0.56 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 210760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265579759 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.1265579759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.1301151741
Short name T686
Test name
Test status
Simulation time 31894481 ps
CPU time 0.7 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301151741 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.1301151741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.662214585
Short name T689
Test name
Test status
Simulation time 119931247 ps
CPU time 0.79 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662214585 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.662214585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.86466588
Short name T704
Test name
Test status
Simulation time 394940492 ps
CPU time 0.67 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86466588 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.86466588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.1941961725
Short name T693
Test name
Test status
Simulation time 257297903 ps
CPU time 1.06 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:07 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941961725 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.1941961725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.993613783
Short name T702
Test name
Test status
Simulation time 879237264 ps
CPU time 2.63 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:08 AM UTC 24
Peak memory 211368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993613783 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.993613783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3644248681
Short name T696
Test name
Test status
Simulation time 1166814546 ps
CPU time 2 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:07 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644248681 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3644248681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.545461026
Short name T688
Test name
Test status
Simulation time 167380242 ps
CPU time 0.77 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545461026 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.545461026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.3904845652
Short name T680
Test name
Test status
Simulation time 34503366 ps
CPU time 0.6 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904845652 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3904845652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.1462616209
Short name T721
Test name
Test status
Simulation time 466979426 ps
CPU time 1.93 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:10 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462616209 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.1462616209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2459510611
Short name T747
Test name
Test status
Simulation time 1870013731 ps
CPU time 6.84 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:15 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2459510611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmg
r_stress_all_with_rand_reset.2459510611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.2720467435
Short name T691
Test name
Test status
Simulation time 164427904 ps
CPU time 0.98 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720467435 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.2720467435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.2256460161
Short name T690
Test name
Test status
Simulation time 192739708 ps
CPU time 0.96 seconds
Started Aug 27 05:18:04 AM UTC 24
Finished Aug 27 05:18:06 AM UTC 24
Peak memory 209216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256460161 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2256460161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.3921161833
Short name T706
Test name
Test status
Simulation time 174983080 ps
CPU time 0.66 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921161833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3921161833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.3044713262
Short name T718
Test name
Test status
Simulation time 119488513 ps
CPU time 0.67 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044713262 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.3044713262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3491630630
Short name T707
Test name
Test status
Simulation time 29857553 ps
CPU time 0.61 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491630630 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.3491630630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.4049563131
Short name T717
Test name
Test status
Simulation time 343327136 ps
CPU time 0.78 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049563131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.4049563131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.3899273378
Short name T716
Test name
Test status
Simulation time 81305227 ps
CPU time 0.6 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 206204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899273378 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3899273378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.3305084659
Short name T712
Test name
Test status
Simulation time 46884094 ps
CPU time 0.6 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305084659 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3305084659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.390073029
Short name T722
Test name
Test status
Simulation time 53470547 ps
CPU time 0.61 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:10 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390073029 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.390073029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.1059462752
Short name T720
Test name
Test status
Simulation time 279868814 ps
CPU time 1.23 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059462752 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.1059462752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.1290420132
Short name T708
Test name
Test status
Simulation time 99757468 ps
CPU time 0.73 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290420132 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1290420132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.4226658843
Short name T740
Test name
Test status
Simulation time 150324495 ps
CPU time 0.7 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:12 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226658843 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.4226658843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.3587326013
Short name T719
Test name
Test status
Simulation time 185504869 ps
CPU time 0.99 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587326013 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.3587326013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1195296273
Short name T735
Test name
Test status
Simulation time 791286231 ps
CPU time 2.92 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195296273 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1195296273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2678381442
Short name T723
Test name
Test status
Simulation time 1012474915 ps
CPU time 2.26 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:10 AM UTC 24
Peak memory 211072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678381442 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2678381442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3997944154
Short name T714
Test name
Test status
Simulation time 67015114 ps
CPU time 0.82 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997944154 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3997944154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.881115911
Short name T705
Test name
Test status
Simulation time 32894487 ps
CPU time 0.61 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 208220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881115911 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.881115911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.1751947259
Short name T730
Test name
Test status
Simulation time 265463429 ps
CPU time 1.1 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751947259 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.1751947259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.865829265
Short name T745
Test name
Test status
Simulation time 1371538953 ps
CPU time 5.02 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:13 AM UTC 24
Peak memory 211588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=865829265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr
_stress_all_with_rand_reset.865829265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1195035708
Short name T713
Test name
Test status
Simulation time 120045233 ps
CPU time 0.8 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195035708 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1195035708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.1678122120
Short name T711
Test name
Test status
Simulation time 279088247 ps
CPU time 0.73 seconds
Started Aug 27 05:18:06 AM UTC 24
Finished Aug 27 05:18:09 AM UTC 24
Peak memory 210692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678122120 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1678122120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.369976311
Short name T728
Test name
Test status
Simulation time 33000741 ps
CPU time 0.72 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369976311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.369976311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.2577404781
Short name T732
Test name
Test status
Simulation time 64400347 ps
CPU time 0.65 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577404781 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.2577404781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1988470119
Short name T726
Test name
Test status
Simulation time 33712475 ps
CPU time 0.53 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 205944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988470119 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.1988470119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.904708840
Short name T570
Test name
Test status
Simulation time 736937440 ps
CPU time 0.78 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904708840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.904708840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2357591435
Short name T731
Test name
Test status
Simulation time 55505583 ps
CPU time 0.57 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357591435 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2357591435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.1329190610
Short name T725
Test name
Test status
Simulation time 65330379 ps
CPU time 0.55 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329190610 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.1329190610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.1020706523
Short name T585
Test name
Test status
Simulation time 72838128 ps
CPU time 0.64 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020706523 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.1020706523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.1211715476
Short name T724
Test name
Test status
Simulation time 112088476 ps
CPU time 0.64 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:10 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211715476 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.1211715476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.2542487592
Short name T729
Test name
Test status
Simulation time 75779775 ps
CPU time 0.85 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542487592 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2542487592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.2599224913
Short name T727
Test name
Test status
Simulation time 274759420 ps
CPU time 0.67 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599224913 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.2599224913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.4171262194
Short name T709
Test name
Test status
Simulation time 230260964 ps
CPU time 0.79 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171262194 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.4171262194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2359878928
Short name T742
Test name
Test status
Simulation time 932577289 ps
CPU time 2.02 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:12 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359878928 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2359878928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3784245328
Short name T743
Test name
Test status
Simulation time 984343457 ps
CPU time 2.42 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:12 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784245328 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3784245328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.606211294
Short name T676
Test name
Test status
Simulation time 131223023 ps
CPU time 0.74 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606211294 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.606211294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.831211477
Short name T750
Test name
Test status
Simulation time 63458497 ps
CPU time 0.54 seconds
Started Aug 27 05:18:07 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831211477 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.831211477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.3475997507
Short name T744
Test name
Test status
Simulation time 1393473215 ps
CPU time 2.78 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:13 AM UTC 24
Peak memory 209900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475997507 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.3475997507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1035339672
Short name T110
Test name
Test status
Simulation time 3005129451 ps
CPU time 8.69 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:19 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1035339672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg
r_stress_all_with_rand_reset.1035339672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.115274200
Short name T733
Test name
Test status
Simulation time 196579026 ps
CPU time 1.04 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115274200 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.115274200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.1849048101
Short name T668
Test name
Test status
Simulation time 330453703 ps
CPU time 0.94 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849048101 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.1849048101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.3029178448
Short name T737
Test name
Test status
Simulation time 21424656 ps
CPU time 0.7 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029178448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3029178448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.4152877769
Short name T784
Test name
Test status
Simulation time 72281184 ps
CPU time 0.65 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152877769 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.4152877769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1114841917
Short name T754
Test name
Test status
Simulation time 41417481 ps
CPU time 0.54 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114841917 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.1114841917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.699934631
Short name T758
Test name
Test status
Simulation time 113186404 ps
CPU time 0.8 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699934631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.699934631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.2561709420
Short name T782
Test name
Test status
Simulation time 97184416 ps
CPU time 0.66 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561709420 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2561709420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.2586683585
Short name T755
Test name
Test status
Simulation time 55645208 ps
CPU time 0.51 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586683585 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2586683585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.2672446004
Short name T785
Test name
Test status
Simulation time 52106744 ps
CPU time 0.63 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672446004 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.2672446004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.906788655
Short name T736
Test name
Test status
Simulation time 107599151 ps
CPU time 0.84 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906788655 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.906788655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.4084394661
Short name T739
Test name
Test status
Simulation time 104435273 ps
CPU time 0.77 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084394661 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.4084394661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.4229794009
Short name T789
Test name
Test status
Simulation time 107556339 ps
CPU time 0.83 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229794009 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.4229794009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.2783828382
Short name T756
Test name
Test status
Simulation time 132396005 ps
CPU time 0.64 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783828382 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.2783828382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2611162783
Short name T746
Test name
Test status
Simulation time 836674471 ps
CPU time 2.72 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:13 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611162783 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2611162783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2705189438
Short name T807
Test name
Test status
Simulation time 818349975 ps
CPU time 2.82 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705189438 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2705189438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3333022120
Short name T757
Test name
Test status
Simulation time 60030287 ps
CPU time 0.8 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333022120 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3333022120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.885307700
Short name T734
Test name
Test status
Simulation time 52368466 ps
CPU time 0.54 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885307700 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.885307700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.2196768039
Short name T798
Test name
Test status
Simulation time 150217871 ps
CPU time 1.07 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 210752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196768039 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.2196768039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.3939972453
Short name T96
Test name
Test status
Simulation time 5028632224 ps
CPU time 13.95 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:37 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3939972453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmg
r_stress_all_with_rand_reset.3939972453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.4195386724
Short name T738
Test name
Test status
Simulation time 98010921 ps
CPU time 0.59 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195386724 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.4195386724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.1955044892
Short name T741
Test name
Test status
Simulation time 424141212 ps
CPU time 0.99 seconds
Started Aug 27 05:18:09 AM UTC 24
Finished Aug 27 05:18:12 AM UTC 24
Peak memory 210888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955044892 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1955044892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.2874502811
Short name T797
Test name
Test status
Simulation time 22382033 ps
CPU time 0.63 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874502811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2874502811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1792486222
Short name T796
Test name
Test status
Simulation time 83841660 ps
CPU time 0.62 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792486222 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.1792486222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1067757624
Short name T783
Test name
Test status
Simulation time 37384992 ps
CPU time 0.51 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067757624 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.1067757624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.2523420610
Short name T790
Test name
Test status
Simulation time 108909486 ps
CPU time 0.88 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523420610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2523420610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.2833824902
Short name T792
Test name
Test status
Simulation time 46769656 ps
CPU time 0.59 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 205824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833824902 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2833824902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.1735684383
Short name T786
Test name
Test status
Simulation time 51818574 ps
CPU time 0.6 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735684383 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.1735684383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.1548365769
Short name T799
Test name
Test status
Simulation time 54068706 ps
CPU time 0.6 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 209928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548365769 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.1548365769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.2277756168
Short name T781
Test name
Test status
Simulation time 152363033 ps
CPU time 0.72 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277756168 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.2277756168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.2588980737
Short name T795
Test name
Test status
Simulation time 58923598 ps
CPU time 0.84 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588980737 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2588980737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.2867673279
Short name T787
Test name
Test status
Simulation time 157953735 ps
CPU time 0.71 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 219672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867673279 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.2867673279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3153809426
Short name T794
Test name
Test status
Simulation time 98854549 ps
CPU time 0.89 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153809426 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.3153809426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.265818081
Short name T803
Test name
Test status
Simulation time 1223561889 ps
CPU time 2 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:25 AM UTC 24
Peak memory 210476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265818081 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.265818081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.350732582
Short name T804
Test name
Test status
Simulation time 836831245 ps
CPU time 2.56 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:25 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350732582 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.350732582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2923479058
Short name T791
Test name
Test status
Simulation time 75423855 ps
CPU time 0.83 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923479058 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2923479058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.2275659871
Short name T780
Test name
Test status
Simulation time 26983391 ps
CPU time 0.58 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 208140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275659871 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2275659871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.3553982277
Short name T832
Test name
Test status
Simulation time 211425166 ps
CPU time 1.05 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553982277 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.3553982277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.638696827
Short name T849
Test name
Test status
Simulation time 1756750312 ps
CPU time 5.87 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=638696827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr
_stress_all_with_rand_reset.638696827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.1316680722
Short name T793
Test name
Test status
Simulation time 94289608 ps
CPU time 0.76 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316680722 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.1316680722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.1276840409
Short name T801
Test name
Test status
Simulation time 309095004 ps
CPU time 1.12 seconds
Started Aug 27 05:18:11 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276840409 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1276840409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.199169366
Short name T823
Test name
Test status
Simulation time 21829756 ps
CPU time 0.61 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199169366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.199169366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.74933083
Short name T833
Test name
Test status
Simulation time 54507899 ps
CPU time 0.81 seconds
Started Aug 27 05:18:15 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74933083 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.74933083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.18053362
Short name T829
Test name
Test status
Simulation time 27676501 ps
CPU time 0.59 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18053362 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.18053362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.566632877
Short name T753
Test name
Test status
Simulation time 213018109 ps
CPU time 0.75 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566632877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.566632877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.2383572395
Short name T748
Test name
Test status
Simulation time 34391459 ps
CPU time 0.56 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383572395 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.2383572395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.1455169112
Short name T749
Test name
Test status
Simulation time 29571101 ps
CPU time 0.53 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 206024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455169112 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1455169112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.591676986
Short name T752
Test name
Test status
Simulation time 228500350 ps
CPU time 0.58 seconds
Started Aug 27 05:18:15 AM UTC 24
Finished Aug 27 05:18:25 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591676986 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.591676986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.2596604554
Short name T834
Test name
Test status
Simulation time 266271868 ps
CPU time 1.2 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596604554 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.2596604554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.398964478
Short name T830
Test name
Test status
Simulation time 68438664 ps
CPU time 0.98 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398964478 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.398964478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1117209796
Short name T802
Test name
Test status
Simulation time 147377096 ps
CPU time 0.69 seconds
Started Aug 27 05:18:15 AM UTC 24
Finished Aug 27 05:18:25 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117209796 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.1117209796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2852314231
Short name T751
Test name
Test status
Simulation time 93095298 ps
CPU time 0.77 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852314231 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.2852314231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.48644861
Short name T838
Test name
Test status
Simulation time 1193150617 ps
CPU time 2.08 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:28 AM UTC 24
Peak memory 211304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48644861 -ass
ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.48644861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.739182052
Short name T847
Test name
Test status
Simulation time 903963171 ps
CPU time 2.97 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739182052 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.739182052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1981144546
Short name T831
Test name
Test status
Simulation time 116289476 ps
CPU time 0.78 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981144546 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1981144546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.3000040790
Short name T822
Test name
Test status
Simulation time 61463563 ps
CPU time 0.57 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000040790 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3000040790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.2239102559
Short name T768
Test name
Test status
Simulation time 187399361 ps
CPU time 1.14 seconds
Started Aug 27 05:18:16 AM UTC 24
Finished Aug 27 05:18:22 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239102559 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.2239102559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3941594647
Short name T853
Test name
Test status
Simulation time 9057355845 ps
CPU time 14.42 seconds
Started Aug 27 05:18:15 AM UTC 24
Finished Aug 27 05:18:39 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3941594647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmg
r_stress_all_with_rand_reset.3941594647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1014046656
Short name T800
Test name
Test status
Simulation time 189416347 ps
CPU time 0.68 seconds
Started Aug 27 05:18:13 AM UTC 24
Finished Aug 27 05:18:24 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014046656 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1014046656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.922361688
Short name T825
Test name
Test status
Simulation time 71173277 ps
CPU time 0.64 seconds
Started Aug 27 05:18:14 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 209748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922361688 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.922361688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.771616212
Short name T93
Test name
Test status
Simulation time 24034608 ps
CPU time 0.64 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771616212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.771616212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.1428302051
Short name T138
Test name
Test status
Simulation time 70876361 ps
CPU time 0.8 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428302051 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.1428302051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.606114249
Short name T135
Test name
Test status
Simulation time 30389932 ps
CPU time 0.62 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606114249 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.606114249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.1061252430
Short name T128
Test name
Test status
Simulation time 1889959835 ps
CPU time 0.79 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061252430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1061252430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.848969343
Short name T184
Test name
Test status
Simulation time 47110308 ps
CPU time 0.71 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848969343 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.848969343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.161468730
Short name T181
Test name
Test status
Simulation time 35798647 ps
CPU time 0.6 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161468730 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.161468730
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.3683356736
Short name T185
Test name
Test status
Simulation time 144301715 ps
CPU time 0.64 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683356736 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.3683356736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.1271960228
Short name T180
Test name
Test status
Simulation time 162768761 ps
CPU time 0.81 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271960228 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.1271960228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.3645273879
Short name T177
Test name
Test status
Simulation time 103942762 ps
CPU time 0.75 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645273879 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3645273879
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1570379561
Short name T187
Test name
Test status
Simulation time 119419224 ps
CPU time 0.81 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570379561 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1570379561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.2207886547
Short name T31
Test name
Test status
Simulation time 924668166 ps
CPU time 1.35 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:59 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207886547 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2207886547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.4093259713
Short name T183
Test name
Test status
Simulation time 56403065 ps
CPU time 0.82 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093259713 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.4093259713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3753872326
Short name T143
Test name
Test status
Simulation time 847824258 ps
CPU time 1.98 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:59 AM UTC 24
Peak memory 210472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753872326 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3753872326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4111222505
Short name T188
Test name
Test status
Simulation time 906138565 ps
CPU time 2.41 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:16:00 AM UTC 24
Peak memory 211316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111222505 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.4111222505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1994441709
Short name T182
Test name
Test status
Simulation time 75152313 ps
CPU time 0.81 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994441709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1994441709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2126509674
Short name T176
Test name
Test status
Simulation time 60277344 ps
CPU time 0.66 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126509674 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2126509674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.124165610
Short name T211
Test name
Test status
Simulation time 1318961650 ps
CPU time 5.12 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124165610 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.124165610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2714326916
Short name T67
Test name
Test status
Simulation time 12577713277 ps
CPU time 13.83 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:16:11 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2714326916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr
_stress_all_with_rand_reset.2714326916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1055619855
Short name T175
Test name
Test status
Simulation time 197421986 ps
CPU time 0.54 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:57 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055619855 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1055619855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.224647496
Short name T186
Test name
Test status
Simulation time 482815497 ps
CPU time 1.09 seconds
Started Aug 27 05:15:56 AM UTC 24
Finished Aug 27 05:15:58 AM UTC 24
Peak memory 210852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224647496 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.224647496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1662614521
Short name T759
Test name
Test status
Simulation time 32684220 ps
CPU time 0.6 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662614521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1662614521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3975060209
Short name T776
Test name
Test status
Simulation time 55874618 ps
CPU time 0.69 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975060209 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.3975060209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.808226650
Short name T760
Test name
Test status
Simulation time 31447790 ps
CPU time 0.56 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:20 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808226650 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.808226650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.1352706276
Short name T770
Test name
Test status
Simulation time 383595519 ps
CPU time 0.7 seconds
Started Aug 27 05:18:20 AM UTC 24
Finished Aug 27 05:18:22 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352706276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.1352706276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.384457643
Short name T773
Test name
Test status
Simulation time 30418705 ps
CPU time 0.53 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384457643 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.384457643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.1144081114
Short name T761
Test name
Test status
Simulation time 63058588 ps
CPU time 0.49 seconds
Started Aug 27 05:18:19 AM UTC 24
Finished Aug 27 05:18:20 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144081114 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1144081114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.3650443572
Short name T775
Test name
Test status
Simulation time 48948009 ps
CPU time 0.58 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650443572 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.3650443572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2629617587
Short name T764
Test name
Test status
Simulation time 233312575 ps
CPU time 0.89 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629617587 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.2629617587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.1168577335
Short name T767
Test name
Test status
Simulation time 197900562 ps
CPU time 0.66 seconds
Started Aug 27 05:18:16 AM UTC 24
Finished Aug 27 05:18:21 AM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168577335 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1168577335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2027728890
Short name T777
Test name
Test status
Simulation time 149334167 ps
CPU time 0.67 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027728890 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2027728890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.1721153361
Short name T765
Test name
Test status
Simulation time 323376583 ps
CPU time 1 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:21 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721153361 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.1721153361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2192774363
Short name T769
Test name
Test status
Simulation time 833535659 ps
CPU time 1.93 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:22 AM UTC 24
Peak memory 210416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192774363 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2192774363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1704517584
Short name T771
Test name
Test status
Simulation time 869783705 ps
CPU time 2.8 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704517584 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1704517584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.72764342
Short name T763
Test name
Test status
Simulation time 110233088 ps
CPU time 0.77 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72764342 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.72764342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.787061834
Short name T766
Test name
Test status
Simulation time 31738967 ps
CPU time 0.56 seconds
Started Aug 27 05:18:16 AM UTC 24
Finished Aug 27 05:18:21 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787061834 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.787061834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.794568571
Short name T826
Test name
Test status
Simulation time 1006917103 ps
CPU time 4.11 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794568571 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.794568571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.767656634
Short name T837
Test name
Test status
Simulation time 6861519389 ps
CPU time 4.77 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=767656634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr
_stress_all_with_rand_reset.767656634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.3338533831
Short name T774
Test name
Test status
Simulation time 258712923 ps
CPU time 1.12 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 208036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338533831 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.3338533831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.1962421727
Short name T772
Test name
Test status
Simulation time 360631471 ps
CPU time 0.85 seconds
Started Aug 27 05:18:18 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962421727 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.1962421727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.1652835180
Short name T806
Test name
Test status
Simulation time 186703258 ps
CPU time 0.57 seconds
Started Aug 27 05:18:23 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652835180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1652835180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.1978172180
Short name T814
Test name
Test status
Simulation time 137815930 ps
CPU time 0.6 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978172180 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.1978172180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2743107143
Short name T811
Test name
Test status
Simulation time 29111217 ps
CPU time 0.56 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743107143 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.2743107143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.4278928173
Short name T820
Test name
Test status
Simulation time 598306648 ps
CPU time 0.76 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278928173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.4278928173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2193514291
Short name T816
Test name
Test status
Simulation time 57530169 ps
CPU time 0.61 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193514291 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2193514291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.3449058672
Short name T812
Test name
Test status
Simulation time 28589608 ps
CPU time 0.58 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449058672 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3449058672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.3111207728
Short name T818
Test name
Test status
Simulation time 72192710 ps
CPU time 0.63 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111207728 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.3111207728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.2499727180
Short name T808
Test name
Test status
Simulation time 468718636 ps
CPU time 0.9 seconds
Started Aug 27 05:18:23 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499727180 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.2499727180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.3918735606
Short name T805
Test name
Test status
Simulation time 55201700 ps
CPU time 0.73 seconds
Started Aug 27 05:18:23 AM UTC 24
Finished Aug 27 05:18:25 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918735606 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.3918735606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.2614389358
Short name T817
Test name
Test status
Simulation time 171122662 ps
CPU time 0.7 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614389358 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.2614389358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.214136172
Short name T819
Test name
Test status
Simulation time 131385147 ps
CPU time 0.87 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 207956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214136172 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.214136172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3251319956
Short name T835
Test name
Test status
Simulation time 1093273829 ps
CPU time 1.86 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251319956 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3251319956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3972497834
Short name T836
Test name
Test status
Simulation time 926860992 ps
CPU time 1.92 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972497834 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3972497834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852279304
Short name T813
Test name
Test status
Simulation time 186558365 ps
CPU time 0.76 seconds
Started Aug 27 05:18:24 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852279304 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852279304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.4211182816
Short name T779
Test name
Test status
Simulation time 28887574 ps
CPU time 0.58 seconds
Started Aug 27 05:18:21 AM UTC 24
Finished Aug 27 05:18:23 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211182816 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.4211182816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.2314843672
Short name T846
Test name
Test status
Simulation time 3804065999 ps
CPU time 3.26 seconds
Started Aug 27 05:18:25 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314843672 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.2314843672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.176288651
Short name T848
Test name
Test status
Simulation time 1181309262 ps
CPU time 3.56 seconds
Started Aug 27 05:18:25 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=176288651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr
_stress_all_with_rand_reset.176288651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.3740687945
Short name T809
Test name
Test status
Simulation time 107114606 ps
CPU time 0.75 seconds
Started Aug 27 05:18:23 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740687945 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.3740687945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.3241907043
Short name T810
Test name
Test status
Simulation time 210375353 ps
CPU time 0.9 seconds
Started Aug 27 05:18:23 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241907043 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.3241907043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.3895558303
Short name T843
Test name
Test status
Simulation time 30359990 ps
CPU time 0.88 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895558303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3895558303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.547243326
Short name T841
Test name
Test status
Simulation time 74550796 ps
CPU time 0.6 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547243326 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.547243326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2863770253
Short name T839
Test name
Test status
Simulation time 36693792 ps
CPU time 0.56 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:28 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863770253 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.2863770253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.2992517443
Short name T844
Test name
Test status
Simulation time 289155706 ps
CPU time 0.8 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992517443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.2992517443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2922811066
Short name T855
Test name
Test status
Simulation time 88069460 ps
CPU time 0.59 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:45 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922811066 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2922811066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.476312016
Short name T840
Test name
Test status
Simulation time 36725611 ps
CPU time 0.59 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:28 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476312016 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.476312016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.757731284
Short name T870
Test name
Test status
Simulation time 45898295 ps
CPU time 0.67 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757731284 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.757731284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.575572372
Short name T828
Test name
Test status
Simulation time 272011373 ps
CPU time 0.92 seconds
Started Aug 27 05:18:25 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575572372 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.575572372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.2792616891
Short name T824
Test name
Test status
Simulation time 62571201 ps
CPU time 0.79 seconds
Started Aug 27 05:18:25 AM UTC 24
Finished Aug 27 05:18:27 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792616891 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2792616891
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3304699431
Short name T866
Test name
Test status
Simulation time 114847115 ps
CPU time 0.95 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 220056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304699431 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3304699431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1195300908
Short name T845
Test name
Test status
Simulation time 267355374 ps
CPU time 0.9 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195300908 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.1195300908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3711320167
Short name T850
Test name
Test status
Simulation time 1032094213 ps
CPU time 2.13 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:30 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711320167 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3711320167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3630991370
Short name T851
Test name
Test status
Simulation time 1243720644 ps
CPU time 2.08 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:30 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630991370 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3630991370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1174896544
Short name T874
Test name
Test status
Simulation time 67381503 ps
CPU time 0.97 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174896544 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1174896544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.2439596574
Short name T815
Test name
Test status
Simulation time 63975272 ps
CPU time 0.57 seconds
Started Aug 27 05:18:25 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439596574 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2439596574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.1733921279
Short name T900
Test name
Test status
Simulation time 2397428435 ps
CPU time 3.61 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:59 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733921279 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.1733921279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.3073711407
Short name T821
Test name
Test status
Simulation time 38602150 ps
CPU time 0.66 seconds
Started Aug 27 05:18:25 AM UTC 24
Finished Aug 27 05:18:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073711407 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.3073711407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.2345854551
Short name T842
Test name
Test status
Simulation time 236344645 ps
CPU time 0.85 seconds
Started Aug 27 05:18:26 AM UTC 24
Finished Aug 27 05:18:29 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345854551 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.2345854551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2030460509
Short name T876
Test name
Test status
Simulation time 116401659 ps
CPU time 0.65 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030460509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2030460509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2449222817
Short name T916
Test name
Test status
Simulation time 54529218 ps
CPU time 0.74 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449222817 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.2449222817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.442278930
Short name T892
Test name
Test status
Simulation time 29349976 ps
CPU time 0.54 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 206188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442278930 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.442278930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2534873464
Short name T897
Test name
Test status
Simulation time 200949252 ps
CPU time 0.73 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534873464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2534873464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.1828112642
Short name T914
Test name
Test status
Simulation time 55741611 ps
CPU time 0.58 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828112642 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1828112642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.2050219166
Short name T891
Test name
Test status
Simulation time 74627090 ps
CPU time 0.52 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050219166 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2050219166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.1451285099
Short name T893
Test name
Test status
Simulation time 40943455 ps
CPU time 0.62 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451285099 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.1451285099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.3998919499
Short name T881
Test name
Test status
Simulation time 229898240 ps
CPU time 0.83 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998919499 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.3998919499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2397016169
Short name T880
Test name
Test status
Simulation time 105401320 ps
CPU time 0.77 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397016169 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.2397016169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2105622964
Short name T895
Test name
Test status
Simulation time 231593851 ps
CPU time 0.68 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105622964 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2105622964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.2545651992
Short name T896
Test name
Test status
Simulation time 440482557 ps
CPU time 0.82 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 210852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545651992 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.2545651992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.217479895
Short name T898
Test name
Test status
Simulation time 785275271 ps
CPU time 2.65 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217479895 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.217479895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2248459180
Short name T852
Test name
Test status
Simulation time 799048631 ps
CPU time 2.77 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:32 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248459180 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2248459180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1785313519
Short name T857
Test name
Test status
Simulation time 95618092 ps
CPU time 0.72 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785313519 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1785313519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3947778209
Short name T872
Test name
Test status
Simulation time 62689264 ps
CPU time 0.54 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947778209 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3947778209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.2572765809
Short name T917
Test name
Test status
Simulation time 1551312729 ps
CPU time 3.93 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572765809 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2572765809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.1460771527
Short name T921
Test name
Test status
Simulation time 4943108726 ps
CPU time 5.56 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:03 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1460771527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg
r_stress_all_with_rand_reset.1460771527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.4272945090
Short name T875
Test name
Test status
Simulation time 128571168 ps
CPU time 0.68 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272945090 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.4272945090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.1185988036
Short name T879
Test name
Test status
Simulation time 312575018 ps
CPU time 0.92 seconds
Started Aug 27 05:18:27 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185988036 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1185988036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.992991918
Short name T858
Test name
Test status
Simulation time 229638205 ps
CPU time 0.58 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992991918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.992991918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.3064093759
Short name T854
Test name
Test status
Simulation time 101944590 ps
CPU time 0.57 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:45 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064093759 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.3064093759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.226685808
Short name T860
Test name
Test status
Simulation time 30313318 ps
CPU time 0.56 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:51 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226685808 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.226685808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.1121046690
Short name T965
Test name
Test status
Simulation time 401848389 ps
CPU time 0.74 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121046690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1121046690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.1493813127
Short name T956
Test name
Test status
Simulation time 67080760 ps
CPU time 0.54 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493813127 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1493813127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.3550132521
Short name T859
Test name
Test status
Simulation time 29290494 ps
CPU time 0.49 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550132521 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3550132521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.1333253360
Short name T869
Test name
Test status
Simulation time 70425924 ps
CPU time 0.58 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333253360 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.1333253360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.3832642213
Short name T944
Test name
Test status
Simulation time 60253769 ps
CPU time 0.55 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832642213 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.3832642213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.125761970
Short name T915
Test name
Test status
Simulation time 102146377 ps
CPU time 0.7 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125761970 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.125761970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.1278947443
Short name T856
Test name
Test status
Simulation time 167809843 ps
CPU time 0.64 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:46 AM UTC 24
Peak memory 220148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278947443 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1278947443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2271745527
Short name T959
Test name
Test status
Simulation time 79365131 ps
CPU time 0.56 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271745527 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.2271745527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1031328716
Short name T969
Test name
Test status
Simulation time 779651236 ps
CPU time 2.7 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:23 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031328716 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1031328716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4127098554
Short name T863
Test name
Test status
Simulation time 1545193274 ps
CPU time 1.94 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:52 AM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127098554 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4127098554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1910314855
Short name T962
Test name
Test status
Simulation time 207134588 ps
CPU time 0.76 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910314855 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1910314855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.2733512612
Short name T925
Test name
Test status
Simulation time 37527987 ps
CPU time 0.62 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 209932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733512612 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2733512612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.2893833360
Short name T871
Test name
Test status
Simulation time 41512173 ps
CPU time 0.6 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893833360 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.2893833360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.2484033372
Short name T894
Test name
Test status
Simulation time 2303717360 ps
CPU time 2.65 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2484033372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmg
r_stress_all_with_rand_reset.2484033372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.808706213
Short name T861
Test name
Test status
Simulation time 136853981 ps
CPU time 0.71 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:51 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808706213 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.808706213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.3610628596
Short name T862
Test name
Test status
Simulation time 372279507 ps
CPU time 0.92 seconds
Started Aug 27 05:18:29 AM UTC 24
Finished Aug 27 05:18:51 AM UTC 24
Peak memory 208468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610628596 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.3610628596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.2843478310
Short name T882
Test name
Test status
Simulation time 297785475 ps
CPU time 0.74 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843478310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2843478310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.2734180384
Short name T865
Test name
Test status
Simulation time 140611949 ps
CPU time 0.58 seconds
Started Aug 27 05:18:47 AM UTC 24
Finished Aug 27 05:18:55 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734180384 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.2734180384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1664341905
Short name T778
Test name
Test status
Simulation time 27871902 ps
CPU time 0.53 seconds
Started Aug 27 05:18:33 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664341905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.1664341905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.1994108841
Short name T867
Test name
Test status
Simulation time 105157820 ps
CPU time 0.76 seconds
Started Aug 27 05:18:47 AM UTC 24
Finished Aug 27 05:18:55 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994108841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1994108841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.3358635313
Short name T864
Test name
Test status
Simulation time 39730839 ps
CPU time 0.51 seconds
Started Aug 27 05:18:47 AM UTC 24
Finished Aug 27 05:18:55 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358635313 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3358635313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.3978036645
Short name T958
Test name
Test status
Simulation time 42134478 ps
CPU time 0.53 seconds
Started Aug 27 05:18:39 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978036645 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3978036645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.1925797521
Short name T885
Test name
Test status
Simulation time 53570510 ps
CPU time 0.58 seconds
Started Aug 27 05:18:52 AM UTC 24
Finished Aug 27 05:18:57 AM UTC 24
Peak memory 210656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925797521 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.1925797521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.305392706
Short name T878
Test name
Test status
Simulation time 259614554 ps
CPU time 0.91 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305392706 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.305392706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.1501205291
Short name T827
Test name
Test status
Simulation time 69207086 ps
CPU time 0.68 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501205291 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.1501205291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1090105448
Short name T888
Test name
Test status
Simulation time 126355384 ps
CPU time 0.78 seconds
Started Aug 27 05:18:52 AM UTC 24
Finished Aug 27 05:18:57 AM UTC 24
Peak memory 219972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090105448 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1090105448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3033828501
Short name T884
Test name
Test status
Simulation time 190314582 ps
CPU time 0.73 seconds
Started Aug 27 05:18:37 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033828501 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.3033828501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1685335264
Short name T890
Test name
Test status
Simulation time 1256082084 ps
CPU time 1.99 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:57 AM UTC 24
Peak memory 210828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685335264 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1685335264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2142269031
Short name T899
Test name
Test status
Simulation time 903257583 ps
CPU time 2.99 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:58 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142269031 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2142269031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3842440727
Short name T883
Test name
Test status
Simulation time 54434877 ps
CPU time 0.76 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842440727 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3842440727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.100595258
Short name T873
Test name
Test status
Simulation time 29740360 ps
CPU time 0.62 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100595258 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.100595258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.4213601686
Short name T922
Test name
Test status
Simulation time 2276283744 ps
CPU time 6.61 seconds
Started Aug 27 05:18:52 AM UTC 24
Finished Aug 27 05:19:03 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213601686 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.4213601686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2760635185
Short name T918
Test name
Test status
Simulation time 7693311719 ps
CPU time 5.03 seconds
Started Aug 27 05:18:52 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2760635185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg
r_stress_all_with_rand_reset.2760635185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.2610530137
Short name T868
Test name
Test status
Simulation time 39772507 ps
CPU time 0.7 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610530137 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.2610530137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1599215307
Short name T788
Test name
Test status
Simulation time 105287425 ps
CPU time 0.84 seconds
Started Aug 27 05:18:31 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599215307 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1599215307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.4008615332
Short name T928
Test name
Test status
Simulation time 112328622 ps
CPU time 0.55 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:05 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008615332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.4008615332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.1864570121
Short name T934
Test name
Test status
Simulation time 43281922 ps
CPU time 0.68 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864570121 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.1864570121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.2738791887
Short name T929
Test name
Test status
Simulation time 38950780 ps
CPU time 0.51 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:05 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738791887 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.2738791887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.3884427998
Short name T933
Test name
Test status
Simulation time 634320667 ps
CPU time 0.71 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884427998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3884427998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.2964127831
Short name T931
Test name
Test status
Simulation time 69998031 ps
CPU time 0.53 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964127831 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2964127831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.197382159
Short name T927
Test name
Test status
Simulation time 53189851 ps
CPU time 0.49 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197382159 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.197382159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.14794530
Short name T974
Test name
Test status
Simulation time 73749959 ps
CPU time 0.56 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14794530 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.14794530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.1134361496
Short name T877
Test name
Test status
Simulation time 103465761 ps
CPU time 0.77 seconds
Started Aug 27 05:18:53 AM UTC 24
Finished Aug 27 05:18:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134361496 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.1134361496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.1445986143
Short name T887
Test name
Test status
Simulation time 80060088 ps
CPU time 0.63 seconds
Started Aug 27 05:18:52 AM UTC 24
Finished Aug 27 05:18:57 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445986143 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1445986143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.2430602316
Short name T935
Test name
Test status
Simulation time 157029475 ps
CPU time 0.68 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430602316 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2430602316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.798181448
Short name T930
Test name
Test status
Simulation time 56367888 ps
CPU time 0.6 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798181448 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.798181448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.836662984
Short name T937
Test name
Test status
Simulation time 1104685910 ps
CPU time 1.7 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836662984 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.836662984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3067641832
Short name T939
Test name
Test status
Simulation time 1239119586 ps
CPU time 2.01 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:07 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067641832 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3067641832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3987608899
Short name T932
Test name
Test status
Simulation time 295966033 ps
CPU time 0.75 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987608899 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3987608899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.60809052
Short name T886
Test name
Test status
Simulation time 179594348 ps
CPU time 0.54 seconds
Started Aug 27 05:18:52 AM UTC 24
Finished Aug 27 05:18:57 AM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60809052 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.60809052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3952376472
Short name T966
Test name
Test status
Simulation time 84960669 ps
CPU time 0.83 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:22 AM UTC 24
Peak memory 210976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952376472 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.3952376472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.2575197698
Short name T940
Test name
Test status
Simulation time 10326143761 ps
CPU time 11.78 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:17 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2575197698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg
r_stress_all_with_rand_reset.2575197698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.259430736
Short name T936
Test name
Test status
Simulation time 265297455 ps
CPU time 1.16 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259430736 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.259430736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.997349824
Short name T926
Test name
Test status
Simulation time 105353126 ps
CPU time 0.77 seconds
Started Aug 27 05:18:57 AM UTC 24
Finished Aug 27 05:19:05 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997349824 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.997349824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.4135034794
Short name T906
Test name
Test status
Simulation time 36696158 ps
CPU time 0.86 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135034794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.4135034794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1183294154
Short name T912
Test name
Test status
Simulation time 68199615 ps
CPU time 0.73 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183294154 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.1183294154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2732246379
Short name T902
Test name
Test status
Simulation time 30898098 ps
CPU time 0.59 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:00 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732246379 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.2732246379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.4027609422
Short name T913
Test name
Test status
Simulation time 109464580 ps
CPU time 0.82 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027609422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.4027609422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3858225965
Short name T904
Test name
Test status
Simulation time 51691560 ps
CPU time 0.57 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858225965 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3858225965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.2843607251
Short name T903
Test name
Test status
Simulation time 45547781 ps
CPU time 0.57 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843607251 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2843607251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.1395338510
Short name T908
Test name
Test status
Simulation time 125183987 ps
CPU time 0.57 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395338510 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.1395338510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.3941957222
Short name T901
Test name
Test status
Simulation time 124842221 ps
CPU time 0.66 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:00 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941957222 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.3941957222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1950331632
Short name T986
Test name
Test status
Simulation time 63048072 ps
CPU time 0.58 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 209932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950331632 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1950331632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.3097293211
Short name T911
Test name
Test status
Simulation time 538845927 ps
CPU time 0.67 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097293211 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3097293211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.127029064
Short name T905
Test name
Test status
Simulation time 162408836 ps
CPU time 0.66 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127029064 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.127029064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2765863001
Short name T919
Test name
Test status
Simulation time 907883619 ps
CPU time 2.07 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:02 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765863001 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2765863001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4181593379
Short name T920
Test name
Test status
Simulation time 835028754 ps
CPU time 2.76 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:03 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181593379 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4181593379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1929802634
Short name T907
Test name
Test status
Simulation time 140365658 ps
CPU time 0.77 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929802634 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1929802634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.4258044874
Short name T963
Test name
Test status
Simulation time 115208668 ps
CPU time 0.58 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258044874 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.4258044874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.1342153605
Short name T923
Test name
Test status
Simulation time 983168658 ps
CPU time 3.27 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:03 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342153605 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.1342153605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.3027850510
Short name T924
Test name
Test status
Simulation time 2288307589 ps
CPU time 4.18 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:04 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3027850510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmg
r_stress_all_with_rand_reset.3027850510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.4171194678
Short name T910
Test name
Test status
Simulation time 152490259 ps
CPU time 0.95 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171194678 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.4171194678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.1621249892
Short name T909
Test name
Test status
Simulation time 293437208 ps
CPU time 0.83 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:01 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621249892 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1621249892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.967115340
Short name T941
Test name
Test status
Simulation time 52575327 ps
CPU time 0.66 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967115340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.967115340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.1840673724
Short name T957
Test name
Test status
Simulation time 66463965 ps
CPU time 0.75 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840673724 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.1840673724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.531594381
Short name T949
Test name
Test status
Simulation time 30402111 ps
CPU time 0.62 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531594381 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.531594381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.2458057089
Short name T953
Test name
Test status
Simulation time 417248609 ps
CPU time 0.72 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458057089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2458057089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.4095118660
Short name T943
Test name
Test status
Simulation time 45788213 ps
CPU time 0.56 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095118660 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.4095118660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2270631948
Short name T889
Test name
Test status
Simulation time 60669942 ps
CPU time 0.56 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270631948 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2270631948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.3354459308
Short name T954
Test name
Test status
Simulation time 130777364 ps
CPU time 0.59 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 210476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354459308 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid.3354459308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.848354328
Short name T973
Test name
Test status
Simulation time 168902746 ps
CPU time 0.84 seconds
Started Aug 27 05:19:00 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848354328 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.848354328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.595981185
Short name T971
Test name
Test status
Simulation time 99902274 ps
CPU time 0.79 seconds
Started Aug 27 05:19:00 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 210064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595981185 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.595981185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.4109621326
Short name T960
Test name
Test status
Simulation time 110224808 ps
CPU time 0.82 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 219868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109621326 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.4109621326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3992331818
Short name T951
Test name
Test status
Simulation time 267384631 ps
CPU time 0.85 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 209260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992331818 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.3992331818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2598749135
Short name T967
Test name
Test status
Simulation time 837178666 ps
CPU time 2.02 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:22 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598749135 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2598749135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3209863124
Short name T968
Test name
Test status
Simulation time 919711586 ps
CPU time 2.13 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:22 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209863124 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3209863124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1858226228
Short name T950
Test name
Test status
Simulation time 138261289 ps
CPU time 0.77 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858226228 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1858226228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.1367901997
Short name T946
Test name
Test status
Simulation time 36368388 ps
CPU time 0.56 seconds
Started Aug 27 05:18:59 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367901997 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1367901997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1627872744
Short name T970
Test name
Test status
Simulation time 872147155 ps
CPU time 3.31 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:24 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627872744 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1627872744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.2958583923
Short name T978
Test name
Test status
Simulation time 6413868544 ps
CPU time 7.57 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:28 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2958583923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmg
r_stress_all_with_rand_reset.2958583923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.932935363
Short name T972
Test name
Test status
Simulation time 145956548 ps
CPU time 0.8 seconds
Started Aug 27 05:19:00 AM UTC 24
Finished Aug 27 05:19:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932935363 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.932935363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1769073871
Short name T964
Test name
Test status
Simulation time 402324732 ps
CPU time 1.29 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769073871 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.1769073871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.590078818
Short name T983
Test name
Test status
Simulation time 22599117 ps
CPU time 0.79 seconds
Started Aug 27 05:19:04 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590078818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.590078818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.525229448
Short name T948
Test name
Test status
Simulation time 74462519 ps
CPU time 0.57 seconds
Started Aug 27 05:19:06 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525229448 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.525229448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.782818934
Short name T942
Test name
Test status
Simulation time 35898233 ps
CPU time 0.51 seconds
Started Aug 27 05:19:06 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782818934 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.782818934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.1960459659
Short name T947
Test name
Test status
Simulation time 388708999 ps
CPU time 0.71 seconds
Started Aug 27 05:19:06 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960459659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1960459659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1031773078
Short name T945
Test name
Test status
Simulation time 60862126 ps
CPU time 0.49 seconds
Started Aug 27 05:19:06 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031773078 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.1031773078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.2069241137
Short name T938
Test name
Test status
Simulation time 36921109 ps
CPU time 0.58 seconds
Started Aug 27 05:19:06 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069241137 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2069241137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.4132415048
Short name T975
Test name
Test status
Simulation time 174387627 ps
CPU time 0.56 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132415048 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.4132415048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.276520936
Short name T980
Test name
Test status
Simulation time 128275598 ps
CPU time 0.69 seconds
Started Aug 27 05:19:03 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 209456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276520936 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.276520936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2622103591
Short name T961
Test name
Test status
Simulation time 42746382 ps
CPU time 0.75 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622103591 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2622103591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1657824018
Short name T977
Test name
Test status
Simulation time 125405645 ps
CPU time 0.69 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657824018 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1657824018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3289711680
Short name T952
Test name
Test status
Simulation time 243401536 ps
CPU time 1.03 seconds
Started Aug 27 05:19:06 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289711680 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.3289711680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1424082788
Short name T985
Test name
Test status
Simulation time 750674921 ps
CPU time 2.62 seconds
Started Aug 27 05:19:05 AM UTC 24
Finished Aug 27 05:19:59 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424082788 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1424082788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.79361885
Short name T984
Test name
Test status
Simulation time 53685550 ps
CPU time 0.85 seconds
Started Aug 27 05:19:05 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79361885 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.79361885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.982457162
Short name T955
Test name
Test status
Simulation time 40738657 ps
CPU time 0.56 seconds
Started Aug 27 05:19:02 AM UTC 24
Finished Aug 27 05:19:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982457162 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.982457162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2866761229
Short name T982
Test name
Test status
Simulation time 213861276 ps
CPU time 0.86 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 210696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866761229 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2866761229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.1173638897
Short name T979
Test name
Test status
Simulation time 5689021264 ps
CPU time 10.71 seconds
Started Aug 27 05:19:07 AM UTC 24
Finished Aug 27 05:19:36 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1173638897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmg
r_stress_all_with_rand_reset.1173638897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.800568990
Short name T976
Test name
Test status
Simulation time 426083847 ps
CPU time 0.71 seconds
Started Aug 27 05:19:03 AM UTC 24
Finished Aug 27 05:19:26 AM UTC 24
Peak memory 207856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800568990 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.800568990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.2331436120
Short name T981
Test name
Test status
Simulation time 150833073 ps
CPU time 0.65 seconds
Started Aug 27 05:19:04 AM UTC 24
Finished Aug 27 05:19:57 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331436120 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.2331436120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.409995859
Short name T71
Test name
Test status
Simulation time 71208863 ps
CPU time 0.78 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409995859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.409995859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.4009259716
Short name T139
Test name
Test status
Simulation time 49558431 ps
CPU time 0.88 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009259716 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.4009259716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1386652037
Short name T193
Test name
Test status
Simulation time 57337056 ps
CPU time 0.66 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386652037 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.1386652037
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.564440883
Short name T129
Test name
Test status
Simulation time 116455427 ps
CPU time 0.97 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564440883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.564440883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.2809589776
Short name T195
Test name
Test status
Simulation time 57000890 ps
CPU time 0.64 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 206020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809589776 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2809589776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3083202640
Short name T190
Test name
Test status
Simulation time 51496887 ps
CPU time 0.59 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083202640 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3083202640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.1812365062
Short name T198
Test name
Test status
Simulation time 46129159 ps
CPU time 0.69 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812365062 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.1812365062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2449284859
Short name T192
Test name
Test status
Simulation time 286165547 ps
CPU time 0.83 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449284859 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.2449284859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3493120033
Short name T194
Test name
Test status
Simulation time 68687520 ps
CPU time 0.97 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493120033 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3493120033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3236708263
Short name T201
Test name
Test status
Simulation time 182867881 ps
CPU time 0.77 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236708263 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3236708263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3770392714
Short name T199
Test name
Test status
Simulation time 163558779 ps
CPU time 0.93 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770392714 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.3770392714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.978510963
Short name T140
Test name
Test status
Simulation time 971263959 ps
CPU time 1.88 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:02 AM UTC 24
Peak memory 210900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978510963 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.978510963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3374783274
Short name T141
Test name
Test status
Simulation time 1236956898 ps
CPU time 1.97 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:02 AM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374783274 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3374783274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3524425782
Short name T196
Test name
Test status
Simulation time 52731763 ps
CPU time 0.86 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524425782 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3524425782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1553272317
Short name T189
Test name
Test status
Simulation time 59716227 ps
CPU time 0.59 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553272317 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1553272317
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3094088104
Short name T214
Test name
Test status
Simulation time 667162888 ps
CPU time 2.35 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094088104 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.3094088104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.3313162787
Short name T50
Test name
Test status
Simulation time 1722265871 ps
CPU time 6.23 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3313162787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr
_stress_all_with_rand_reset.3313162787
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.175005400
Short name T191
Test name
Test status
Simulation time 107491329 ps
CPU time 0.79 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175005400 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.175005400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3456375566
Short name T205
Test name
Test status
Simulation time 303429313 ps
CPU time 1.32 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 210548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456375566 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3456375566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3201560555
Short name T72
Test name
Test status
Simulation time 31732011 ps
CPU time 0.76 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201560555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3201560555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3405022171
Short name T145
Test name
Test status
Simulation time 58211663 ps
CPU time 0.8 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405022171 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.3405022171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2546901639
Short name T130
Test name
Test status
Simulation time 76348194 ps
CPU time 0.5 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546901639 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.2546901639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1987768574
Short name T131
Test name
Test status
Simulation time 388750698 ps
CPU time 0.95 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987768574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.1987768574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3590718176
Short name T210
Test name
Test status
Simulation time 52015405 ps
CPU time 0.67 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590718176 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3590718176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3950154426
Short name T209
Test name
Test status
Simulation time 59063636 ps
CPU time 0.74 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950154426 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3950154426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.2979626653
Short name T212
Test name
Test status
Simulation time 75615647 ps
CPU time 0.72 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979626653 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.2979626653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.13456061
Short name T200
Test name
Test status
Simulation time 206999586 ps
CPU time 0.72 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13456061 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.13456061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2816290641
Short name T204
Test name
Test status
Simulation time 151550889 ps
CPU time 0.77 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816290641 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.2816290641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1671224629
Short name T215
Test name
Test status
Simulation time 167296971 ps
CPU time 0.72 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671224629 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1671224629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1447508036
Short name T208
Test name
Test status
Simulation time 182837928 ps
CPU time 0.76 seconds
Started Aug 27 05:16:01 AM UTC 24
Finished Aug 27 05:16:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447508036 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.1447508036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4251059593
Short name T216
Test name
Test status
Simulation time 883460705 ps
CPU time 2.82 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251059593 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.4251059593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1800441668
Short name T213
Test name
Test status
Simulation time 1312772253 ps
CPU time 2.17 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:03 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800441668 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1800441668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.4187961517
Short name T207
Test name
Test status
Simulation time 83638579 ps
CPU time 0.91 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187961517 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.4187961517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.3319604151
Short name T202
Test name
Test status
Simulation time 32978293 ps
CPU time 0.73 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319604151 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3319604151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.920409399
Short name T262
Test name
Test status
Simulation time 1703971465 ps
CPU time 5.8 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:10 AM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920409399 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.920409399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1965075985
Short name T119
Test name
Test status
Simulation time 6309849464 ps
CPU time 8.69 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1965075985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr
_stress_all_with_rand_reset.1965075985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.55026296
Short name T203
Test name
Test status
Simulation time 197960759 ps
CPU time 0.79 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55026296 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.55026296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.380291780
Short name T206
Test name
Test status
Simulation time 327943970 ps
CPU time 0.98 seconds
Started Aug 27 05:15:59 AM UTC 24
Finished Aug 27 05:16:01 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380291780 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.380291780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1297671988
Short name T230
Test name
Test status
Simulation time 30016027 ps
CPU time 0.88 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297671988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1297671988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3416818010
Short name T232
Test name
Test status
Simulation time 59498813 ps
CPU time 0.82 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416818010 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.3416818010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.140539878
Short name T222
Test name
Test status
Simulation time 39598318 ps
CPU time 0.58 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140539878 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.140539878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2580251663
Short name T132
Test name
Test status
Simulation time 214489242 ps
CPU time 0.77 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580251663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2580251663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.4054479321
Short name T227
Test name
Test status
Simulation time 51124868 ps
CPU time 0.58 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054479321 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.4054479321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2011724655
Short name T221
Test name
Test status
Simulation time 60490789 ps
CPU time 0.54 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011724655 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2011724655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3175655706
Short name T231
Test name
Test status
Simulation time 99633732 ps
CPU time 0.71 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175655706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.3175655706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1635066535
Short name T219
Test name
Test status
Simulation time 139759068 ps
CPU time 0.7 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635066535 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.1635066535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.166833627
Short name T220
Test name
Test status
Simulation time 131828973 ps
CPU time 0.71 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166833627 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.166833627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3928237151
Short name T228
Test name
Test status
Simulation time 105789737 ps
CPU time 0.86 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928237151 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3928237151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2949417851
Short name T226
Test name
Test status
Simulation time 114038397 ps
CPU time 0.62 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949417851 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.2949417851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2924150670
Short name T238
Test name
Test status
Simulation time 1203829916 ps
CPU time 1.83 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924150670 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2924150670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590920503
Short name T241
Test name
Test status
Simulation time 731207209 ps
CPU time 2.78 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590920503 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3590920503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3497899593
Short name T223
Test name
Test status
Simulation time 69420696 ps
CPU time 0.74 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497899593 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3497899593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.888580291
Short name T218
Test name
Test status
Simulation time 78742053 ps
CPU time 0.56 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888580291 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.888580291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3925899678
Short name T224
Test name
Test status
Simulation time 1561300608 ps
CPU time 2.32 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925899678 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.3925899678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3160439975
Short name T53
Test name
Test status
Simulation time 1831549833 ps
CPU time 3.05 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3160439975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr
_stress_all_with_rand_reset.3160439975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4199717987
Short name T225
Test name
Test status
Simulation time 464414714 ps
CPU time 0.86 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199717987 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.4199717987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3407636608
Short name T229
Test name
Test status
Simulation time 130054890 ps
CPU time 0.89 seconds
Started Aug 27 05:16:03 AM UTC 24
Finished Aug 27 05:16:05 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407636608 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.3407636608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.697546867
Short name T92
Test name
Test status
Simulation time 17368442 ps
CPU time 0.6 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697546867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.697546867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.1436421448
Short name T242
Test name
Test status
Simulation time 67729903 ps
CPU time 0.64 seconds
Started Aug 27 05:16:06 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436421448 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.1436421448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.188726799
Short name T234
Test name
Test status
Simulation time 32745302 ps
CPU time 0.6 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188726799 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.188726799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2499732118
Short name T246
Test name
Test status
Simulation time 111137935 ps
CPU time 0.82 seconds
Started Aug 27 05:16:06 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499732118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2499732118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.419378123
Short name T20
Test name
Test status
Simulation time 38726508 ps
CPU time 0.53 seconds
Started Aug 27 05:16:06 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419378123 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.419378123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1921885280
Short name T197
Test name
Test status
Simulation time 68315661 ps
CPU time 0.6 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921885280 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1921885280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3225438646
Short name T243
Test name
Test status
Simulation time 81867451 ps
CPU time 0.61 seconds
Started Aug 27 05:16:06 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225438646 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.3225438646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.604321127
Short name T237
Test name
Test status
Simulation time 174346405 ps
CPU time 1 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604321127 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.604321127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.429097303
Short name T178
Test name
Test status
Simulation time 26604974 ps
CPU time 0.66 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429097303 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.429097303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3463316385
Short name T244
Test name
Test status
Simulation time 125988637 ps
CPU time 0.79 seconds
Started Aug 27 05:16:06 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463316385 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.3463316385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3928029457
Short name T236
Test name
Test status
Simulation time 216870728 ps
CPU time 0.76 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928029457 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.3928029457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3938852364
Short name T239
Test name
Test status
Simulation time 954109630 ps
CPU time 1.8 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938852364 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3938852364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1738459650
Short name T240
Test name
Test status
Simulation time 904503182 ps
CPU time 2.16 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738459650 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1738459650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174196275
Short name T235
Test name
Test status
Simulation time 147723819 ps
CPU time 0.81 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174196275 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174196275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.3641481434
Short name T179
Test name
Test status
Simulation time 42934256 ps
CPU time 0.64 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641481434 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.3641481434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3809913370
Short name T287
Test name
Test status
Simulation time 1483860112 ps
CPU time 5.04 seconds
Started Aug 27 05:16:06 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809913370 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.3809913370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.3724489155
Short name T217
Test name
Test status
Simulation time 186522686 ps
CPU time 0.95 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724489155 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.3724489155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.3274334804
Short name T233
Test name
Test status
Simulation time 193382838 ps
CPU time 0.77 seconds
Started Aug 27 05:16:04 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274334804 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.3274334804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2263885173
Short name T249
Test name
Test status
Simulation time 68845996 ps
CPU time 0.78 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263885173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2263885173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3456462969
Short name T148
Test name
Test status
Simulation time 59289383 ps
CPU time 0.77 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456462969 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.3456462969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.711841727
Short name T248
Test name
Test status
Simulation time 29366746 ps
CPU time 0.64 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711841727 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.711841727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.791942158
Short name T258
Test name
Test status
Simulation time 207945008 ps
CPU time 0.82 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791942158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.791942158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.731223990
Short name T254
Test name
Test status
Simulation time 63022188 ps
CPU time 0.58 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 205988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731223990 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.731223990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.965480587
Short name T251
Test name
Test status
Simulation time 84666491 ps
CPU time 0.64 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 206188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965480587 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.965480587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3439426178
Short name T256
Test name
Test status
Simulation time 65723216 ps
CPU time 0.62 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439426178 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.3439426178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1690987889
Short name T253
Test name
Test status
Simulation time 188963976 ps
CPU time 1 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690987889 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.1690987889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3255298316
Short name T250
Test name
Test status
Simulation time 73889127 ps
CPU time 0.88 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255298316 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3255298316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.220431121
Short name T260
Test name
Test status
Simulation time 93722419 ps
CPU time 0.9 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220431121 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.220431121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3647774825
Short name T259
Test name
Test status
Simulation time 390910054 ps
CPU time 0.98 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647774825 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.3647774825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.59688432
Short name T261
Test name
Test status
Simulation time 1602976667 ps
CPU time 1.84 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:10 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59688432 -ass
ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_
mubi.59688432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4193073475
Short name T263
Test name
Test status
Simulation time 868682702 ps
CPU time 3.12 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:11 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193073475 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.4193073475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3427286621
Short name T257
Test name
Test status
Simulation time 53449119 ps
CPU time 0.85 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427286621 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3427286621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1768457243
Short name T247
Test name
Test status
Simulation time 28909004 ps
CPU time 0.69 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:08 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768457243 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.1768457243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1998020062
Short name T296
Test name
Test status
Simulation time 460191430 ps
CPU time 2.24 seconds
Started Aug 27 05:16:10 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998020062 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.1998020062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3103692958
Short name T54
Test name
Test status
Simulation time 3999611219 ps
CPU time 12.1 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:20 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3103692958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr
_stress_all_with_rand_reset.3103692958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1395506486
Short name T252
Test name
Test status
Simulation time 229609858 ps
CPU time 0.91 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395506486 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1395506486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1157883864
Short name T255
Test name
Test status
Simulation time 373432687 ps
CPU time 0.88 seconds
Started Aug 27 05:16:07 AM UTC 24
Finished Aug 27 05:16:09 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157883864 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.1157883864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%