| T801 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.656813761 |
|
|
Sep 01 08:27:34 PM UTC 24 |
Sep 01 08:27:49 PM UTC 24 |
998853260 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2080517496 |
|
|
Sep 01 08:27:38 PM UTC 24 |
Sep 01 08:27:49 PM UTC 24 |
1031422127 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.2263046682 |
|
|
Sep 01 08:27:08 PM UTC 24 |
Sep 01 08:27:49 PM UTC 24 |
8133425152 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2794658596 |
|
|
Sep 01 08:27:35 PM UTC 24 |
Sep 01 08:27:50 PM UTC 24 |
846016860 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.2236529893 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:51 PM UTC 24 |
43632972 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.342466313 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
76107956 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3609557760 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
38082792 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.1474974573 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
31501805 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2557947672 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
64955663 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3339257176 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
47221351 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.873294306 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
143243499 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.1260137731 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
111664596 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3447979169 |
|
|
Sep 01 08:27:48 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
68254258 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.772920478 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
48810256 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.3292457999 |
|
|
Sep 01 08:27:58 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
231864591 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.790497213 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
392196474 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4247407320 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
191609785 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2188066808 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
32156007 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3542900644 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
30725967 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.3056999473 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
89409975 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.442807182 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
91618703 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.4187306418 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
85699328 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2523514344 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
67855305 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.393459595 |
|
|
Sep 01 08:27:35 PM UTC 24 |
Sep 01 08:27:52 PM UTC 24 |
5287389133 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2323927326 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:53 PM UTC 24 |
909126655 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3164362974 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:27:53 PM UTC 24 |
1044460385 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3979971038 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:53 PM UTC 24 |
969864794 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2648809969 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:54 PM UTC 24 |
890127399 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.567974265 |
|
|
Sep 01 08:27:35 PM UTC 24 |
Sep 01 08:27:54 PM UTC 24 |
1978559747 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.3340274038 |
|
|
Sep 01 08:27:55 PM UTC 24 |
Sep 01 08:27:57 PM UTC 24 |
54505284 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2646202178 |
|
|
Sep 01 08:27:54 PM UTC 24 |
Sep 01 08:27:57 PM UTC 24 |
89744227 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2270845264 |
|
|
Sep 01 08:27:54 PM UTC 24 |
Sep 01 08:27:57 PM UTC 24 |
161053239 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.1031055859 |
|
|
Sep 01 08:27:58 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
57434579 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.4050928978 |
|
|
Sep 01 08:27:56 PM UTC 24 |
Sep 01 08:27:57 PM UTC 24 |
68187050 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.559867722 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
45869316 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.71633932 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
66054171 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.2625191340 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
310233378 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.3648021885 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
68873470 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2245980377 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
135124034 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.2204922425 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
52363358 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.1271686843 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
75724512 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.1614064448 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
170037330 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1752549368 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
111502883 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1915133053 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:58 PM UTC 24 |
63293306 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.942790567 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:27:59 PM UTC 24 |
1088907141 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1448546433 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:00 PM UTC 24 |
831713137 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.2407133146 |
|
|
Sep 01 08:27:56 PM UTC 24 |
Sep 01 08:28:01 PM UTC 24 |
3167956781 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.88997730 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:01 PM UTC 24 |
2599504968 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.1346796478 |
|
|
Sep 01 08:27:06 PM UTC 24 |
Sep 01 08:28:01 PM UTC 24 |
20606818 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3149131346 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
42108054 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.2977348878 |
|
|
Sep 01 08:27:17 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
109282230 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.3523145127 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
23098853 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.4237542381 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
38450779 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.3869967832 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
34846589 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.3201085683 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
109875280 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3706141441 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
86873185 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.1792623745 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
75131020 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.2626870558 |
|
|
Sep 01 08:28:00 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
41810533 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2320767877 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
148739348 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3630010802 |
|
|
Sep 01 08:27:51 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
130860704 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2762945831 |
|
|
Sep 01 08:27:51 PM UTC 24 |
Sep 01 08:28:02 PM UTC 24 |
65318258 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.2752984085 |
|
|
Sep 01 08:28:00 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
106714187 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.2301772400 |
|
|
Sep 01 08:27:50 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
200289513 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2026120519 |
|
|
Sep 01 08:27:48 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
418614866 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.1229340988 |
|
|
Sep 01 08:27:51 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
53638537 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3059328177 |
|
|
Sep 01 08:27:48 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
41960728 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.368613221 |
|
|
Sep 01 08:27:48 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
76051554 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.3860546201 |
|
|
Sep 01 08:27:48 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
55197378 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2223413881 |
|
|
Sep 01 08:27:48 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
31502549 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.1750816838 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
67169014 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2719513404 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
56986375 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.1570119721 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
51622353 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1902904561 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
7707324436 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.2172339925 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
51206080 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.3140432361 |
|
|
Sep 01 08:27:58 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
148465601 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2428351698 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
101977084 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.4164129607 |
|
|
Sep 01 08:27:58 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
201696047 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3666800515 |
|
|
Sep 01 08:27:55 PM UTC 24 |
Sep 01 08:28:03 PM UTC 24 |
2123658318 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1157885092 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:04 PM UTC 24 |
899461779 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.1678030350 |
|
|
Sep 01 08:27:52 PM UTC 24 |
Sep 01 08:28:04 PM UTC 24 |
43828872 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.146029377 |
|
|
Sep 01 08:27:59 PM UTC 24 |
Sep 01 08:28:04 PM UTC 24 |
868785421 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.499091104 |
|
|
Sep 01 08:27:47 PM UTC 24 |
Sep 01 08:28:04 PM UTC 24 |
1240146418 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.466424778 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:28:04 PM UTC 24 |
2372618523 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.724920517 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:04 PM UTC 24 |
32013542 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4044873564 |
|
|
Sep 01 08:27:47 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
772293398 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.821893063 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
32150629 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1204861822 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
25021913 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.6579912 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
30122707 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.3069464458 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
336122213 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.4174813618 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
327556090 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1319201266 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
54346409 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.338637864 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
168840076 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2027951589 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:05 PM UTC 24 |
267070266 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.233240508 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:06 PM UTC 24 |
1182091097 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1331015930 |
|
|
Sep 01 08:28:03 PM UTC 24 |
Sep 01 08:28:06 PM UTC 24 |
845366686 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.396340612 |
|
|
Sep 01 08:27:38 PM UTC 24 |
Sep 01 08:28:07 PM UTC 24 |
2689732894 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.3910454888 |
|
|
Sep 01 08:27:44 PM UTC 24 |
Sep 01 08:28:07 PM UTC 24 |
2445022881 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2321988597 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
38056692 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.3298503456 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
31681390 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.1660636922 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
39191554 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.3012662982 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
54692623 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.1151314090 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
50835086 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1916643608 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
120789642 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2076915174 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
150456615 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.269169177 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
108774178 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.2620406659 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
106383294 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.23386602 |
|
|
Sep 01 08:28:02 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
1446623215 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.3061066927 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
54654837 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.657632868 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
64923557 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3717904314 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:08 PM UTC 24 |
279547386 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.408518409 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:09 PM UTC 24 |
244826825 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1156210546 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:09 PM UTC 24 |
1292242132 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.488507749 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:10 PM UTC 24 |
1942787659 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.791268673 |
|
|
Sep 01 08:28:01 PM UTC 24 |
Sep 01 08:28:11 PM UTC 24 |
7010607051 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.1946330854 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
66669259 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.3117040399 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
125193272 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.418329253 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
68754038 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.2678544961 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
42771195 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.3785307815 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
158704044 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1948555524 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
191601101 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.2865256861 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:12 PM UTC 24 |
64178547 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.456321522 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
135551194 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2448737392 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
215499926 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.4096538565 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
62466530 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.2545137574 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
414693246 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.217979567 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
72550216 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.2659263364 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
40668445 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.4270077585 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
208944727 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1244067485 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:15 PM UTC 24 |
895076517 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.2511779767 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
545575519 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.2449318833 |
|
|
Sep 01 08:28:08 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
27678499 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1397241709 |
|
|
Sep 01 08:28:10 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
154830142 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.2657243092 |
|
|
Sep 01 08:28:08 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
129349133 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3772347653 |
|
|
Sep 01 08:28:08 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
23817361 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.184073846 |
|
|
Sep 01 08:28:08 PM UTC 24 |
Sep 01 08:28:13 PM UTC 24 |
201311384 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.887572104 |
|
|
Sep 01 08:28:11 PM UTC 24 |
Sep 01 08:28:14 PM UTC 24 |
31042751 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.135980393 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:14 PM UTC 24 |
1700990564 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.427737801 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:14 PM UTC 24 |
53390337 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.3829149924 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:14 PM UTC 24 |
73492804 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2463324197 |
|
|
Sep 01 08:28:13 PM UTC 24 |
Sep 01 08:28:15 PM UTC 24 |
141948531 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.1904204939 |
|
|
Sep 01 08:28:13 PM UTC 24 |
Sep 01 08:28:15 PM UTC 24 |
49289742 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.2004309617 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:15 PM UTC 24 |
111763394 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.91020817 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:15 PM UTC 24 |
795221810 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2426513934 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
120546093 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.463978050 |
|
|
Sep 01 08:28:15 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
86084367 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1341194073 |
|
|
Sep 01 08:28:15 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
86821971 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.2105628650 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
218365933 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.570966236 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
138620548 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.771909287 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
186399310 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.3639213497 |
|
|
Sep 01 08:28:15 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
51958238 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.2142326287 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
1382867487 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.398838887 |
|
|
Sep 01 08:28:16 PM UTC 24 |
Sep 01 08:28:17 PM UTC 24 |
71802358 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3222575846 |
|
|
Sep 01 08:28:15 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
107455341 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1675677887 |
|
|
Sep 01 08:28:15 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
164340269 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.299141906 |
|
|
Sep 01 08:28:13 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
73048459 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.1732851142 |
|
|
Sep 01 08:28:13 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
118592441 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1812741304 |
|
|
Sep 01 08:28:13 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
386325945 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2541005098 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
39110831 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1016394026 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
897763516 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.26930361 |
|
|
Sep 01 08:28:13 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
109709865 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.2553740766 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
23717915 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3992215555 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
47962771 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.4115636579 |
|
|
Sep 01 08:27:46 PM UTC 24 |
Sep 01 08:28:18 PM UTC 24 |
23762505 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.181516424 |
|
|
Sep 01 08:27:49 PM UTC 24 |
Sep 01 08:28:19 PM UTC 24 |
6154922700 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.636467991 |
|
|
Sep 01 08:27:46 PM UTC 24 |
Sep 01 08:28:19 PM UTC 24 |
210031653 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.3301691307 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:19 PM UTC 24 |
233421055 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.4011808578 |
|
|
Sep 01 08:27:53 PM UTC 24 |
Sep 01 08:28:19 PM UTC 24 |
165135575 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2524287626 |
|
|
Sep 01 08:28:14 PM UTC 24 |
Sep 01 08:28:19 PM UTC 24 |
975910824 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3497158500 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:20 PM UTC 24 |
912933645 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.783712877 |
|
|
Sep 01 08:28:16 PM UTC 24 |
Sep 01 08:28:21 PM UTC 24 |
2953565986 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.3049081015 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:21 PM UTC 24 |
46968894 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3323334190 |
|
|
Sep 01 08:28:04 PM UTC 24 |
Sep 01 08:28:21 PM UTC 24 |
6251034582 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.199118694 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:21 PM UTC 24 |
237650991 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.403287455 |
|
|
Sep 01 08:28:07 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
39690691 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.3885256670 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
185883890 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.6188503 |
|
|
Sep 01 08:28:07 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
540745167 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1849971796 |
|
|
Sep 01 08:28:09 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
2589084053 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2952672281 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
376221344 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2006279014 |
|
|
Sep 01 08:27:37 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
84004263 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2252485068 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:23 PM UTC 24 |
1428337196 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3214715343 |
|
|
Sep 01 08:27:37 PM UTC 24 |
Sep 01 08:28:24 PM UTC 24 |
882356492 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.689241044 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:24 PM UTC 24 |
850527200 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4149559196 |
|
|
Sep 01 08:27:37 PM UTC 24 |
Sep 01 08:28:24 PM UTC 24 |
903410195 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.2795062451 |
|
|
Sep 01 08:28:16 PM UTC 24 |
Sep 01 08:28:30 PM UTC 24 |
6583195680 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3389402299 |
|
|
Sep 01 08:28:06 PM UTC 24 |
Sep 01 08:28:31 PM UTC 24 |
13566317091 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3314029238 |
|
|
Sep 01 08:27:37 PM UTC 24 |
Sep 01 08:28:32 PM UTC 24 |
150840439 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3628085413 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:41 PM UTC 24 |
32081568 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.2481016383 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:41 PM UTC 24 |
314904688 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.411197713 |
|
|
Sep 01 08:28:05 PM UTC 24 |
Sep 01 08:28:41 PM UTC 24 |
176659703 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1341314922 |
|
|
Sep 01 08:27:37 PM UTC 24 |
Sep 01 08:28:42 PM UTC 24 |
36271159 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.1780777374 |
|
|
Sep 01 08:28:20 PM UTC 24 |
Sep 01 08:28:22 PM UTC 24 |
123420183 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3064938779 |
|
|
Sep 01 08:28:17 PM UTC 24 |
Sep 01 08:28:23 PM UTC 24 |
206275964 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.654686618 |
|
|
Sep 01 08:28:20 PM UTC 24 |
Sep 01 08:28:23 PM UTC 24 |
57460753 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3735279641 |
|
|
Sep 01 08:28:20 PM UTC 24 |
Sep 01 08:28:24 PM UTC 24 |
736774757 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2959507766 |
|
|
Sep 01 08:28:20 PM UTC 24 |
Sep 01 08:28:24 PM UTC 24 |
826401825 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.4016453574 |
|
|
Sep 01 08:28:25 PM UTC 24 |
Sep 01 08:28:28 PM UTC 24 |
130938667 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.1492814533 |
|
|
Sep 01 08:28:24 PM UTC 24 |
Sep 01 08:28:36 PM UTC 24 |
18199236 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1497469171 |
|
|
Sep 01 08:28:25 PM UTC 24 |
Sep 01 08:28:37 PM UTC 24 |
218963793 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1342869906 |
|
|
Sep 01 08:28:25 PM UTC 24 |
Sep 01 08:28:37 PM UTC 24 |
41281357 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2205661011 |
|
|
Sep 01 08:28:25 PM UTC 24 |
Sep 01 08:28:37 PM UTC 24 |
103998199 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.406731818 |
|
|
Sep 01 08:28:28 PM UTC 24 |
Sep 01 08:28:37 PM UTC 24 |
24681664 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3977017047 |
|
|
Sep 01 08:28:18 PM UTC 24 |
Sep 01 08:28:38 PM UTC 24 |
54081174 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1941325196 |
|
|
Sep 01 08:28:18 PM UTC 24 |
Sep 01 08:28:38 PM UTC 24 |
307282070 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.3468326246 |
|
|
Sep 01 08:28:25 PM UTC 24 |
Sep 01 08:28:38 PM UTC 24 |
220759008 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1107451561 |
|
|
Sep 01 08:28:18 PM UTC 24 |
Sep 01 08:28:38 PM UTC 24 |
149439986 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1245609657 |
|
|
Sep 01 08:28:22 PM UTC 24 |
Sep 01 08:28:38 PM UTC 24 |
53896109 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3938328809 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:38 PM UTC 24 |
68477300 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2164646088 |
|
|
Sep 01 08:28:18 PM UTC 24 |
Sep 01 08:28:40 PM UTC 24 |
317275434 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1049148368 |
|
|
Sep 01 08:28:39 PM UTC 24 |
Sep 01 08:28:42 PM UTC 24 |
74588588 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.341852493 |
|
|
Sep 01 08:28:39 PM UTC 24 |
Sep 01 08:28:42 PM UTC 24 |
170343086 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1748622709 |
|
|
Sep 01 08:28:30 PM UTC 24 |
Sep 01 08:28:42 PM UTC 24 |
28852624 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2396204525 |
|
|
Sep 01 08:28:38 PM UTC 24 |
Sep 01 08:28:42 PM UTC 24 |
38781944 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.174033729 |
|
|
Sep 01 08:28:33 PM UTC 24 |
Sep 01 08:28:42 PM UTC 24 |
133221713 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.826830989 |
|
|
Sep 01 08:28:38 PM UTC 24 |
Sep 01 08:28:43 PM UTC 24 |
152014947 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.40349534 |
|
|
Sep 01 08:28:42 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
48040930 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.574657568 |
|
|
Sep 01 08:28:42 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
28619432 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1996171783 |
|
|
Sep 01 08:28:42 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
116651651 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.302111681 |
|
|
Sep 01 08:28:42 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
364868190 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.3599538998 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
41649209 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2677439892 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
35240974 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4255258077 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
22617053 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.2367257013 |
|
|
Sep 01 08:28:42 PM UTC 24 |
Sep 01 08:28:47 PM UTC 24 |
31310707 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3374792375 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:48 PM UTC 24 |
250508579 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2770273226 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:48 PM UTC 24 |
115892339 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2828893679 |
|
|
Sep 01 08:28:24 PM UTC 24 |
Sep 01 08:28:53 PM UTC 24 |
30539779 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.740674342 |
|
|
Sep 01 08:28:20 PM UTC 24 |
Sep 01 08:28:55 PM UTC 24 |
561227267 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3982207139 |
|
|
Sep 01 08:28:49 PM UTC 24 |
Sep 01 08:28:57 PM UTC 24 |
42012380 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1848359481 |
|
|
Sep 01 08:28:49 PM UTC 24 |
Sep 01 08:28:57 PM UTC 24 |
22484040 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3028739600 |
|
|
Sep 01 08:28:49 PM UTC 24 |
Sep 01 08:28:57 PM UTC 24 |
70842751 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2375033053 |
|
|
Sep 01 08:28:56 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
38182589 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.1638427235 |
|
|
Sep 01 08:28:39 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
24980335 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3400049533 |
|
|
Sep 01 08:28:49 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
40927049 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2098651433 |
|
|
Sep 01 08:28:39 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
23355338 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1733441286 |
|
|
Sep 01 08:28:23 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
156216144 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.140245513 |
|
|
Sep 01 08:28:39 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
113347820 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1164560056 |
|
|
Sep 01 08:28:39 PM UTC 24 |
Sep 01 08:28:58 PM UTC 24 |
231691448 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3493462811 |
|
|
Sep 01 08:28:54 PM UTC 24 |
Sep 01 08:28:59 PM UTC 24 |
20380088 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.203194746 |
|
|
Sep 01 08:28:37 PM UTC 24 |
Sep 01 08:28:59 PM UTC 24 |
60396592 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3840942624 |
|
|
Sep 01 08:28:49 PM UTC 24 |
Sep 01 08:28:59 PM UTC 24 |
115902828 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.911204028 |
|
|
Sep 01 08:28:50 PM UTC 24 |
Sep 01 08:28:59 PM UTC 24 |
199308126 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1591009331 |
|
|
Sep 01 08:28:59 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
51411597 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.497673063 |
|
|
Sep 01 08:28:59 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
35196181 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1145134814 |
|
|
Sep 01 08:28:43 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
23212480 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3399272284 |
|
|
Sep 01 08:28:59 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
58884578 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3748015531 |
|
|
Sep 01 08:28:43 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
35526734 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.735971007 |
|
|
Sep 01 08:28:47 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
25741835 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2491689750 |
|
|
Sep 01 08:28:59 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
128205598 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4188277494 |
|
|
Sep 01 08:28:43 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
50647554 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.965559390 |
|
|
Sep 01 08:29:00 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
57685204 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1618261843 |
|
|
Sep 01 08:28:48 PM UTC 24 |
Sep 01 08:29:02 PM UTC 24 |
45730310 ps |