| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.95 | 98.23 | 96.58 | 99.62 | 96.00 | 96.37 | 100.00 | 98.85 |
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.2510387859 | Sep 01 08:28:38 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 68468685 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.4286154380 | Sep 01 08:28:38 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 48201835 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3005735091 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 19562663 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.673456903 | Sep 01 08:28:48 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 109893042 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2663688627 | Sep 01 08:28:43 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 72932423 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1050535563 | Sep 01 08:29:00 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 73376512 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2550835478 | Sep 01 08:28:41 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 53989296 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.808264017 | Sep 01 08:28:43 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 208644329 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3551714152 | Sep 01 08:28:24 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 61634357 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.85734336 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 248536700 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3975983916 | Sep 01 08:28:24 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 132636253 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2013652010 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 123159780 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.886913700 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 50664216 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.2753784374 | Sep 01 08:28:48 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 34737946 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1441796100 | Sep 01 08:28:59 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 132651791 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2326996259 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 325999093 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.2858616982 | Sep 01 08:28:24 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 30015108 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2606492961 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:03 PM UTC 24 | 29109317 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4186470623 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 47635369 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1741956966 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 32436068 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1762781804 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 17164686 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.520602349 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 30159031 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2709502153 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 195077077 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1781372735 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 20331690 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2764396 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 41836256 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1226201768 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 49914069 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1524505388 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 149646257 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1711332134 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 113481922 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4185484725 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:07 PM UTC 24 | 21162028 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.2869580077 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 19274679 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3415183102 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 60974143 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1537317805 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 46241204 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.87573381 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 18612690 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3753956001 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 126642716 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.1579476807 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 27101190 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1488498465 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 24844389 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.475958309 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 45079757 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.679305173 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 56273149 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3306786568 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 395760588 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.252440339 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 41124972 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1311725664 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 19423673 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1162834201 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 30504381 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3803710771 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 95024828 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.732806608 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 37050306 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3194226826 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 51124758 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.4091848959 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 101816323 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.647756254 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 22258750 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2821652588 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 43466104 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3705617552 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 794020253 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1906655404 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 47173763 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1528775893 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 20363568 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1793657 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 19920809 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.4120974604 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 615686762 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.4293035372 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 27370853 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.445483489 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 44138649 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.3205853020 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 21159846 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.3003357226 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 47948276 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3600195793 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:08 PM UTC 24 | 22437417 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.4088310855 | Sep 01 08:29:07 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 37615287 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2649911313 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 44989638 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3501094871 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 46641453 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2490428017 | Sep 01 08:29:07 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 40620912 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3488414615 | Sep 01 08:29:07 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 53606043 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.2325733279 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 17412678 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.803525519 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 34823182 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.174393660 | Sep 01 08:29:07 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 17660652 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3331603592 | Sep 01 08:29:07 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 70933257 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.4251593167 | Sep 01 08:29:07 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 16212038 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1640240792 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 733365153 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1730181701 | Sep 01 08:29:05 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 90996671 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2902755435 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 204285071 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2167257003 | Sep 01 08:29:06 PM UTC 24 | Sep 01 08:29:09 PM UTC 24 | 165008257 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1110993669 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:10 PM UTC 24 | 19861068 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1652310875 | Sep 01 08:28:58 PM UTC 24 | Sep 01 08:29:10 PM UTC 24 | 16201534 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2778757113 | Sep 01 08:28:31 PM UTC 24 | Sep 01 08:29:10 PM UTC 24 | 52461632 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.433470152 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:13 PM UTC 24 | 27628920 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.199463329 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:13 PM UTC 24 | 27261503 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.3973063052 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:16 PM UTC 24 | 20759448 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.413678550 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:16 PM UTC 24 | 18789946 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.114702870 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:16 PM UTC 24 | 20278103 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4250778048 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1093100532 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 08:24:33 PM UTC 24 |
| Finished | Sep 01 08:24:38 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250778048 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.4250778048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1294712970 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1329804804 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 08:24:39 PM UTC 24 |
| Finished | Sep 01 08:24:42 PM UTC 24 |
| Peak memory | 238752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294712970 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1294712970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.194374049 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 210708015 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:24:39 PM UTC 24 |
| Finished | Sep 01 08:24:41 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194374049 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.194374049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3831598113 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2805308810 ps |
| CPU time | 7.86 seconds |
| Started | Sep 01 08:24:39 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3831598113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr _stress_all_with_rand_reset.3831598113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.3814825918 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 42242178 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:24:39 PM UTC 24 |
| Finished | Sep 01 08:24:41 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814825918 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.3814825918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2205661011 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 103998199 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:28:25 PM UTC 24 |
| Finished | Sep 01 08:28:37 PM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205661011 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.2205661011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1632242470 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1209800441 ps |
| CPU time | 7.66 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:37 PM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1632242470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr _stress_all_with_rand_reset.1632242470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.40349534 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 48040930 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:42 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 206608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40349534 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pw rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.40349534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3309563675 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1189216730 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 08:24:57 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309563675 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3309563675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3735279641 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 736774757 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 08:28:20 PM UTC 24 |
| Finished | Sep 01 08:28:24 PM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735279641 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3735279641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4255258077 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 22617053 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 206520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255258077 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.4255258077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.753130724 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 35910382 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:24:35 PM UTC 24 |
| Finished | Sep 01 08:24:37 PM UTC 24 |
| Peak memory | 206164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753130724 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.753130724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.4037070056 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 269546297 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 08:24:45 PM UTC 24 |
| Finished | Sep 01 08:24:47 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037070056 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.4037070056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3293108598 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1854863037 ps |
| CPU time | 7.68 seconds |
| Started | Sep 01 08:25:46 PM UTC 24 |
| Finished | Sep 01 08:25:55 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3293108598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg r_stress_all_with_rand_reset.3293108598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3391586564 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30684182 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:24:32 PM UTC 24 |
| Finished | Sep 01 08:24:34 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391586564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3391586564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.3489637983 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 89616125 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:24:53 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489637983 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.3489637983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3705617552 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 794020253 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705617552 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.3705617552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3784493266 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 54576758 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784493266 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.3784493266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1848359481 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 22484040 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:49 PM UTC 24 |
| Finished | Sep 01 08:28:57 PM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848359481 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1848359481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.3670721803 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 172156925 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:55 PM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670721803 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.3670721803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2491689750 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 128205598 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:28:59 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491689750 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.2491689750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.3164715124 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 47693940 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:24:38 PM UTC 24 |
| Finished | Sep 01 08:24:40 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164715124 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3164715124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3064938779 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 206275964 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:28:17 PM UTC 24 |
| Finished | Sep 01 08:28:23 PM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064938779 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3064938779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1941325196 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 307282070 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:28:18 PM UTC 24 |
| Finished | Sep 01 08:28:38 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941325196 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1941325196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2164646088 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 317275434 ps |
| CPU time | 3.05 seconds |
| Started | Sep 01 08:28:18 PM UTC 24 |
| Finished | Sep 01 08:28:40 PM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164646088 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2164646088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.654686618 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 57460753 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:28:20 PM UTC 24 |
| Finished | Sep 01 08:28:23 PM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=654686618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_wi th_rand_reset.654686618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3977017047 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 54081174 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:18 PM UTC 24 |
| Finished | Sep 01 08:28:38 PM UTC 24 |
| Peak memory | 208444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977017047 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3977017047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1107451561 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 149439986 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:18 PM UTC 24 |
| Finished | Sep 01 08:28:38 PM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107451561 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.1107451561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1618261843 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 45730310 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:28:48 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1618261843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_ with_rand_reset.1618261843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3748015531 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 35526734 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:28:43 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748015531 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3748015531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1145134814 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 23212480 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:28:43 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 207076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145134814 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.1145134814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.735971007 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 25741835 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:28:47 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 209092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735971007 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.735971007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2663688627 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 72932423 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:28:43 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663688627 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2663688627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.808264017 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 208644329 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 08:28:43 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808264017 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.808264017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3400049533 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 40927049 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:49 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3400049533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_ with_rand_reset.3400049533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3982207139 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 42012380 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:49 PM UTC 24 |
| Finished | Sep 01 08:28:57 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982207139 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3982207139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3028739600 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 70842751 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:28:49 PM UTC 24 |
| Finished | Sep 01 08:28:57 PM UTC 24 |
| Peak memory | 209360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028739600 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.3028739600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.2753784374 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 34737946 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 08:28:48 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753784374 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.2753784374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.673456903 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 109893042 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:28:48 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673456903 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.673456903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.886913700 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 50664216 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=886913700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_w ith_rand_reset.886913700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2375033053 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 38182589 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:56 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375033053 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2375033053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3493462811 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 20380088 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:54 PM UTC 24 |
| Finished | Sep 01 08:28:59 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493462811 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3493462811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2013652010 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 123159780 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013652010 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.2013652010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3840942624 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 115902828 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 08:28:49 PM UTC 24 |
| Finished | Sep 01 08:28:59 PM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840942624 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3840942624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.911204028 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 199308126 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:28:50 PM UTC 24 |
| Finished | Sep 01 08:28:59 PM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911204028 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.911204028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3399272284 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 58884578 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:28:59 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3399272284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_ with_rand_reset.3399272284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1652310875 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 16201534 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:10 PM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652310875 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.1652310875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1110993669 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 19861068 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:10 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110993669 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1110993669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.85734336 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 248536700 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85734336 -assert nopostproc +UV M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.85734336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2606492961 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 29109317 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606492961 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2606492961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2326996259 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 325999093 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:28:58 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326996259 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.2326996259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1050535563 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 73376512 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:29:00 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1050535563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_ with_rand_reset.1050535563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1591009331 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 51411597 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:59 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591009331 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1591009331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.497673063 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 35196181 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:59 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 207000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497673063 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.497673063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.965559390 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 57685204 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:29:00 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965559390 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.965559390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1441796100 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 132651791 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 08:28:59 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441796100 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1441796100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1711332134 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 113481922 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1711332134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_ with_rand_reset.1711332134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3005735091 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 19562663 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005735091 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3005735091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4186470623 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 47635369 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186470623 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.4186470623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.520602349 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 30159031 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520602349 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.520602349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3753956001 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 126642716 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753956001 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3753956001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2709502153 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 195077077 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709502153 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.2709502153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1226201768 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 49914069 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1226201768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_ with_rand_reset.1226201768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1741956966 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 32436068 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741956966 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1741956966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1762781804 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 17164686 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762781804 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1762781804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1524505388 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 149646257 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524505388 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.1524505388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.4120974604 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 615686762 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120974604 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.4120974604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3415183102 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 60974143 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3415183102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_ with_rand_reset.3415183102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1781372735 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 20331690 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781372735 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1781372735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2764396 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 41836256 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base _test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwr mgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2764396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4185484725 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 21162028 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:07 PM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185484725 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.4185484725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1730181701 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 90996671 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730181701 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1730181701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3306786568 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 395760588 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:29:05 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306786568 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.3306786568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3194226826 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 51124758 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3194226826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_ with_rand_reset.3194226826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.87573381 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 18612690 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87573381 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.87573381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.2869580077 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 19274679 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869580077 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2869580077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1537317805 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 46241204 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537317805 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.1537317805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1640240792 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 733365153 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640240792 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1640240792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3803710771 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 95024828 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803710771 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.3803710771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.4091848959 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 101816323 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4091848959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_ with_rand_reset.4091848959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1488498465 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 24844389 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488498465 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1488498465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.1579476807 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 27101190 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579476807 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1579476807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1162834201 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 30504381 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162834201 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.1162834201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2167257003 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 165008257 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167257003 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2167257003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2902755435 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 204285071 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902755435 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.2902755435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.740674342 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 561227267 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 08:28:20 PM UTC 24 |
| Finished | Sep 01 08:28:55 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740674342 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.740674342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1311725664 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 19423673 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311725664 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1311725664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.475958309 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 45079757 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475958309 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.475958309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.679305173 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 56273149 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679305173 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.679305173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2821652588 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 43466104 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821652588 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2821652588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1528775893 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 20363568 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528775893 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1528775893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.732806608 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 37050306 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732806608 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.732806608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1906655404 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 47173763 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906655404 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1906655404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.252440339 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 41124972 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252440339 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.252440339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.4293035372 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 27370853 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293035372 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.4293035372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.647756254 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 22258750 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647756254 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.647756254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2959507766 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 826401825 ps |
| CPU time | 2.93 seconds |
| Started | Sep 01 08:28:20 PM UTC 24 |
| Finished | Sep 01 08:28:24 PM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959507766 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2959507766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1245609657 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 53896109 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:28:22 PM UTC 24 |
| Finished | Sep 01 08:28:38 PM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1245609657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_w ith_rand_reset.1245609657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.1780777374 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 123420183 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:20 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780777374 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1780777374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.445483489 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 44138649 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445483489 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.445483489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.3205853020 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 21159846 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205853020 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3205853020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3600195793 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 22437417 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600195793 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3600195793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3501094871 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 46641453 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501094871 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3501094871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1793657 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 19920809 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base _test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwr mgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1793657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.2325733279 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 17412678 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325733279 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2325733279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.803525519 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 34823182 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803525519 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.803525519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2649911313 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 44989638 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649911313 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2649911313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.3003357226 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 47948276 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:29:06 PM UTC 24 |
| Finished | Sep 01 08:29:08 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003357226 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3003357226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2490428017 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 40620912 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:29:07 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490428017 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2490428017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1733441286 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 156216144 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733441286 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1733441286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2770273226 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 115892339 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:48 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770273226 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2770273226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2677439892 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 35240974 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677439892 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.2677439892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3551714152 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 61634357 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:28:24 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3551714152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w ith_rand_reset.3551714152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.3599538998 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 41649209 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 207024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599538998 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3599538998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2828893679 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 30539779 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:28:24 PM UTC 24 |
| Finished | Sep 01 08:28:53 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828893679 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.2828893679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3938328809 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 68477300 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:38 PM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938328809 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3938328809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3374792375 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 250508579 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:28:23 PM UTC 24 |
| Finished | Sep 01 08:28:48 PM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374792375 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.3374792375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3331603592 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 70933257 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:29:07 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331603592 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3331603592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.4088310855 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 37615287 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:29:07 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088310855 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.4088310855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3488414615 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 53606043 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:29:07 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 206512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488414615 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3488414615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.174393660 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 17660652 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:29:07 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174393660 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.174393660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.4251593167 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 16212038 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:29:07 PM UTC 24 |
| Finished | Sep 01 08:29:09 PM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251593167 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.4251593167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.433470152 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 27628920 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:13 PM UTC 24 |
| Peak memory | 206396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433470152 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.433470152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.199463329 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 27261503 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:13 PM UTC 24 |
| Peak memory | 206516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199463329 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.199463329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.413678550 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 18789946 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:16 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413678550 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.413678550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.114702870 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 20278103 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:16 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114702870 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.114702870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.3973063052 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 20759448 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:16 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973063052 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3973063052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.4016453574 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 130938667 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:28:25 PM UTC 24 |
| Finished | Sep 01 08:28:28 PM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4016453574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_w ith_rand_reset.4016453574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1497469171 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 218963793 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:25 PM UTC 24 |
| Finished | Sep 01 08:28:37 PM UTC 24 |
| Peak memory | 208984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497469171 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1497469171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.1492814533 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 18199236 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:28:24 PM UTC 24 |
| Finished | Sep 01 08:28:36 PM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492814533 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.1492814533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1342869906 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 41281357 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:28:25 PM UTC 24 |
| Finished | Sep 01 08:28:37 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342869906 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.1342869906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.2858616982 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 30015108 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:28:24 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858616982 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2858616982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3975983916 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 132636253 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:28:24 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975983916 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.3975983916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.174033729 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 133221713 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:28:33 PM UTC 24 |
| Finished | Sep 01 08:28:42 PM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=174033729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_wi th_rand_reset.174033729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1748622709 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 28852624 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:30 PM UTC 24 |
| Finished | Sep 01 08:28:42 PM UTC 24 |
| Peak memory | 208600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748622709 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1748622709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.406731818 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 24681664 ps |
| CPU time | 0.51 seconds |
| Started | Sep 01 08:28:28 PM UTC 24 |
| Finished | Sep 01 08:28:37 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406731818 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.406731818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2778757113 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 52461632 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:28:31 PM UTC 24 |
| Finished | Sep 01 08:29:10 PM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778757113 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.2778757113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.3468326246 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 220759008 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:28:25 PM UTC 24 |
| Finished | Sep 01 08:28:38 PM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468326246 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3468326246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.341852493 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 170343086 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:28:39 PM UTC 24 |
| Finished | Sep 01 08:28:42 PM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=341852493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_wi th_rand_reset.341852493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.2510387859 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 68468685 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:38 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510387859 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2510387859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2396204525 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 38781944 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:28:38 PM UTC 24 |
| Finished | Sep 01 08:28:42 PM UTC 24 |
| Peak memory | 206720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396204525 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2396204525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.4286154380 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 48201835 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:28:38 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286154380 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.4286154380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.203194746 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 60396592 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:28:37 PM UTC 24 |
| Finished | Sep 01 08:28:59 PM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203194746 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.203194746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.826830989 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 152014947 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:28:38 PM UTC 24 |
| Finished | Sep 01 08:28:43 PM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826830989 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.826830989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2550835478 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 53989296 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:28:41 PM UTC 24 |
| Finished | Sep 01 08:29:03 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2550835478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w ith_rand_reset.2550835478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2098651433 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 23355338 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:39 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098651433 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2098651433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.1638427235 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 24980335 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:39 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 207024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638427235 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1638427235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1049148368 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 74588588 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:28:39 PM UTC 24 |
| Finished | Sep 01 08:28:42 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049148368 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.1049148368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.140245513 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 113347820 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:28:39 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140245513 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.140245513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1164560056 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 231691448 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:28:39 PM UTC 24 |
| Finished | Sep 01 08:28:58 PM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164560056 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.1164560056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4188277494 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 50647554 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:43 PM UTC 24 |
| Finished | Sep 01 08:29:02 PM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4188277494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w ith_rand_reset.4188277494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.574657568 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 28619432 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:42 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574657568 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.574657568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1996171783 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 116651651 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:28:42 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996171783 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.1996171783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.2367257013 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 31310707 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:28:42 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 210536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367257013 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2367257013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.302111681 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 364868190 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:28:42 PM UTC 24 |
| Finished | Sep 01 08:28:47 PM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302111681 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.302111681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2461185171 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 97026596 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:24:39 PM UTC 24 |
| Finished | Sep 01 08:24:41 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461185171 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.2461185171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.1664949590 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 108128830 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:24:37 PM UTC 24 |
| Finished | Sep 01 08:24:40 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664949590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.1664949590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2496699572 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 90161855 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:24:35 PM UTC 24 |
| Finished | Sep 01 08:24:38 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496699572 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2496699572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.835856659 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 354848703 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:24:32 PM UTC 24 |
| Finished | Sep 01 08:24:34 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835856659 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.835856659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.4292651962 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 74115574 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 08:24:30 PM UTC 24 |
| Finished | Sep 01 08:24:32 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292651962 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.4292651962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2223104764 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 148254519 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 08:24:35 PM UTC 24 |
| Finished | Sep 01 08:24:38 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223104764 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.2223104764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4060006514 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1120010559 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 08:24:35 PM UTC 24 |
| Finished | Sep 01 08:24:40 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060006514 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.4060006514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2550125054 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 80678323 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:24:35 PM UTC 24 |
| Finished | Sep 01 08:24:38 PM UTC 24 |
| Peak memory | 208224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550125054 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2550125054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.2967656978 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 31150532 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:24:29 PM UTC 24 |
| Finished | Sep 01 08:24:31 PM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967656978 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2967656978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3944538894 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2151389532 ps |
| CPU time | 4.1 seconds |
| Started | Sep 01 08:24:41 PM UTC 24 |
| Finished | Sep 01 08:24:46 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944538894 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3944538894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.4140272968 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 272411770 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:24:32 PM UTC 24 |
| Finished | Sep 01 08:24:34 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140272968 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.4140272968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.656296410 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 85433227 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:24:32 PM UTC 24 |
| Finished | Sep 01 08:24:34 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656296410 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.656296410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1625249215 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 65573683 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:24:42 PM UTC 24 |
| Finished | Sep 01 08:24:45 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625249215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1625249215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.3049294884 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 71968504 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:24:47 PM UTC 24 |
| Finished | Sep 01 08:24:49 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049294884 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.3049294884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2077891767 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29529451 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:24:44 PM UTC 24 |
| Finished | Sep 01 08:24:46 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077891767 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.2077891767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.712472397 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 380343111 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:24:46 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712472397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.712472397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.3204889738 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 38569524 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:24:46 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204889738 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3204889738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2310454806 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 28835447 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:24:46 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310454806 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2310454806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.1518545930 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 55368336 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:24:47 PM UTC 24 |
| Finished | Sep 01 08:24:49 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518545930 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.1518545930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.2799721953 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 236101658 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:24:41 PM UTC 24 |
| Finished | Sep 01 08:24:44 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799721953 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.2799721953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.3112645509 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 38458175 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:24:41 PM UTC 24 |
| Finished | Sep 01 08:24:43 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112645509 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3112645509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.1868515211 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 136413867 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:24:47 PM UTC 24 |
| Finished | Sep 01 08:24:50 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868515211 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1868515211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.3842880720 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 464821880 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:24:51 PM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842880720 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3842880720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3836964823 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 997784458 ps |
| CPU time | 3.22 seconds |
| Started | Sep 01 08:24:44 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836964823 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3836964823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1068750621 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 871997832 ps |
| CPU time | 5.62 seconds |
| Started | Sep 01 08:24:44 PM UTC 24 |
| Finished | Sep 01 08:24:50 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068750621 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1068750621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.86171929 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 65064563 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 08:24:44 PM UTC 24 |
| Finished | Sep 01 08:24:46 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86171929 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.86171929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1238705602 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 42698069 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:24:41 PM UTC 24 |
| Finished | Sep 01 08:24:43 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238705602 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1238705602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.3199449136 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 401579962 ps |
| CPU time | 3.41 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:24:53 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199449136 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.3199449136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.2459559972 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4347067385 ps |
| CPU time | 16.5 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:25:07 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2459559972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr _stress_all_with_rand_reset.2459559972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1207129278 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 196069576 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:24:41 PM UTC 24 |
| Finished | Sep 01 08:24:43 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207129278 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1207129278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.2525304481 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 206927877 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:24:42 PM UTC 24 |
| Finished | Sep 01 08:24:45 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525304481 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.2525304481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.536557842 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 41167870 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:25:34 PM UTC 24 |
| Finished | Sep 01 08:25:36 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536557842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.536557842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1794285165 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 50668813 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794285165 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.1794285165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2532418214 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 30853839 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532418214 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.2532418214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2508450000 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 112507692 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508450000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2508450000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3233289936 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36625150 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233289936 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3233289936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.683656238 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 27649584 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 206192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683656238 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.683656238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.804443198 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 76462642 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804443198 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.804443198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.1206807976 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 147150735 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:35 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206807976 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.1206807976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.1633078671 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 45570913 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633078671 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.1633078671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.1714173761 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 219541193 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 220040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714173761 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1714173761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.3518859861 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 248765564 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518859861 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.3518859861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.839302185 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 813744776 ps |
| CPU time | 4.13 seconds |
| Started | Sep 01 08:25:34 PM UTC 24 |
| Finished | Sep 01 08:25:39 PM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839302185 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.839302185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1153790230 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 777623715 ps |
| CPU time | 5.69 seconds |
| Started | Sep 01 08:25:34 PM UTC 24 |
| Finished | Sep 01 08:25:41 PM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153790230 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1153790230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1098988862 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 137041356 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098988862 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1098988862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3807071351 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 38336183 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807071351 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.3807071351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.4253942298 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1713888708 ps |
| CPU time | 5.42 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:43 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253942298 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.4253942298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3657055352 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1690029592 ps |
| CPU time | 3.64 seconds |
| Started | Sep 01 08:25:35 PM UTC 24 |
| Finished | Sep 01 08:25:41 PM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3657055352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg r_stress_all_with_rand_reset.3657055352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2205834470 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 584268038 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 08:25:33 PM UTC 24 |
| Finished | Sep 01 08:25:36 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205834470 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.2205834470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.687296595 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 359066781 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 08:25:33 PM UTC 24 |
| Finished | Sep 01 08:25:36 PM UTC 24 |
| Peak memory | 210348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687296595 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.687296595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1290076434 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 50070931 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:39 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290076434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1290076434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.2780823083 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 29834577 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:25:38 PM UTC 24 |
| Finished | Sep 01 08:25:40 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780823083 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.2780823083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2313605881 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 358807903 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313605881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2313605881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.3595007535 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 41890435 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595007535 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.3595007535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.562886173 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 121451578 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562886173 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.562886173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.3045547141 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 46411269 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045547141 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.3045547141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.1799508274 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 282155121 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:39 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799508274 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.1799508274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1780320328 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 119809131 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:39 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780320328 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1780320328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3653723453 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 117743065 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653723453 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3653723453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2400424730 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 103619808 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:25:38 PM UTC 24 |
| Finished | Sep 01 08:25:41 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400424730 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.2400424730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4269270529 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 879505694 ps |
| CPU time | 3.77 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269270529 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4269270529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2463047884 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2954410470 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 08:25:38 PM UTC 24 |
| Finished | Sep 01 08:25:41 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463047884 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2463047884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2129553847 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 98508001 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:25:38 PM UTC 24 |
| Finished | Sep 01 08:25:41 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129553847 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2129553847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3701749962 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 26984393 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:39 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701749962 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3701749962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.4134985935 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5631265655 ps |
| CPU time | 5.19 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134985935 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.4134985935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2426857098 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1047489955 ps |
| CPU time | 5.6 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2426857098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg r_stress_all_with_rand_reset.2426857098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1079447111 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 215719717 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:40 PM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079447111 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1079447111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.4031596012 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 323785260 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:25:37 PM UTC 24 |
| Finished | Sep 01 08:25:40 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031596012 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.4031596012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.4113287583 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 152385022 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:25:41 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113287583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.4113287583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.2281144002 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 45594438 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:45 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281144002 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.2281144002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.513818789 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 41896718 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:25:42 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513818789 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.513818789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2963935707 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 391216817 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:25:42 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963935707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2963935707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1310396762 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 49153454 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:45 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310396762 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1310396762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3380355768 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 42691074 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:25:42 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380355768 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3380355768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.4189100425 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 38211004 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:45 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189100425 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.4189100425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.4181120 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 186158193 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:43 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181120 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.4181120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1459668091 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 63567194 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:43 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459668091 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1459668091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.4118758714 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 101536777 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:46 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118758714 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.4118758714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.121713062 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 42356045 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:25:42 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121713062 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.121713062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4183374020 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 755633354 ps |
| CPU time | 5.17 seconds |
| Started | Sep 01 08:25:41 PM UTC 24 |
| Finished | Sep 01 08:25:48 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183374020 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4183374020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2327760458 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 763565633 ps |
| CPU time | 5.48 seconds |
| Started | Sep 01 08:25:41 PM UTC 24 |
| Finished | Sep 01 08:25:48 PM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327760458 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2327760458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3637934212 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 62787022 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:25:41 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637934212 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3637934212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3838807441 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 58481900 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:40 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838807441 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3838807441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.839539970 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 141044091 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:46 PM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839539970 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.839539970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1804701943 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 6511889633 ps |
| CPU time | 16.38 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1804701943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmg r_stress_all_with_rand_reset.1804701943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.266474415 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 314611442 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 08:25:41 PM UTC 24 |
| Finished | Sep 01 08:25:45 PM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266474415 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.266474415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.245665911 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 360772905 ps |
| CPU time | 2 seconds |
| Started | Sep 01 08:25:41 PM UTC 24 |
| Finished | Sep 01 08:25:44 PM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245665911 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.245665911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.1716172340 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 63729166 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716172340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1716172340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.4028297050 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 68247008 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:25:46 PM UTC 24 |
| Finished | Sep 01 08:25:48 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028297050 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.4028297050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1046474213 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 33170414 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046474213 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.1046474213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.2103574694 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 109757282 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103574694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2103574694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.1861301535 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 42267561 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:25:46 PM UTC 24 |
| Finished | Sep 01 08:25:48 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861301535 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.1861301535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.1123164602 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 47417206 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 208164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123164602 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1123164602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.3141805552 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 54909647 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:46 PM UTC 24 |
| Finished | Sep 01 08:25:49 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141805552 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.3141805552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.26404524 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 47886133 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:45 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26404524 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.26404524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3333078862 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 118247250 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:46 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333078862 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3333078862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.3053674474 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 175731130 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:25:46 PM UTC 24 |
| Finished | Sep 01 08:25:49 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053674474 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3053674474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.606646764 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 319022938 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:48 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606646764 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.606646764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1107710623 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 798185648 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107710623 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1107710623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.232158659 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 832281338 ps |
| CPU time | 4.61 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:50 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232158659 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.232158659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2790185405 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 171980086 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:25:45 PM UTC 24 |
| Finished | Sep 01 08:25:47 PM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790185405 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2790185405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1166219392 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 31153404 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:45 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166219392 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1166219392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.637845438 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1445245376 ps |
| CPU time | 3.31 seconds |
| Started | Sep 01 08:25:47 PM UTC 24 |
| Finished | Sep 01 08:25:51 PM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637845438 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.637845438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.3800247170 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 195436924 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:46 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800247170 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.3800247170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.1699525925 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 155581848 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:25:43 PM UTC 24 |
| Finished | Sep 01 08:25:46 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699525925 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.1699525925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.695040171 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 46431960 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:51 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695040171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.695040171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.603359576 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 65493271 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603359576 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.603359576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2786196327 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 37473585 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:50 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786196327 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.2786196327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.1330635888 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 205034528 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:51 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330635888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1330635888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.1538043770 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 60356276 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:51 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538043770 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1538043770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.4277324913 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 52920799 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:50 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277324913 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.4277324913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.3912961763 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 81813164 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912961763 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.3912961763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.3723924050 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 198545105 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:25:47 PM UTC 24 |
| Finished | Sep 01 08:25:49 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723924050 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.3723924050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.88373194 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 63571853 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:25:47 PM UTC 24 |
| Finished | Sep 01 08:25:49 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88373194 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.88373194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.4193601016 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 150471370 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193601016 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.4193601016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3229736040 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 184460646 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:51 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229736040 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.3229736040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1163159742 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 834133589 ps |
| CPU time | 4.87 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163159742 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1163159742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.429992203 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 871218923 ps |
| CPU time | 4.25 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:53 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429992203 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.429992203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3445682107 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 87537813 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:51 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445682107 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3445682107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.4132858687 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 31570051 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:47 PM UTC 24 |
| Finished | Sep 01 08:25:49 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132858687 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.4132858687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.1850682737 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1505990266 ps |
| CPU time | 4.49 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850682737 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.1850682737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.2542313038 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 9493599395 ps |
| CPU time | 12.74 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2542313038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmg r_stress_all_with_rand_reset.2542313038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.345484224 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 58766458 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:25:47 PM UTC 24 |
| Finished | Sep 01 08:25:49 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345484224 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.345484224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.1097530128 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 59009059 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:25:48 PM UTC 24 |
| Finished | Sep 01 08:25:50 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097530128 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.1097530128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.3862534097 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 38747086 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:53 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862534097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3862534097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1011028448 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 87247692 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011028448 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.1011028448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.3701572478 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 110152911 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701572478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3701572478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.207577672 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 58360481 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207577672 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.207577672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.478952914 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 62826712 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478952914 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.478952914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.160663178 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 110273381 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:55 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160663178 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.160663178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.876397981 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 81279286 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876397981 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.876397981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3653695534 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 113098050 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653695534 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3653695534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.137957289 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 103362463 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137957289 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.137957289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.1209658477 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 80092767 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209658477 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.1209658477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2186079789 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1000506551 ps |
| CPU time | 3.15 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186079789 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2186079789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3651188699 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1049452584 ps |
| CPU time | 3.84 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651188699 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3651188699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2424300335 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 172890558 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:25:52 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424300335 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2424300335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.3881511737 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 70990776 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881511737 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3881511737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.2062267157 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6884793343 ps |
| CPU time | 4.62 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062267157 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2062267157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.2685177993 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 6273589395 ps |
| CPU time | 8.36 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:26:03 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2685177993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg r_stress_all_with_rand_reset.2685177993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.4003251180 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 256112016 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:54 PM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003251180 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.4003251180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.3082850108 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 30671678 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:25:50 PM UTC 24 |
| Finished | Sep 01 08:25:52 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082850108 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3082850108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.2707865647 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 24357846 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:57 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707865647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2707865647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.3847134670 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 83779636 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:56 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847134670 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.3847134670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.858772328 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 29549153 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:57 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858772328 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.858772328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.3189261706 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 378691260 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:58 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189261706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3189261706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.2573193049 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 43127805 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:57 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573193049 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2573193049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.2051621272 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 144089899 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:57 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051621272 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2051621272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1929869917 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 73255129 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929869917 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.1929869917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.4049524000 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 315737363 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049524000 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.4049524000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.1803711489 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 46200042 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803711489 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1803711489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.50965346 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 155024485 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50965346 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.50965346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1693291926 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 248709851 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:58 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693291926 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.1693291926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.583116590 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 761908727 ps |
| CPU time | 4.27 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:26:00 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583116590 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.583116590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2483054428 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1251491067 ps |
| CPU time | 3 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483054428 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2483054428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1621113028 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 141062651 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:57 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621113028 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1621113028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.1657042701 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 30452440 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:25:53 PM UTC 24 |
| Finished | Sep 01 08:25:55 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657042701 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.1657042701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.3296766906 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2409703890 ps |
| CPU time | 4.44 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:26:02 PM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296766906 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.3296766906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.2541794665 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 17453242547 ps |
| CPU time | 21.47 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2541794665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmg r_stress_all_with_rand_reset.2541794665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2696538259 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 343681022 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:25:54 PM UTC 24 |
| Finished | Sep 01 08:25:56 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696538259 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2696538259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.1419449740 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 165108113 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 08:25:55 PM UTC 24 |
| Finished | Sep 01 08:25:57 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419449740 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.1419449740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.3315377165 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 66032033 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315377165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3315377165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.2096913260 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 62962029 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:25:59 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096913260 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.2096913260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.43043077 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 38548155 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:25:58 PM UTC 24 |
| Finished | Sep 01 08:26:00 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43043077 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.43043077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.2153538708 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 399492270 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:25:59 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153538708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2153538708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.2707176805 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 50406633 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:25:59 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707176805 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2707176805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.2225783794 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 29849455 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:25:59 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225783794 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2225783794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.1076652008 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 46475382 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:02 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076652008 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.1076652008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.1588818696 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 129619604 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588818696 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.1588818696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.1628503888 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 64249414 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628503888 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1628503888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.918966576 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 100761813 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:25:59 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918966576 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.918966576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3751774241 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 213566662 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 08:25:58 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751774241 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.3751774241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2576986623 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 826075538 ps |
| CPU time | 4.59 seconds |
| Started | Sep 01 08:25:58 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576986623 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2576986623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1298190907 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1034962474 ps |
| CPU time | 2.5 seconds |
| Started | Sep 01 08:25:58 PM UTC 24 |
| Finished | Sep 01 08:26:02 PM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298190907 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1298190907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.154611981 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 54629837 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 08:25:58 PM UTC 24 |
| Finished | Sep 01 08:26:01 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154611981 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.154611981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.400468746 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 37238861 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400468746 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.400468746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.2653444953 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2626189715 ps |
| CPU time | 4.55 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653444953 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.2653444953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.3458450772 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 6887819516 ps |
| CPU time | 11.54 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:13 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3458450772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmg r_stress_all_with_rand_reset.3458450772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3074813827 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 246219894 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:26:00 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074813827 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.3074813827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.3223031505 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 286647098 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 08:25:57 PM UTC 24 |
| Finished | Sep 01 08:26:00 PM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223031505 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.3223031505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.3846074903 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 28649165 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:26:01 PM UTC 24 |
| Finished | Sep 01 08:26:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846074903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3846074903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.4229457894 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 67653384 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229457894 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.4229457894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1051783501 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 38354079 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051783501 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.1051783501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2613988359 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 112513827 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613988359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2613988359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.159727944 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 48200808 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159727944 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.159727944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.626325460 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 38586127 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626325460 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.626325460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.633602616 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 51965094 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633602616 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.633602616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.2347877727 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 196935674 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:03 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347877727 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.2347877727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.3840029161 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 120500320 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:03 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840029161 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3840029161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.1553421710 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 114639830 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:05 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553421710 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1553421710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1878206611 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 324431110 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878206611 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.1878206611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.498088363 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1019803683 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 08:26:01 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498088363 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.498088363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.603046518 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1039662949 ps |
| CPU time | 2.26 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:05 PM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603046518 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.603046518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2856647215 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 68914833 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856647215 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2856647215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.2713997002 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 32080125 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:02 PM UTC 24 |
| Peak memory | 208148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713997002 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2713997002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.1395173327 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1178394954 ps |
| CPU time | 5.14 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:09 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395173327 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.1395173327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.933780182 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 4833497954 ps |
| CPU time | 19.87 seconds |
| Started | Sep 01 08:26:02 PM UTC 24 |
| Finished | Sep 01 08:26:23 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=933780182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr _stress_all_with_rand_reset.933780182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.1900982110 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 227420488 ps |
| CPU time | 2.15 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:04 PM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900982110 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1900982110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.2906163881 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 119057241 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:26:00 PM UTC 24 |
| Finished | Sep 01 08:26:03 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906163881 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.2906163881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.4247095335 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 44294205 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247095335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.4247095335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.1407689724 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 87380571 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407689724 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.1407689724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.3548746863 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 40194716 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548746863 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.3548746863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.852125563 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 357164896 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852125563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.852125563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.3705109037 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 35460324 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705109037 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.3705109037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.2607955044 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 43103178 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:07 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607955044 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2607955044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.2869727351 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 46530933 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869727351 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.2869727351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.3891732147 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 288083983 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891732147 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.3891732147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.1923565380 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 106343278 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923565380 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1923565380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.2351314741 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 101588436 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351314741 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2351314741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.2345662673 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 89161770 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345662673 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.2345662673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.976996709 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1323403266 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976996709 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.976996709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2554273187 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1035412801 ps |
| CPU time | 2.34 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:07 PM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554273187 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2554273187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3091275640 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 72515752 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:07 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091275640 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3091275640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.1377920310 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 30510939 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377920310 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1377920310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.1624812474 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1587754641 ps |
| CPU time | 3.86 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:11 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624812474 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.1624812474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.2976904448 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 5854808095 ps |
| CPU time | 9.78 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2976904448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmg r_stress_all_with_rand_reset.2976904448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.501801745 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 233351966 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501801745 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.501801745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.2099385988 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 406759693 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:26:04 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099385988 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.2099385988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.810989523 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 33797608 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:24:50 PM UTC 24 |
| Finished | Sep 01 08:24:53 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810989523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.810989523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2223154699 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 29347503 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:24:51 PM UTC 24 |
| Finished | Sep 01 08:24:53 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223154699 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.2223154699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2412675692 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 400308790 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:24:53 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412675692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2412675692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3878624040 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 46471994 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:24:53 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 206208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878624040 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3878624040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.3244699684 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 25732915 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:24:53 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244699684 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3244699684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.3350414290 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 228000275 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:24:54 PM UTC 24 |
| Finished | Sep 01 08:24:56 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350414290 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.3350414290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.2048806231 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 291644531 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:24:52 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048806231 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.2048806231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.329530266 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 80650537 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:24:51 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329530266 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.329530266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1319618463 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 111853014 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:24:53 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319618463 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1319618463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.3990604243 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 807187311 ps |
| CPU time | 3.18 seconds |
| Started | Sep 01 08:24:54 PM UTC 24 |
| Finished | Sep 01 08:24:58 PM UTC 24 |
| Peak memory | 239072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990604243 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.3990604243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1978266511 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 314130351 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:24:52 PM UTC 24 |
| Finished | Sep 01 08:24:54 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978266511 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.1978266511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2913429845 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 841763465 ps |
| CPU time | 4.91 seconds |
| Started | Sep 01 08:24:50 PM UTC 24 |
| Finished | Sep 01 08:24:56 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913429845 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2913429845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.582140677 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2357184808 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 08:24:50 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582140677 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.582140677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.576130296 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 107060740 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:24:51 PM UTC 24 |
| Finished | Sep 01 08:24:54 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576130296 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.576130296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3930932377 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 26569953 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:24:51 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930932377 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3930932377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.3849137421 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1566353925 ps |
| CPU time | 4.46 seconds |
| Started | Sep 01 08:24:54 PM UTC 24 |
| Finished | Sep 01 08:25:00 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849137421 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3849137421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2411858801 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4716025820 ps |
| CPU time | 19 seconds |
| Started | Sep 01 08:24:54 PM UTC 24 |
| Finished | Sep 01 08:25:14 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2411858801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr _stress_all_with_rand_reset.2411858801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.665069684 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 114701619 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:24:49 PM UTC 24 |
| Finished | Sep 01 08:24:51 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665069684 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.665069684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.110108540 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 55217283 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:24:50 PM UTC 24 |
| Finished | Sep 01 08:24:52 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110108540 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.110108540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.2695170107 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 44887981 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:26:07 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695170107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2695170107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.1642675818 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 81242190 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642675818 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.1642675818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.262932058 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 29516670 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262932058 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.262932058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.2260094876 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 622010546 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260094876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2260094876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.2392268351 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 29995877 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392268351 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2392268351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.2392922212 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 35983058 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:09 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392922212 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2392922212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.2277543941 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 52084706 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:11 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277543941 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.2277543941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.881725031 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 225763219 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881725031 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.881725031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.2150054853 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 50135145 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150054853 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.2150054853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.1889577310 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 188768342 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:11 PM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889577310 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1889577310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3035232514 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 111245804 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035232514 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.3035232514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2271030525 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 748769476 ps |
| CPU time | 3.22 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271030525 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2271030525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1611770955 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1005316239 ps |
| CPU time | 2.64 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:11 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611770955 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1611770955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.694542007 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 180134088 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:26:08 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694542007 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.694542007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.270193178 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 116836928 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:26:06 PM UTC 24 |
| Finished | Sep 01 08:26:08 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270193178 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.270193178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.3357182410 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1275563558 ps |
| CPU time | 4.58 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357182410 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3357182410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.634187332 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 6705705871 ps |
| CPU time | 15.87 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:26 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=634187332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr _stress_all_with_rand_reset.634187332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.4064217163 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 303459247 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:26:07 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064217163 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.4064217163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.17339835 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 133822381 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:26:07 PM UTC 24 |
| Finished | Sep 01 08:26:10 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17339835 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.17339835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.1105446471 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 31744204 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105446471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1105446471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2128175583 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 63377743 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:13 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128175583 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.2128175583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3256777391 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 30791694 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256777391 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.3256777391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.2248333472 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 110001255 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248333472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2248333472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.3018574999 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 102375137 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:13 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018574999 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3018574999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.841254317 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 60915203 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:13 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841254317 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.841254317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.2280118833 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 43795678 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280118833 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.2280118833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.485106346 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 290521211 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485106346 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.485106346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.2521938775 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 136229233 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521938775 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2521938775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.1870536599 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 106457640 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870536599 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1870536599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.3949018193 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 160231696 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949018193 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.3949018193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1948966855 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 857776891 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948966855 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1948966855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3798310315 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 738600517 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798310315 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3798310315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.678084300 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 50836933 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678084300 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.678084300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.1311648969 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 30624674 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:26:09 PM UTC 24 |
| Finished | Sep 01 08:26:11 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311648969 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1311648969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.4109123088 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2203659667 ps |
| CPU time | 9.77 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:22 PM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109123088 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.4109123088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.3581420563 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4334985317 ps |
| CPU time | 15.73 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:28 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3581420563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmg r_stress_all_with_rand_reset.3581420563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.2789133906 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 81988361 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789133906 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2789133906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.2083762019 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 196064728 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:26:10 PM UTC 24 |
| Finished | Sep 01 08:26:12 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083762019 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.2083762019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.1439391085 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 66101777 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439391085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1439391085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.2936197715 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 57445655 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:16 PM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936197715 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.2936197715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3255683347 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 31487947 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255683347 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.3255683347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.3459356289 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 113455383 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:16 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459356289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3459356289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.4083056511 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 59209807 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083056511 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.4083056511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.3364577883 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 79906215 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364577883 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3364577883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.449058755 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 44665102 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449058755 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.449058755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.3378342733 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 178105458 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:16 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378342733 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.3378342733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.1728314786 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 78455660 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:26:12 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728314786 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1728314786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.2199292615 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 147856618 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 220136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199292615 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2199292615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.322786691 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 299528518 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322786691 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.322786691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1841819696 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1243012978 ps |
| CPU time | 2.31 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:16 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841819696 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1841819696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.125674769 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 934210631 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125674769 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.125674769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2650143000 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 54882196 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:16 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650143000 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2650143000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.1967707668 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 31462337 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:26:11 PM UTC 24 |
| Finished | Sep 01 08:26:13 PM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967707668 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1967707668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.3714826155 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1308257708 ps |
| CPU time | 5.83 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:22 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714826155 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.3714826155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.1558567671 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 809962597 ps |
| CPU time | 3.42 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1558567671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmg r_stress_all_with_rand_reset.1558567671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.2304275347 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 151870664 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:15 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304275347 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.2304275347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.875157644 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 136393431 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 08:26:13 PM UTC 24 |
| Finished | Sep 01 08:26:16 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875157644 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.875157644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.946738591 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 52528019 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946738591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.946738591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3595362597 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 60249087 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595362597 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.3595362597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1131818516 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 46379968 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 206204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131818516 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.1131818516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.3792504620 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 339918180 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792504620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3792504620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.1937605176 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 66090861 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937605176 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1937605176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.894488763 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 49398679 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894488763 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.894488763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.2165417742 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 38900057 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165417742 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.2165417742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.1596852851 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 131529437 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 208236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596852851 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.1596852851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.2503522544 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 53678853 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503522544 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2503522544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.895874389 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 116410655 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895874389 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.895874389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.1403071086 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 255330496 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403071086 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.1403071086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1532746452 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 955250173 ps |
| CPU time | 2.9 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532746452 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1532746452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3811745808 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1044713724 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:20 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811745808 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3811745808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1079065258 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 69448182 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079065258 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1079065258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.1087605419 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 89406801 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087605419 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1087605419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2623437078 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 223773050 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:20 PM UTC 24 |
| Peak memory | 210660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623437078 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2623437078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.2698714825 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4844569596 ps |
| CPU time | 15.55 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:34 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2698714825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg r_stress_all_with_rand_reset.2698714825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.2195961347 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 158159056 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 208220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195961347 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.2195961347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.3208634077 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 95910294 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:15 PM UTC 24 |
| Finished | Sep 01 08:26:17 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208634077 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3208634077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3740874633 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 32988417 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740874633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3740874633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.2726285144 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 61978806 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:26:20 PM UTC 24 |
| Finished | Sep 01 08:26:42 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726285144 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.2726285144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3097801789 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 30125394 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097801789 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.3097801789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.3680906030 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 637399944 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680906030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3680906030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.3768169037 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 86648989 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:22 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768169037 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3768169037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.1409486652 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 86463324 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:26:20 PM UTC 24 |
| Finished | Sep 01 08:26:32 PM UTC 24 |
| Peak memory | 210592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409486652 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.1409486652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.1955327057 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 291044048 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:26:18 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955327057 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.1955327057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.3043538576 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 105874637 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:26:18 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043538576 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3043538576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.2894405135 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 99973769 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:26:20 PM UTC 24 |
| Finished | Sep 01 08:26:32 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894405135 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2894405135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1261644505 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 296092788 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261644505 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.1261644505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4081937904 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1201569529 ps |
| CPU time | 2.53 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:22 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081937904 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4081937904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2750196889 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 917025261 ps |
| CPU time | 3.61 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:23 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750196889 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2750196889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2301529996 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 65629993 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:19 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301529996 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2301529996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2816296350 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 75745238 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:26:17 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816296350 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2816296350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.2312929911 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1426793784 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:26:20 PM UTC 24 |
| Finished | Sep 01 08:26:54 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312929911 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2312929911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1671377300 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5737160841 ps |
| CPU time | 15.44 seconds |
| Started | Sep 01 08:26:20 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1671377300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmg r_stress_all_with_rand_reset.1671377300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.611859647 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 56804402 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:26:18 PM UTC 24 |
| Finished | Sep 01 08:26:20 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611859647 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.611859647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.2602269740 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 188034008 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:26:18 PM UTC 24 |
| Finished | Sep 01 08:26:21 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602269740 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.2602269740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.576197309 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 52387573 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576197309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.576197309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.107997036 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 45936071 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107997036 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.107997036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1066200673 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 30440903 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066200673 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.1066200673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.2526725745 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 114512738 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:27 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526725745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2526725745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.938787539 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 30246354 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938787539 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.938787539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.125457626 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 286743987 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125457626 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.125457626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.1976491363 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 44700781 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976491363 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.1976491363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.2857046612 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 73780182 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857046612 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.2857046612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.1077046348 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 39820895 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077046348 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1077046348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.2709717402 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 113663542 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709717402 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2709717402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.37211233 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 336850067 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37211233 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.37211233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2276393582 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 847416425 ps |
| CPU time | 2.93 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:27:05 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276393582 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2276393582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.987299670 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1271625471 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:26:54 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987299670 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.987299670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3370167429 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 70537465 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370167429 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3370167429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.1454221763 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 53210493 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:26:52 PM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454221763 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1454221763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.334968764 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2396870301 ps |
| CPU time | 4.27 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:27:01 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334968764 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.334968764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.26902015 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5034826568 ps |
| CPU time | 7.06 seconds |
| Started | Sep 01 08:26:22 PM UTC 24 |
| Finished | Sep 01 08:27:04 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=26902015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_ stress_all_with_rand_reset.26902015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.1721237123 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 234643111 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721237123 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.1721237123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.684121965 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 130339202 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:26:21 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684121965 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.684121965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.3521950104 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 84721060 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:26:24 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 210808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521950104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3521950104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3915456030 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 48864135 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:26:30 PM UTC 24 |
| Finished | Sep 01 08:26:42 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915456030 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.3915456030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.4272335145 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 29205075 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:26:27 PM UTC 24 |
| Finished | Sep 01 08:26:32 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272335145 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.4272335145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.757536459 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 378440520 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:26:28 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757536459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.757536459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.4041720136 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 59701972 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:26:28 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041720136 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.4041720136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.4205810080 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 41651384 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:26:28 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205810080 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.4205810080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.1838201909 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 44395091 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:26:33 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838201909 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.1838201909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.1277830397 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 176421371 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:26:24 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277830397 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.1277830397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.1195609202 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 163715777 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:26:23 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195609202 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.1195609202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.4219184549 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 109359722 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:26:33 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219184549 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.4219184549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2297243948 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 385055223 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:26:28 PM UTC 24 |
| Finished | Sep 01 08:26:48 PM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297243948 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.2297243948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.286228681 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1080013651 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 08:26:25 PM UTC 24 |
| Finished | Sep 01 08:26:38 PM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286228681 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.286228681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4026411952 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 533851609 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:26:25 PM UTC 24 |
| Finished | Sep 01 08:26:37 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026411952 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4026411952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.3957582340 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 31096907 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:26:23 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957582340 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3957582340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.3568210450 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1777613221 ps |
| CPU time | 5.84 seconds |
| Started | Sep 01 08:26:34 PM UTC 24 |
| Finished | Sep 01 08:27:08 PM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568210450 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.3568210450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.547128277 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2546976045 ps |
| CPU time | 6.27 seconds |
| Started | Sep 01 08:26:34 PM UTC 24 |
| Finished | Sep 01 08:27:08 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=547128277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr _stress_all_with_rand_reset.547128277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.1979582710 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 973081183 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:26:24 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979582710 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.1979582710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.1479457711 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 265857068 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:26:24 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479457711 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.1479457711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.3357404565 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 123243116 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:26:39 PM UTC 24 |
| Finished | Sep 01 08:26:42 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357404565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3357404565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2050497465 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 85190450 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:26:44 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050497465 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.2050497465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.681353305 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 69029901 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:26:40 PM UTC 24 |
| Finished | Sep 01 08:26:42 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681353305 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.681353305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.1990403443 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 111842551 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:26:44 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990403443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1990403443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.3990426203 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 41504072 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:26:44 PM UTC 24 |
| Finished | Sep 01 08:26:52 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990426203 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3990426203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.1298697783 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 32859803 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:26:43 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298697783 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1298697783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.2083983693 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 57353430 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:26:44 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083983693 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.2083983693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.2266562761 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 251613639 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:26:37 PM UTC 24 |
| Finished | Sep 01 08:26:43 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266562761 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.2266562761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.1394088810 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 34592699 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:26:35 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394088810 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1394088810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.2867768085 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 117819106 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:26:44 PM UTC 24 |
| Finished | Sep 01 08:26:53 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867768085 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2867768085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.268492443 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 305705695 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:26:41 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268492443 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.268492443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1042867510 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 705941469 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 08:26:39 PM UTC 24 |
| Finished | Sep 01 08:26:44 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042867510 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1042867510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3766914947 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 811911785 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 08:26:39 PM UTC 24 |
| Finished | Sep 01 08:26:44 PM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766914947 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3766914947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.534438754 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 69868543 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:26:40 PM UTC 24 |
| Finished | Sep 01 08:26:42 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534438754 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.534438754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.864546135 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 31965955 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:26:35 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864546135 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.864546135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.874345380 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5536037276 ps |
| CPU time | 3.12 seconds |
| Started | Sep 01 08:26:45 PM UTC 24 |
| Finished | Sep 01 08:27:00 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874345380 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.874345380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.3316654891 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 6302432316 ps |
| CPU time | 10.83 seconds |
| Started | Sep 01 08:26:45 PM UTC 24 |
| Finished | Sep 01 08:27:08 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3316654891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmg r_stress_all_with_rand_reset.3316654891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.2257465153 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 166036479 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:26:38 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257465153 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2257465153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.23812271 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 154892535 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:26:38 PM UTC 24 |
| Finished | Sep 01 08:26:47 PM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23812271 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.23812271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.1483755553 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 33568700 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:26:48 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483755553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1483755553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.446699295 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 67965477 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:02 PM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446699295 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.446699295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.2142029016 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 122175596 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:26:52 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142029016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.2142029016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.1241723358 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 43761288 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:26:52 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 206184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241723358 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1241723358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.96036307 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 71747920 ps |
| CPU time | 0.52 seconds |
| Started | Sep 01 08:26:50 PM UTC 24 |
| Finished | Sep 01 08:26:52 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96036307 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.96036307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.2595878196 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 110313669 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:02 PM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595878196 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.2595878196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.2444955231 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 162962352 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:26:48 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444955231 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.2444955231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.2582618893 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 57561285 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:26:45 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582618893 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2582618893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.1317281029 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 107863636 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:26:59 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317281029 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1317281029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.740091318 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 78424604 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:26:50 PM UTC 24 |
| Finished | Sep 01 08:26:52 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740091318 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.740091318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3874546623 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1237022672 ps |
| CPU time | 2 seconds |
| Started | Sep 01 08:26:48 PM UTC 24 |
| Finished | Sep 01 08:27:04 PM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874546623 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3874546623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2981465111 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 226680812 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:26:48 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981465111 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2981465111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.3531020307 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 48834203 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:26:45 PM UTC 24 |
| Finished | Sep 01 08:26:58 PM UTC 24 |
| Peak memory | 207976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531020307 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3531020307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2762417910 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1714910209 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:05 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762417910 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.2762417910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.360044497 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 274135644 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:26:48 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360044497 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.360044497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.3403289923 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 130179472 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:26:48 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403289923 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.3403289923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.2731408899 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 60600667 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731408899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2731408899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.3252353775 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 93474108 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:01 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252353775 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.3252353775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3759779978 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 87463106 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:26:55 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759779978 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.3759779978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.2067153104 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 112384208 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:26:58 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 207612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067153104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.2067153104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.502899494 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 105715632 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:26:58 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 207816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502899494 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.502899494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.3849196961 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 49485002 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:26:58 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849196961 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3849196961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.2830907000 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 82812471 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830907000 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.2830907000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.327633101 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 137226996 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327633101 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.327633101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.3736690456 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 47764619 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:02 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736690456 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3736690456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.3047203705 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 105362576 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047203705 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3047203705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2417465272 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 132738854 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:26:56 PM UTC 24 |
| Finished | Sep 01 08:26:59 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417465272 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.2417465272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.595326793 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 773690288 ps |
| CPU time | 3.22 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:06 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595326793 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.595326793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1384912278 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 815582467 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:05 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384912278 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1384912278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3680154011 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 89132130 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:26:55 PM UTC 24 |
| Finished | Sep 01 08:26:57 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680154011 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3680154011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.2896644354 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 38035744 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:02 PM UTC 24 |
| Peak memory | 208208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896644354 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2896644354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.3059929417 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1798689611 ps |
| CPU time | 5.62 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059929417 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.3059929417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.282686123 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8257059498 ps |
| CPU time | 10.64 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=282686123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr _stress_all_with_rand_reset.282686123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.120267451 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 76868242 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120267451 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.120267451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.1216435886 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 153647560 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:26:54 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216435886 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1216435886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.4139360037 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 24464240 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:24:57 PM UTC 24 |
| Finished | Sep 01 08:24:59 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139360037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.4139360037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.810726085 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 98667704 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:24:59 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810726085 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.810726085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1812709919 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 37038860 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:24:57 PM UTC 24 |
| Finished | Sep 01 08:24:59 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812709919 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.1812709919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.4252433290 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 111291361 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 08:24:59 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252433290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.4252433290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2057257412 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 63146976 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:24:59 PM UTC 24 |
| Finished | Sep 01 08:25:01 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057257412 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2057257412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.3322178555 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 35757134 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:24:59 PM UTC 24 |
| Finished | Sep 01 08:25:01 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322178555 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3322178555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.2322975849 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 72103594 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:25:00 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322975849 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.2322975849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.520028371 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 261572984 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 08:24:56 PM UTC 24 |
| Finished | Sep 01 08:24:58 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520028371 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.520028371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3004477470 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 62858453 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:24:56 PM UTC 24 |
| Finished | Sep 01 08:24:58 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004477470 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3004477470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3660023796 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 106452820 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 08:25:00 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660023796 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3660023796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.2273594285 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 501241087 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 08:25:00 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 236880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273594285 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2273594285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.4194947162 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 258262202 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:24:57 PM UTC 24 |
| Finished | Sep 01 08:25:00 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194947162 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.4194947162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3044467816 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 920442803 ps |
| CPU time | 4.17 seconds |
| Started | Sep 01 08:24:57 PM UTC 24 |
| Finished | Sep 01 08:25:02 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044467816 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3044467816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2325034866 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 64745612 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 08:24:57 PM UTC 24 |
| Finished | Sep 01 08:25:00 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325034866 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2325034866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.626755156 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 32095689 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:24:54 PM UTC 24 |
| Finished | Sep 01 08:24:56 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626755156 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.626755156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2360794418 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2323432018 ps |
| CPU time | 7.42 seconds |
| Started | Sep 01 08:25:01 PM UTC 24 |
| Finished | Sep 01 08:25:09 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360794418 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.2360794418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.157406199 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4912530404 ps |
| CPU time | 5.11 seconds |
| Started | Sep 01 08:25:00 PM UTC 24 |
| Finished | Sep 01 08:25:06 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=157406199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_ stress_all_with_rand_reset.157406199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3067640036 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 329240645 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 08:24:56 PM UTC 24 |
| Finished | Sep 01 08:24:58 PM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067640036 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.3067640036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.2687900883 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 327280159 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:24:56 PM UTC 24 |
| Finished | Sep 01 08:24:58 PM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687900883 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.2687900883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.1618419771 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 20912856 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:28 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618419771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1618419771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1210490009 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 64005054 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210490009 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.1210490009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3241149611 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 40071050 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:28 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241149611 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.3241149611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.3897208467 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 111824154 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:27:00 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897208467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3897208467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.591169779 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 125859839 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:27:01 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591169779 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.591169779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.2163607537 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 148713682 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:00 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163607537 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2163607537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.2186164081 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 58849550 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186164081 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.2186164081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.3006008672 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 352382456 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006008672 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.3006008672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.4237594338 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 52990291 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237594338 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.4237594338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.212732884 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 143064079 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212732884 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.212732884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.394260285 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 683983178 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:02 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394260285 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.394260285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.714857513 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1626863423 ps |
| CPU time | 1.99 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:08 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714857513 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.714857513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2853335636 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 837290400 ps |
| CPU time | 2.95 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:30 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853335636 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2853335636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3699523174 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 155199196 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699523174 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3699523174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.3393080877 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 31209723 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393080877 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3393080877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.1572278806 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1449098048 ps |
| CPU time | 4.82 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:21 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572278806 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.1572278806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.4067008213 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 7982170073 ps |
| CPU time | 11.78 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:28 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4067008213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg r_stress_all_with_rand_reset.4067008213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.309031370 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 222707969 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309031370 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.309031370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.513264146 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 177043234 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:26:59 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513264146 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.513264146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.75747718 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 80550306 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75747718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ= pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.75747718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.524656107 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 47197986 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524656107 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.524656107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3289436860 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 29044634 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 206200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289436860 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.3289436860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.2200901844 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 110313601 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200901844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.2200901844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.2534666981 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 34555925 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534666981 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.2534666981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3560015613 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 21392860 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 206188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560015613 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3560015613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.1696836846 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 75756034 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696836846 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.1696836846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.2586448601 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 87419066 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:23 PM UTC 24 |
| Peak memory | 207984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586448601 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.2586448601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.2505211236 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 60902852 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505211236 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2505211236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.2487855570 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 121700307 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487855570 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.2487855570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.3485366157 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 269473031 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485366157 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.3485366157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1559970813 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1110604112 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559970813 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1559970813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.994106684 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 167156118 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 209088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994106684 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.994106684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.607063087 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 67122396 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:27:02 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607063087 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.607063087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.598333808 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2445887568 ps |
| CPU time | 3.95 seconds |
| Started | Sep 01 08:27:05 PM UTC 24 |
| Finished | Sep 01 08:27:10 PM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598333808 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.598333808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.725245411 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 5628870964 ps |
| CPU time | 11.79 seconds |
| Started | Sep 01 08:27:05 PM UTC 24 |
| Finished | Sep 01 08:27:18 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=725245411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr _stress_all_with_rand_reset.725245411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.1558099352 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 62552924 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:23 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558099352 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.1558099352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.1950167419 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 264340483 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:27:04 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950167419 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.1950167419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.1346796478 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 20606818 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:27:06 PM UTC 24 |
| Finished | Sep 01 08:28:01 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346796478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1346796478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.4022850199 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 83099690 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022850199 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.4022850199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1736870868 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 32261874 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:22 PM UTC 24 |
| Peak memory | 205916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736870868 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.1736870868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.2679939622 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 228489549 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679939622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2679939622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2376717621 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 43313501 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376717621 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2376717621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.2293675442 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 35053687 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293675442 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2293675442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.3554200641 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 70336155 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554200641 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.3554200641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.146879281 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 215952549 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:27:05 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146879281 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.146879281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.1871188592 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 80580062 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:27:05 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871188592 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1871188592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.2008766485 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 111048503 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008766485 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2008766485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1210680487 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 150020054 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:23 PM UTC 24 |
| Peak memory | 208208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210680487 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.1210680487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2780233668 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1027573016 ps |
| CPU time | 2.4 seconds |
| Started | Sep 01 08:27:06 PM UTC 24 |
| Finished | Sep 01 08:27:23 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780233668 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2780233668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.364840374 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1064217494 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 08:27:06 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364840374 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.364840374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2761092909 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 129501216 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:23 PM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761092909 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2761092909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.3317151001 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 44476844 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:27:05 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317151001 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3317151001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.679083380 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 2844382798 ps |
| CPU time | 6.46 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:39 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679083380 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.679083380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.2263046682 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 8133425152 ps |
| CPU time | 16.22 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:49 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2263046682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg r_stress_all_with_rand_reset.2263046682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.1736372929 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 234086414 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:27:05 PM UTC 24 |
| Finished | Sep 01 08:27:07 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736372929 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.1736372929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.3623125458 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 127160338 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:27:06 PM UTC 24 |
| Finished | Sep 01 08:27:31 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623125458 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.3623125458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.1793120026 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 60190389 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:27:09 PM UTC 24 |
| Finished | Sep 01 08:27:12 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793120026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.1793120026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.1714628804 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 46923929 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:27:15 PM UTC 24 |
| Finished | Sep 01 08:27:18 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714628804 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.1714628804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2155521925 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 29154721 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:27:11 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155521925 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.2155521925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.2540559328 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 109553489 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:27:14 PM UTC 24 |
| Finished | Sep 01 08:27:23 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540559328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2540559328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.3900190013 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 38229076 ps |
| CPU time | 0.51 seconds |
| Started | Sep 01 08:27:15 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900190013 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3900190013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.27063183 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 66155222 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:27:13 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27063183 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.27063183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.3962395574 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 61009222 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962395574 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.3962395574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.1571635409 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 311393298 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571635409 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.1571635409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.737166496 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 107708492 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737166496 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.737166496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.2977348878 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 109282230 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:27:17 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977348878 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2977348878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.3991765259 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 61795050 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:13 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991765259 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.3991765259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2116090641 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1907944725 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 08:27:09 PM UTC 24 |
| Finished | Sep 01 08:27:13 PM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116090641 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2116090641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1258855081 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 819877894 ps |
| CPU time | 2.81 seconds |
| Started | Sep 01 08:27:09 PM UTC 24 |
| Finished | Sep 01 08:27:14 PM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258855081 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1258855081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.519301386 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 141068253 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:09 PM UTC 24 |
| Finished | Sep 01 08:27:12 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519301386 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.519301386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.4263525006 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 42713962 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263525006 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.4263525006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.696739661 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1545763887 ps |
| CPU time | 5.54 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696739661 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.696739661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.576506799 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 6712473152 ps |
| CPU time | 13.4 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:46 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=576506799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr _stress_all_with_rand_reset.576506799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.3916295521 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 310632848 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916295521 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.3916295521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.1442128722 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 408017864 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:27:08 PM UTC 24 |
| Finished | Sep 01 08:27:17 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442128722 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.1442128722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.3155075600 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 67370167 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155075600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.3155075600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.3173492886 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 90946941 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:27:23 PM UTC 24 |
| Finished | Sep 01 08:27:27 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173492886 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.3173492886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.262143976 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 31480496 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:27 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262143976 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.262143976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.3225101436 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 207615261 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:22 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225101436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3225101436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.3420260691 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 31787241 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:23 PM UTC 24 |
| Finished | Sep 01 08:27:27 PM UTC 24 |
| Peak memory | 206056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420260691 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3420260691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.1375832244 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 65330421 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:27:20 PM UTC 24 |
| Finished | Sep 01 08:27:22 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375832244 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1375832244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.710419703 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 45852949 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:24 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710419703 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.710419703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.3231633618 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 238284068 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231633618 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.3231633618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.533355493 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 164555296 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533355493 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.533355493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.1123383056 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 100894814 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:27:24 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123383056 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1123383056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.1544112757 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 216882573 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:27 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544112757 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.1544112757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2913119117 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1153734318 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:28 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913119117 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2913119117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1063138726 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 824031979 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:29 PM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063138726 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1063138726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.4104049695 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 334126615 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:26 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104049695 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.4104049695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.1080738578 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 40970323 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080738578 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1080738578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.2198092165 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1113268553 ps |
| CPU time | 3.64 seconds |
| Started | Sep 01 08:27:24 PM UTC 24 |
| Finished | Sep 01 08:27:36 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198092165 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.2198092165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.3501432102 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 146110453 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501432102 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.3501432102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.976873977 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 350456654 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:27:18 PM UTC 24 |
| Finished | Sep 01 08:27:26 PM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976873977 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.976873977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.1684666620 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 48901173 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:27 PM UTC 24 |
| Finished | Sep 01 08:27:32 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684666620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.1684666620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.2514993280 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 98180272 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:27:29 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514993280 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.2514993280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3148901031 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 28641209 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:27:28 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 205804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148901031 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.3148901031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.2065729336 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 205392507 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:28 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065729336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2065729336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.3108014848 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 25293445 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:27:29 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 206200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108014848 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3108014848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.1627644720 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 85409393 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:28 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627644720 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1627644720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.2555035759 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 54836418 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:27:30 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555035759 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.2555035759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.3461157713 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 143184284 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:27:24 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461157713 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.3461157713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.2014909526 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 81992077 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:27:24 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014909526 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.2014909526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.3121758548 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 244891880 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:27:30 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121758548 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3121758548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.1639125961 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 387709063 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:27:28 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639125961 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.1639125961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1615719731 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 934257753 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 08:27:27 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615719731 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1615719731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.762596486 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 852517563 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 08:27:27 PM UTC 24 |
| Finished | Sep 01 08:27:35 PM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762596486 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.762596486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.355318304 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 390997047 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:27:28 PM UTC 24 |
| Finished | Sep 01 08:27:34 PM UTC 24 |
| Peak memory | 207876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355318304 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.355318304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.2283495784 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 50842290 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:27:24 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283495784 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2283495784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.707356882 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2431015230 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 08:27:32 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707356882 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.707356882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.1727823759 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 9030887088 ps |
| CPU time | 13.31 seconds |
| Started | Sep 01 08:27:31 PM UTC 24 |
| Finished | Sep 01 08:27:45 PM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1727823759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmg r_stress_all_with_rand_reset.1727823759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.243775932 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 37338307 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:25 PM UTC 24 |
| Finished | Sep 01 08:27:27 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243775932 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.243775932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.2176517689 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 482559206 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:27:27 PM UTC 24 |
| Finished | Sep 01 08:27:33 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176517689 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2176517689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.146290238 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 57223895 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:27:34 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146290238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.146290238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.395113906 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 60693299 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395113906 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.395113906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1567971521 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 39182548 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567971521 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.1567971521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.2404142324 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 393042907 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404142324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.2404142324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2508240316 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 55911927 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508240316 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2508240316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.2717808408 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 89276021 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717808408 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2717808408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.799448552 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 72616884 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 210588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799448552 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.799448552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2792140278 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 88357697 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:33 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 208108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792140278 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.2792140278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1090734019 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 128147703 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:33 PM UTC 24 |
| Finished | Sep 01 08:27:35 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090734019 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1090734019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.2219759324 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 102401129 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 219956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219759324 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.2219759324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.4152694181 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 288694350 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152694181 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.4152694181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.656813761 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 998853260 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 08:27:34 PM UTC 24 |
| Finished | Sep 01 08:27:49 PM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656813761 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.656813761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2794658596 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 846016860 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:50 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794658596 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2794658596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2959049097 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 169371632 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959049097 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2959049097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.3610820492 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 51021734 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:27:33 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610820492 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3610820492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.567974265 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1978559747 ps |
| CPU time | 7.02 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:54 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=567974265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr _stress_all_with_rand_reset.567974265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.287959524 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 265818094 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:33 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287959524 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.287959524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.3737631499 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 190605210 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:27:33 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737631499 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.3737631499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.1939524451 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 39847655 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939524451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1939524451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.1175354692 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 81946025 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 210344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175354692 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.1175354692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2419135061 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 38143295 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419135061 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.2419135061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.4171334341 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 197848450 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171334341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.4171334341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.1023200089 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 58701553 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023200089 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.1023200089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3778904197 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 27589208 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 206080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778904197 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3778904197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.1117341435 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 83717795 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117341435 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.1117341435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.2337357896 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 95213405 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 219620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337357896 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2337357896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.1155097419 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 139842920 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 208160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155097419 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.1155097419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3295972641 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1303651878 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295972641 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3295972641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1470448746 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 871088510 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:39 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470448746 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1470448746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.646523154 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 64393300 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:37 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646523154 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.646523154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.1187448258 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 28376430 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187448258 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1187448258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.2493549959 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 77782296 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493549959 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.2493549959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.393459595 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5287389133 ps |
| CPU time | 15.41 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=393459595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr _stress_all_with_rand_reset.393459595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.2058231638 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 182869584 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058231638 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2058231638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.3955887550 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 332859143 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955887550 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.3955887550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.3608041318 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 35633890 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:27:36 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608041318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.3608041318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.3921456173 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 59692639 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921456173 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.3921456173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1341314922 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 36271159 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:37 PM UTC 24 |
| Finished | Sep 01 08:28:42 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341314922 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.1341314922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1791240966 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 159731165 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791240966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1791240966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.1969153949 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 73249773 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969153949 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1969153949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.507290346 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 38954026 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507290346 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.507290346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.4121449328 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 94572618 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121449328 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.4121449328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.210537225 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 274677782 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:27:36 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210537225 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.210537225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.104731280 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 53985953 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:36 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104731280 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.104731280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3197351428 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 333414354 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197351428 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3197351428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3314029238 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 150840439 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:27:37 PM UTC 24 |
| Finished | Sep 01 08:28:32 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314029238 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.3314029238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3214715343 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 882356492 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 08:27:37 PM UTC 24 |
| Finished | Sep 01 08:28:24 PM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214715343 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3214715343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4149559196 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 903410195 ps |
| CPU time | 2.78 seconds |
| Started | Sep 01 08:27:37 PM UTC 24 |
| Finished | Sep 01 08:28:24 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149559196 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4149559196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2006279014 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 84004263 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:27:37 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006279014 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2006279014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.1884824967 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 33093157 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:27:35 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884824967 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1884824967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.2282990389 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 673429667 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:45 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282990389 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.2282990389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.396340612 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2689732894 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:28:07 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=396340612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr _stress_all_with_rand_reset.396340612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.430614988 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 265721694 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:27:36 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430614988 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.430614988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.2284876366 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 105108092 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:27:36 PM UTC 24 |
| Finished | Sep 01 08:27:38 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284876366 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.2284876366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.4206590516 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 75889097 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:46 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206590516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.4206590516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.1699814793 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 59685144 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699814793 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.1699814793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.2214896035 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 32345736 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 205856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214896035 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.2214896035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.4177085155 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 193645922 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177085155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.4177085155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.2792731695 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 143366280 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792731695 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.2792731695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.1480124775 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 81725306 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 206204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480124775 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1480124775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.3165606764 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 41628203 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165606764 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.3165606764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.3201214062 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 115147203 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:46 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201214062 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.3201214062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1006356171 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 81566368 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006356171 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1006356171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.336991302 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 126772437 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336991302 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.336991302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1652774342 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 226219025 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652774342 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.1652774342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2080517496 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1031422127 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:49 PM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080517496 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2080517496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1578282000 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 852855818 ps |
| CPU time | 2.93 seconds |
| Started | Sep 01 08:27:39 PM UTC 24 |
| Finished | Sep 01 08:27:44 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578282000 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1578282000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2639903467 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 93400892 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:42 PM UTC 24 |
| Peak memory | 207904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639903467 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2639903467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.3422383256 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 31666015 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:46 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422383256 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3422383256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.714523391 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 40068675 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:27:40 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714523391 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.714523391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1441756143 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 253455535 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:46 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441756143 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1441756143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.4204334718 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 154857350 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:38 PM UTC 24 |
| Finished | Sep 01 08:27:46 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204334718 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.4204334718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.145418285 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 57241987 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:05 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145418285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.145418285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.2425493063 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 78672977 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:25:04 PM UTC 24 |
| Finished | Sep 01 08:25:06 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425493063 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.2425493063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1638414470 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 38502821 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:25:04 PM UTC 24 |
| Finished | Sep 01 08:25:06 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638414470 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.1638414470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.212938017 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1019685792 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:25:04 PM UTC 24 |
| Finished | Sep 01 08:25:06 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212938017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.212938017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.2352783709 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 84330966 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:04 PM UTC 24 |
| Finished | Sep 01 08:25:06 PM UTC 24 |
| Peak memory | 206000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352783709 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2352783709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.2572967688 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 25710513 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:25:04 PM UTC 24 |
| Finished | Sep 01 08:25:06 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572967688 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.2572967688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.1277793119 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 54634428 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:05 PM UTC 24 |
| Finished | Sep 01 08:25:07 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277793119 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.1277793119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3164220536 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 228567039 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:05 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164220536 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.3164220536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.1572778701 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 26264419 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:25:01 PM UTC 24 |
| Finished | Sep 01 08:25:03 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572778701 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1572778701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.3794829929 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 191216400 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:25:05 PM UTC 24 |
| Finished | Sep 01 08:25:07 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794829929 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.3794829929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.2877266829 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 607287338 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 08:25:06 PM UTC 24 |
| Finished | Sep 01 08:25:09 PM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877266829 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2877266829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.994887351 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 223340906 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 08:25:04 PM UTC 24 |
| Finished | Sep 01 08:25:07 PM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994887351 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.994887351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1024180458 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1316673429 ps |
| CPU time | 3.6 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:07 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024180458 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.1024180458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.761559232 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1121100740 ps |
| CPU time | 4.43 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:08 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761559232 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.761559232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.195397401 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 96816843 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:05 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195397401 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.195397401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.319076978 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 29755668 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:25:01 PM UTC 24 |
| Finished | Sep 01 08:25:03 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319076978 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.319076978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.2867740473 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 90596679 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:25:06 PM UTC 24 |
| Finished | Sep 01 08:25:09 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867740473 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.2867740473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2773063649 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4786105165 ps |
| CPU time | 27.93 seconds |
| Started | Sep 01 08:25:06 PM UTC 24 |
| Finished | Sep 01 08:25:36 PM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2773063649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr _stress_all_with_rand_reset.2773063649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1940713961 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 164126044 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:05 PM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940713961 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1940713961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.1640167480 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 91187320 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 08:25:02 PM UTC 24 |
| Finished | Sep 01 08:25:05 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640167480 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.1640167480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.2236529893 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 43632972 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:51 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236529893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2236529893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.1750816838 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 67169014 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750816838 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.1750816838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3609557760 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 38082792 ps |
| CPU time | 0.53 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 205448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609557760 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.3609557760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.790497213 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 392196474 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790497213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.790497213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.342466313 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 76107956 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 206208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342466313 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.342466313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3339257176 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 47221351 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339257176 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3339257176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.1570119721 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 51622353 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570119721 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.1570119721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2497437168 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 413218453 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:27:42 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497437168 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.2497437168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.1336057277 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 85555515 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:27:42 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336057277 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1336057277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2428351698 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 101977084 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428351698 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2428351698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.873294306 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 143243499 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873294306 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.873294306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2323927326 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 909126655 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:53 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323927326 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2323927326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3164362974 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1044460385 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:53 PM UTC 24 |
| Peak memory | 210044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164362974 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3164362974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2557947672 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 64955663 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557947672 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2557947672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3844780898 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 47125815 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:41 PM UTC 24 |
| Finished | Sep 01 08:27:43 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844780898 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3844780898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.466424778 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2372618523 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:28:04 PM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466424778 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.466424778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.3910454888 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2445022881 ps |
| CPU time | 4.84 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:28:07 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3910454888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmg r_stress_all_with_rand_reset.3910454888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.1426764570 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 110817070 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:27:42 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426764570 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.1426764570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.1262717209 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 121761653 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:42 PM UTC 24 |
| Finished | Sep 01 08:27:47 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262717209 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.1262717209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.4115636579 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 23762505 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:27:46 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115636579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.4115636579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3447979169 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 68254258 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447979169 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.3447979169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3059328177 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 41960728 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059328177 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.3059328177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.1039049830 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 110312546 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039049830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1039049830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.3860546201 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 55197378 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860546201 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3860546201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.368613221 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 76051554 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368613221 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.368613221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.2204922425 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 52363358 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204922425 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.2204922425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.1988764378 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 57132993 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:45 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988764378 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.1988764378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.3050093881 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 120772472 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:45 PM UTC 24 |
| Finished | Sep 01 08:27:48 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050093881 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.3050093881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1752549368 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 111502883 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 220144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752549368 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1752549368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2223413881 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 31502549 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223413881 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.2223413881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4044873564 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 772293398 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 08:27:47 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044873564 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4044873564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.499091104 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1240146418 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 08:27:47 PM UTC 24 |
| Finished | Sep 01 08:28:04 PM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499091104 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.499091104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2026120519 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 418614866 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:48 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026120519 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2026120519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.2172339925 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 51206080 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:27:44 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172339925 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.2172339925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.3648021885 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 68873470 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648021885 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.3648021885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.181516424 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6154922700 ps |
| CPU time | 21.04 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:28:19 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=181516424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr _stress_all_with_rand_reset.181516424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.2029239684 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 285455200 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:27:45 PM UTC 24 |
| Finished | Sep 01 08:27:49 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029239684 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.2029239684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.636467991 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 210031653 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:27:46 PM UTC 24 |
| Finished | Sep 01 08:28:19 PM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636467991 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.636467991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2188066808 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 32156007 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188066808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2188066808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.1229340988 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 53638537 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:27:51 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229340988 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.1229340988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3542900644 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 30725967 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542900644 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.3542900644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.2301772400 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 200289513 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:50 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301772400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.2301772400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2762945831 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 65318258 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:27:51 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762945831 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2762945831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.3056999473 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 89409975 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056999473 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3056999473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.1678030350 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 43828872 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:27:52 PM UTC 24 |
| Finished | Sep 01 08:28:04 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678030350 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.1678030350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.1260137731 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 111664596 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260137731 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.1260137731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.772920478 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 48810256 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772920478 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.772920478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3630010802 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 130860704 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:51 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630010802 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3630010802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.4187306418 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 85699328 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187306418 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.4187306418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3979971038 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 969864794 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:53 PM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979971038 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3979971038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2648809969 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 890127399 ps |
| CPU time | 2.85 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:54 PM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648809969 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2648809969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2523514344 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 67855305 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523514344 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2523514344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.1474974573 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 31501805 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474974573 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1474974573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.88997730 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2599504968 ps |
| CPU time | 4 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:01 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88997730 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.88997730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1902904561 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 7707324436 ps |
| CPU time | 6.13 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1902904561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg r_stress_all_with_rand_reset.1902904561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.442807182 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 91618703 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442807182 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.442807182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4247407320 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 191609785 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:27:49 PM UTC 24 |
| Finished | Sep 01 08:27:52 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247407320 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.4247407320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2245980377 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 135124034 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245980377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2245980377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2646202178 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 89744227 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:27:54 PM UTC 24 |
| Finished | Sep 01 08:27:57 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646202178 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.2646202178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2541005098 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 39110831 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541005098 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.2541005098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.3301691307 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 233421055 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:19 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301691307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3301691307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.2553740766 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 23717915 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553740766 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2553740766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3992215555 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 47962771 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992215555 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3992215555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.3340274038 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 54505284 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:27:55 PM UTC 24 |
| Finished | Sep 01 08:27:57 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340274038 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.3340274038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.2625191340 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 310233378 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625191340 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.2625191340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.559867722 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 45869316 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559867722 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.559867722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2270845264 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 161053239 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:27:54 PM UTC 24 |
| Finished | Sep 01 08:27:57 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270845264 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2270845264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.4011808578 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 165135575 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:19 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011808578 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.4011808578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.942790567 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1088907141 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:59 PM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942790567 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.942790567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1448546433 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 831713137 ps |
| CPU time | 2.38 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:28:00 PM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448546433 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1448546433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1915133053 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 63293306 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915133053 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1915133053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.71633932 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 66054171 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71633932 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.71633932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.2407133146 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3167956781 ps |
| CPU time | 3.84 seconds |
| Started | Sep 01 08:27:56 PM UTC 24 |
| Finished | Sep 01 08:28:01 PM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407133146 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2407133146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3666800515 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2123658318 ps |
| CPU time | 6.76 seconds |
| Started | Sep 01 08:27:55 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3666800515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg r_stress_all_with_rand_reset.3666800515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.1614064448 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 170037330 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614064448 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.1614064448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.1271686843 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 75724512 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:27:53 PM UTC 24 |
| Finished | Sep 01 08:27:58 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271686843 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1271686843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.4237542381 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 38450779 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237542381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.4237542381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.1792623745 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 75131020 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792623745 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.1792623745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3149131346 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 42108054 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149131346 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.3149131346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.3201085683 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 109875280 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201085683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3201085683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.3869967832 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 34846589 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869967832 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3869967832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.3523145127 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 23098853 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523145127 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3523145127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.2626870558 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 41810533 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:28:00 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626870558 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.2626870558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.3292457999 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 231864591 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:27:58 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292457999 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.3292457999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.1031055859 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 57434579 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:27:58 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031055859 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1031055859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.2752984085 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 106714187 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:28:00 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 219848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752984085 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2752984085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2320767877 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 148739348 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320767877 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.2320767877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1157885092 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 899461779 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:04 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157885092 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1157885092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.146029377 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 868785421 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:04 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146029377 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.146029377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3706141441 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 86873185 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:59 PM UTC 24 |
| Finished | Sep 01 08:28:02 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706141441 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3706141441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.4050928978 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 68187050 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:27:56 PM UTC 24 |
| Finished | Sep 01 08:27:57 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050928978 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.4050928978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.23386602 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1446623215 ps |
| CPU time | 5.09 seconds |
| Started | Sep 01 08:28:02 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23386602 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.23386602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.791268673 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 7010607051 ps |
| CPU time | 8.31 seconds |
| Started | Sep 01 08:28:01 PM UTC 24 |
| Finished | Sep 01 08:28:11 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=791268673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr _stress_all_with_rand_reset.791268673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.3140432361 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 148465601 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:27:58 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140432361 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3140432361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.4164129607 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 201696047 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:27:58 PM UTC 24 |
| Finished | Sep 01 08:28:03 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164129607 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.4164129607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1204861822 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 25021913 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204861822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.1204861822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.1151314090 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 50835086 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151314090 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.1151314090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.6579912 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 30122707 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6579912 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.6579912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.269169177 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 108774178 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 208132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269169177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.269169177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.1660636922 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 39191554 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660636922 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.1660636922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.3298503456 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 31681390 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298503456 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3298503456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.3012662982 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 54692623 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012662982 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.3012662982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.3069464458 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 336122213 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069464458 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.3069464458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.724920517 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 32013542 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:04 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724920517 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.724920517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1916643608 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 120789642 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 220132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916643608 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1916643608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2027951589 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 267070266 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027951589 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.2027951589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1331015930 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 845366686 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:06 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331015930 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1331015930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.233240508 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1182091097 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:06 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233240508 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.233240508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1319201266 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 54346409 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319201266 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1319201266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.821893063 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 32150629 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821893063 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.821893063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.488507749 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1942787659 ps |
| CPU time | 3.03 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:10 PM UTC 24 |
| Peak memory | 210412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488507749 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.488507749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3323334190 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 6251034582 ps |
| CPU time | 14.05 seconds |
| Started | Sep 01 08:28:04 PM UTC 24 |
| Finished | Sep 01 08:28:21 PM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3323334190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg r_stress_all_with_rand_reset.3323334190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.338637864 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 168840076 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338637864 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.338637864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.4174813618 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 327556090 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:28:03 PM UTC 24 |
| Finished | Sep 01 08:28:05 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174813618 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.4174813618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.3061066927 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 54654837 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061066927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3061066927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.3117040399 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 125193272 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117040399 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.3117040399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3628085413 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 32081568 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:41 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628085413 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.3628085413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.2481016383 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 314904688 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:41 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481016383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2481016383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.1946330854 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 66669259 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946330854 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.1946330854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.3049081015 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 46968894 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:21 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049081015 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3049081015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.2678544961 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 42771195 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678544961 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.2678544961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3717904314 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 279547386 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717904314 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.3717904314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.2620406659 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 106383294 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620406659 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2620406659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.3785307815 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 158704044 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785307815 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3785307815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.199118694 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 237650991 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:21 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199118694 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.199118694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1156210546 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1292242132 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:09 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156210546 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1156210546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3497158500 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 912933645 ps |
| CPU time | 3.09 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:20 PM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497158500 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3497158500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.411197713 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 176659703 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:41 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411197713 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.411197713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2076915174 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 150456615 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076915174 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2076915174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.135980393 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 1700990564 ps |
| CPU time | 2.58 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:14 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135980393 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.135980393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3389402299 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 13566317091 ps |
| CPU time | 19.08 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:31 PM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3389402299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg r_stress_all_with_rand_reset.3389402299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.408518409 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 244826825 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:09 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408518409 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.408518409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.657632868 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 64923557 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:28:05 PM UTC 24 |
| Finished | Sep 01 08:28:08 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657632868 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.657632868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.3885256670 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 185883890 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 208988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885256670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3885256670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.3829149924 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 73492804 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:14 PM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829149924 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.3829149924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.403287455 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 39690691 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:07 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403287455 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.403287455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.184073846 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 201311384 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:28:08 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184073846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.184073846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3772347653 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 23817361 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:08 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772347653 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3772347653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.2449318833 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 27678499 ps |
| CPU time | 0.54 seconds |
| Started | Sep 01 08:28:08 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449318833 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2449318833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.427737801 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 53390337 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:14 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427737801 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.427737801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2448737392 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 215499926 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448737392 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.2448737392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1948555524 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 191601101 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948555524 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1948555524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.2004309617 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 111763394 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:15 PM UTC 24 |
| Peak memory | 219984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004309617 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2004309617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.2657243092 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 129349133 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:08 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657243092 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.2657243092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.689241044 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 850527200 ps |
| CPU time | 2.97 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:24 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689241044 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.689241044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2252485068 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 1428337196 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:23 PM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252485068 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2252485068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.6188503 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 540745167 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:28:07 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6188503 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.6188503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.418329253 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 68754038 ps |
| CPU time | 0.58 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 209088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418329253 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.418329253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.2142326287 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1382867487 ps |
| CPU time | 5.5 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142326287 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.2142326287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1849971796 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2589084053 ps |
| CPU time | 8.02 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1849971796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmg r_stress_all_with_rand_reset.1849971796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.456321522 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 135551194 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 208020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456321522 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.456321522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2952672281 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 376221344 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:28:06 PM UTC 24 |
| Finished | Sep 01 08:28:22 PM UTC 24 |
| Peak memory | 209244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952672281 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.2952672281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.2659263364 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 40668445 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659263364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2659263364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.299141906 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 73048459 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:28:13 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299141906 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.299141906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.887572104 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 31042751 ps |
| CPU time | 0.52 seconds |
| Started | Sep 01 08:28:11 PM UTC 24 |
| Finished | Sep 01 08:28:14 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887572104 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.887572104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1812741304 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 386325945 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:28:13 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812741304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1812741304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.1904204939 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 49289742 ps |
| CPU time | 0.55 seconds |
| Started | Sep 01 08:28:13 PM UTC 24 |
| Finished | Sep 01 08:28:15 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904204939 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1904204939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2463324197 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 141948531 ps |
| CPU time | 0.56 seconds |
| Started | Sep 01 08:28:13 PM UTC 24 |
| Finished | Sep 01 08:28:15 PM UTC 24 |
| Peak memory | 206108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463324197 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2463324197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.4270077585 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 208944727 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270077585 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.4270077585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.217979567 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 72550216 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217979567 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.217979567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.26930361 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 109709865 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:28:13 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26930361 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.26930361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.1732851142 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 118592441 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:28:13 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 208168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732851142 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.1732851142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.91020817 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 795221810 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:15 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91020817 -ass ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.91020817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1244067485 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 895076517 ps |
| CPU time | 2.47 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:15 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244067485 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1244067485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1397241709 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 154830142 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:28:10 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397241709 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1397241709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.2865256861 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 64178547 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:12 PM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865256861 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.2865256861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.2545137574 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 414693246 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545137574 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2545137574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.4096538565 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 62466530 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:28:09 PM UTC 24 |
| Finished | Sep 01 08:28:13 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096538565 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.4096538565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2719513404 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 56986375 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719513404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2719513404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.3639213497 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 51958238 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:28:15 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639213497 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.3639213497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1370036222 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 30355370 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370036222 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.1370036222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3222575846 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 107455341 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:28:15 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222575846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3222575846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1341194073 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 86821971 ps |
| CPU time | 0.57 seconds |
| Started | Sep 01 08:28:15 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341194073 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.1341194073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.463978050 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 86084367 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 08:28:15 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463978050 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.463978050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.398838887 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 71802358 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:16 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398838887 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.398838887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.2105628650 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 218365933 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105628650 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.2105628650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2321988597 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 38056692 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321988597 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2321988597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1675677887 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 164340269 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:28:15 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675677887 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1675677887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2426513934 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 120546093 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426513934 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.2426513934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1016394026 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 897763516 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:18 PM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016394026 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1016394026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2524287626 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 975910824 ps |
| CPU time | 2.59 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:19 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524287626 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2524287626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.570966236 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 138620548 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570966236 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.570966236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.783712877 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2953565986 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 08:28:16 PM UTC 24 |
| Finished | Sep 01 08:28:21 PM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783712877 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.783712877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.2795062451 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 6583195680 ps |
| CPU time | 12.81 seconds |
| Started | Sep 01 08:28:16 PM UTC 24 |
| Finished | Sep 01 08:28:30 PM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2795062451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmg r_stress_all_with_rand_reset.2795062451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.771909287 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 186399310 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771909287 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.771909287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.2511779767 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 545575519 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:28:14 PM UTC 24 |
| Finished | Sep 01 08:28:17 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511779767 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.2511779767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.315070671 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 33617721 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:10 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315070671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.315070671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.371602592 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 94731149 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:10 PM UTC 24 |
| Finished | Sep 01 08:25:12 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371602592 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.371602592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.416825291 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 28658948 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:10 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416825291 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.416825291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3870802475 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 379303013 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 08:25:09 PM UTC 24 |
| Finished | Sep 01 08:25:12 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870802475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3870802475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.277436852 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 61598348 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:25:09 PM UTC 24 |
| Finished | Sep 01 08:25:12 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277436852 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.277436852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3004226692 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 47366885 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:09 PM UTC 24 |
| Finished | Sep 01 08:25:12 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004226692 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3004226692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.2078236822 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 49689707 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:10 PM UTC 24 |
| Finished | Sep 01 08:25:12 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078236822 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.2078236822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2215337263 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 82761923 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:25:07 PM UTC 24 |
| Finished | Sep 01 08:25:09 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215337263 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.2215337263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.558773265 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 57329337 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:06 PM UTC 24 |
| Finished | Sep 01 08:25:08 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558773265 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.558773265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2414882098 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 98602874 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:25:10 PM UTC 24 |
| Finished | Sep 01 08:25:12 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414882098 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2414882098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.836229685 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 253293187 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:11 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836229685 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.836229685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.944327605 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1247540969 ps |
| CPU time | 3.63 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:13 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944327605 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.944327605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1756393149 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 823766705 ps |
| CPU time | 5.51 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:15 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756393149 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1756393149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2032476362 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 103729993 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:11 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032476362 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2032476362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1032577386 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 31973420 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:25:06 PM UTC 24 |
| Finished | Sep 01 08:25:09 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032577386 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1032577386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2066831138 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1926036693 ps |
| CPU time | 5.09 seconds |
| Started | Sep 01 08:25:11 PM UTC 24 |
| Finished | Sep 01 08:25:17 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066831138 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2066831138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.4152654309 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4831719584 ps |
| CPU time | 25.5 seconds |
| Started | Sep 01 08:25:11 PM UTC 24 |
| Finished | Sep 01 08:25:38 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4152654309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr _stress_all_with_rand_reset.4152654309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.4208555875 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 182302033 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 08:25:07 PM UTC 24 |
| Finished | Sep 01 08:25:09 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208555875 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.4208555875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3796187673 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 391819344 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 08:25:08 PM UTC 24 |
| Finished | Sep 01 08:25:11 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796187673 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3796187673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3549509202 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 47834528 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:25:12 PM UTC 24 |
| Finished | Sep 01 08:25:15 PM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549509202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3549509202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2652940876 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 63895211 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:15 PM UTC 24 |
| Finished | Sep 01 08:25:17 PM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652940876 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.2652940876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2119386660 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 42533929 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:25:14 PM UTC 24 |
| Finished | Sep 01 08:25:16 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119386660 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.2119386660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.711823315 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 560030000 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:25:14 PM UTC 24 |
| Finished | Sep 01 08:25:16 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711823315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.711823315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.1494783797 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 49543528 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:25:15 PM UTC 24 |
| Finished | Sep 01 08:25:17 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494783797 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.1494783797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3498514481 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 44479034 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:25:14 PM UTC 24 |
| Finished | Sep 01 08:25:16 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498514481 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3498514481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3961992286 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 112449335 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:25:15 PM UTC 24 |
| Finished | Sep 01 08:25:17 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961992286 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.3961992286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.347765679 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 344156460 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:25:11 PM UTC 24 |
| Finished | Sep 01 08:25:14 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347765679 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.347765679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1827902665 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 121181769 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:25:11 PM UTC 24 |
| Finished | Sep 01 08:25:13 PM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827902665 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1827902665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2595646680 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 99675052 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:25:15 PM UTC 24 |
| Finished | Sep 01 08:25:18 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595646680 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.2595646680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.86778077 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 176074876 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:25:14 PM UTC 24 |
| Finished | Sep 01 08:25:16 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86778077 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.86778077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2696942967 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1285258690 ps |
| CPU time | 3.81 seconds |
| Started | Sep 01 08:25:12 PM UTC 24 |
| Finished | Sep 01 08:25:17 PM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696942967 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2696942967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.940926999 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1016446557 ps |
| CPU time | 2.76 seconds |
| Started | Sep 01 08:25:12 PM UTC 24 |
| Finished | Sep 01 08:25:16 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940926999 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.940926999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.301257808 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 53455435 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:25:12 PM UTC 24 |
| Finished | Sep 01 08:25:15 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301257808 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.301257808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.354105454 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 29021573 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:11 PM UTC 24 |
| Finished | Sep 01 08:25:13 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354105454 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.354105454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.194739361 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3432681858 ps |
| CPU time | 7.99 seconds |
| Started | Sep 01 08:25:17 PM UTC 24 |
| Finished | Sep 01 08:25:26 PM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194739361 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.194739361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1793581344 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2919422216 ps |
| CPU time | 16.04 seconds |
| Started | Sep 01 08:25:15 PM UTC 24 |
| Finished | Sep 01 08:25:33 PM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1793581344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr _stress_all_with_rand_reset.1793581344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3878815143 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 332255678 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 08:25:12 PM UTC 24 |
| Finished | Sep 01 08:25:15 PM UTC 24 |
| Peak memory | 208224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878815143 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3878815143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.1282468930 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 110118613 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:25:12 PM UTC 24 |
| Finished | Sep 01 08:25:15 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282468930 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.1282468930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1691462706 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 254591885 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:21 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691462706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1691462706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1707803940 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 63325509 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:25:21 PM UTC 24 |
| Finished | Sep 01 08:25:23 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707803940 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.1707803940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2879382215 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 32544151 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:21 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879382215 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.2879382215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2723881886 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 169258282 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:22 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723881886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2723881886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2842535226 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 43734117 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:25:19 PM UTC 24 |
| Finished | Sep 01 08:25:22 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842535226 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2842535226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2254552787 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 106953166 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:22 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254552787 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2254552787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3034082143 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 59377308 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:25:21 PM UTC 24 |
| Finished | Sep 01 08:25:23 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034082143 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.3034082143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.823586089 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 68650439 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:25:17 PM UTC 24 |
| Finished | Sep 01 08:25:19 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823586089 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.823586089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.711111700 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 84212161 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 08:25:17 PM UTC 24 |
| Finished | Sep 01 08:25:20 PM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711111700 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.711111700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.2399056906 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 160978032 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:25:21 PM UTC 24 |
| Finished | Sep 01 08:25:23 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399056906 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2399056906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2758150890 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 203908983 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:23 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758150890 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.2758150890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2369915750 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1249006769 ps |
| CPU time | 4.03 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:25 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369915750 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2369915750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.358549592 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 866305108 ps |
| CPU time | 5.22 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:26 PM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358549592 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.358549592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2998765203 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 70082398 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:25:18 PM UTC 24 |
| Finished | Sep 01 08:25:22 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998765203 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2998765203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2483281390 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 30030755 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:25:17 PM UTC 24 |
| Finished | Sep 01 08:25:19 PM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483281390 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2483281390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3833286437 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 43614171 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:25:21 PM UTC 24 |
| Finished | Sep 01 08:25:23 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833286437 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.3833286437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3318991635 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4350118015 ps |
| CPU time | 10.68 seconds |
| Started | Sep 01 08:25:21 PM UTC 24 |
| Finished | Sep 01 08:25:33 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3318991635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr _stress_all_with_rand_reset.3318991635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4064615462 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 29870865 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:25:17 PM UTC 24 |
| Finished | Sep 01 08:25:20 PM UTC 24 |
| Peak memory | 208236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064615462 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.4064615462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3946665729 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 385046368 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 08:25:17 PM UTC 24 |
| Finished | Sep 01 08:25:20 PM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946665729 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.3946665729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.2036490079 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 26328192 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:25:23 PM UTC 24 |
| Finished | Sep 01 08:25:26 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036490079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.2036490079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.4006414670 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 70196902 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:25:26 PM UTC 24 |
| Finished | Sep 01 08:25:29 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006414670 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.4006414670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1577581160 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 30692634 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:25:25 PM UTC 24 |
| Finished | Sep 01 08:25:27 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577581160 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.1577581160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1346470598 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 112631707 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 08:25:25 PM UTC 24 |
| Finished | Sep 01 08:25:28 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346470598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1346470598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.2820672817 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 51770261 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:25:26 PM UTC 24 |
| Finished | Sep 01 08:25:28 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820672817 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2820672817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.3108086525 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 32196484 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:25:25 PM UTC 24 |
| Finished | Sep 01 08:25:27 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108086525 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.3108086525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.731680045 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 42612718 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731680045 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.731680045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.856733036 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 144714244 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 08:25:22 PM UTC 24 |
| Finished | Sep 01 08:25:25 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856733036 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.856733036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.4051387057 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 67647929 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:25:22 PM UTC 24 |
| Finished | Sep 01 08:25:24 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051387057 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.4051387057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2076483937 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 101570067 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 08:25:26 PM UTC 24 |
| Finished | Sep 01 08:25:29 PM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076483937 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2076483937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.706742983 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 77565246 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:25:25 PM UTC 24 |
| Finished | Sep 01 08:25:27 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706742983 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.706742983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2265132932 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1310186196 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 08:25:23 PM UTC 24 |
| Finished | Sep 01 08:25:28 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265132932 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2265132932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3376376545 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 974347612 ps |
| CPU time | 4.13 seconds |
| Started | Sep 01 08:25:25 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376376545 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3376376545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3957909498 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 165232495 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:25:25 PM UTC 24 |
| Finished | Sep 01 08:25:27 PM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957909498 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3957909498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.276251561 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 260920762 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:25:22 PM UTC 24 |
| Finished | Sep 01 08:25:24 PM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276251561 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.276251561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1629594353 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4221129167 ps |
| CPU time | 5.68 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:35 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629594353 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1629594353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.593490288 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 174538326 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 08:25:23 PM UTC 24 |
| Finished | Sep 01 08:25:26 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593490288 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.593490288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.80726172 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 546286960 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 08:25:23 PM UTC 24 |
| Finished | Sep 01 08:25:26 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80726172 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.80726172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2036421519 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 25337251 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036421519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2036421519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2190199376 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 80051873 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190199376 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.2190199376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2210572453 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 39166801 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:25:29 PM UTC 24 |
| Finished | Sep 01 08:25:31 PM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210572453 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.2210572453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.3465327462 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 290915446 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:25:30 PM UTC 24 |
| Finished | Sep 01 08:25:33 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465327462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3465327462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.315184486 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 50330021 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:25:30 PM UTC 24 |
| Finished | Sep 01 08:25:33 PM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315184486 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.315184486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3035199393 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 52431822 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:25:30 PM UTC 24 |
| Finished | Sep 01 08:25:33 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035199393 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3035199393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.666789350 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 64024160 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666789350 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.666789350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1820127380 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 371658852 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:31 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820127380 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.1820127380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2882392979 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 27450409 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882392979 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2882392979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.4189521796 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 156172948 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189521796 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.4189521796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1117195714 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 416906820 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 08:25:30 PM UTC 24 |
| Finished | Sep 01 08:25:33 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117195714 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.1117195714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.911985115 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1171098073 ps |
| CPU time | 3.62 seconds |
| Started | Sep 01 08:25:29 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911985115 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.911985115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.679925430 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1497581247 ps |
| CPU time | 3.55 seconds |
| Started | Sep 01 08:25:29 PM UTC 24 |
| Finished | Sep 01 08:25:34 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679925430 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.679925430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3855133263 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 65325457 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:25:29 PM UTC 24 |
| Finished | Sep 01 08:25:31 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855133263 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3855133263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.716372783 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 30314481 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716372783 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.716372783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.888662113 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 864904312 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:36 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888662113 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.888662113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1031212406 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4156514563 ps |
| CPU time | 6.43 seconds |
| Started | Sep 01 08:25:32 PM UTC 24 |
| Finished | Sep 01 08:25:40 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1031212406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr _stress_all_with_rand_reset.1031212406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1450389063 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 79369362 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450389063 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1450389063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2777896967 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 304507327 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 08:25:28 PM UTC 24 |
| Finished | Sep 01 08:25:31 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777896967 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.2777896967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest |
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