Unified Coverage Report :: Module :: pwrmgr_cdc

Module : pwrmgr_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cdc	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_ack_pwrdn_sync	100.00	100.00				100.00
u_ack_pwrup_sync	100.00	100.00				100.00
u_ast_sync	100.00	100.00				100.00
u_clr_req_sync	100.00	100.00				100.00
u_ext_req_sync	100.00	100.00				100.00
u_int_fsm_invalid_sync	100.00	100.00				100.00
u_ip_clk_en_sync	100.00	100.00				100.00
u_ip_clk_status_sync	100.00	100.00				100.00
u_pwrup_chg_sync	100.00	100.00				100.00
u_req_pwrdn_sync	100.00	100.00				100.00
u_req_pwrup_sync	100.00	100.00				100.00
u_scdc_sync	100.00	100.00	100.00			100.00	100.00
u_sleeping_sync	100.00	100.00				100.00
u_slow_cdc_sync	100.00	100.00	100.00			100.00	100.00
u_slow_ext_req_sync	100.00	100.00				100.00
u_sync_flash_idle	100.00	100.00				100.00
u_sync_otp	100.00	100.00				100.00
u_sync_rom_ctrl	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_cdc

	Line No.	Total	Covered	Percent
TOTAL		31	31	100.00
ALWAYS	151	3	3	100.00
ALWAYS	161	4	4	100.00
ALWAYS	173	16	16	100.00
ALWAYS	263	3	3	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	4	4	100.00

150                       always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
151        1/1              if (!rst_slow_ni) begin
           Tests:       T1 T2 T3 
152        1/1                slow_ast_q2 <= PWR_AST_RSP_SYNC_DEFAULT;
           Tests:       T1 T2 T3 
153                         end else begin
154        1/1                slow_ast_q2 <= slow_ast_q;
           Tests:       T1 T2 T3 
155                         end
156                       end
157                     
158                       // if possible, we should simulate below with random delays through
159                       // flop_2sync
160                       always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
161        1/1              if (!rst_slow_ni) begin
           Tests:       T1 T2 T3 
162        1/1                slow_ast_o <= PWR_AST_RSP_SYNC_DEFAULT;
           Tests:       T1 T2 T3 
163        1/1              end else if (slow_ast_q2 == slow_ast_q) begin
           Tests:       T1 T2 T3 
164                           // Output only updates whenever sync and delayed outputs both agree.
165                           // If there are delays in sync, this will result in a 1 cycle difference
166                           // and the output will hold the previous value
167        1/1                slow_ast_o <= slow_ast_q2;
           Tests:       T1 T2 T3 
168                         end
                        MISSING_ELSE
169                       end
170                     
171                       // only register configurations can be sync'd using slow_cdc_sync
172                       always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
173        1/1              if (!rst_slow_ni) begin
           Tests:       T1 T2 T3 
174        1/1                slow_wakeup_en_o <= '0;
           Tests:       T1 T2 T3 
175        1/1                slow_reset_en_o <= '0;
           Tests:       T1 T2 T3 
176        1/1                slow_main_pd_no <= '1;
           Tests:       T1 T2 T3 
177        1/1                slow_io_clk_en_o <= '0;
           Tests:       T1 T2 T3 
178        1/1                slow_core_clk_en_o <= '0;
           Tests:       T1 T2 T3 
179        1/1                slow_usb_clk_en_lp_o <= '0;
           Tests:       T1 T2 T3 
180        1/1                slow_usb_clk_en_active_o <= 1'b1;
           Tests:       T1 T2 T3 
181        1/1              end else if (slow_cdc_sync) begin
           Tests:       T1 T2 T3 
182        1/1                slow_wakeup_en_o <= wakeup_en_i;
           Tests:       T1 T2 T3 
183        1/1                slow_reset_en_o <= reset_en_i;
           Tests:       T1 T2 T3 
184        1/1                slow_main_pd_no <= main_pd_ni;
           Tests:       T1 T2 T3 
185        1/1                slow_io_clk_en_o <= io_clk_en_i;
           Tests:       T1 T2 T3 
186        1/1                slow_core_clk_en_o <= core_clk_en_i;
           Tests:       T1 T2 T3 
187        1/1                slow_usb_clk_en_lp_o <= usb_clk_en_lp_i;
           Tests:       T1 T2 T3 
188        1/1                slow_usb_clk_en_active_o <= usb_clk_en_active_i;
           Tests:       T1 T2 T3 
189                         end
                        MISSING_ELSE
190                       end
191                     
192                       ////////////////////////////////
193                       // Sync from clk_slow_i to clk_i
194                       ////////////////////////////////
195                     
196                       logic pwrup_cause_toggle_q, pwrup_cause_toggle_q2;
197                       logic pwrup_cause_chg;
198                     
199                       prim_flop_2sync # (
200                         .Width(1)
201                       ) u_req_pwrup_sync (
202                         .clk_i,
203                         .rst_ni,
204                         .d_i(slow_req_pwrup_i),
205                         .q_o(req_pwrup_o)
206                       );
207                     
208                       prim_flop_2sync # (
209                         .Width(1)
210                       ) u_ack_pwrdn_sync (
211                         .clk_i,
212                         .rst_ni,
213                         .d_i(slow_ack_pwrdn_i),
214                         .q_o(ack_pwrdn_o)
215                       );
216                     
217                       prim_flop_2sync # (
218                         .Width(1)
219                       ) u_int_fsm_invalid_sync (
220                         .clk_i,
221                         .rst_ni,
222                         .d_i(slow_fsm_invalid_i),
223                         .q_o(fsm_invalid_o)
224                       );
225                     
226                       prim_flop_2sync # (
227                         .Width(1)
228                       ) u_pwrup_chg_sync (
229                         .clk_i,
230                         .rst_ni,
231                         .d_i(slow_pwrup_cause_toggle_i),
232                         .q_o(pwrup_cause_toggle_q)
233                       );
234                     
235                       prim_flop_2sync # (
236                         .Width(1)
237                       ) u_ip_clk_en_sync (
238                         .clk_i,
239                         .rst_ni,
240                         .d_i(slow_usb_ip_clk_en_i),
241                         .q_o(usb_ip_clk_en_o)
242                       );
243                     
244                       prim_flop_2sync # (
245                         .Width(1)
246                       ) u_sleeping_sync (
247                         .clk_i,
248                         .rst_ni,
249                         .d_i(core_sleeping_i),
250                         .q_o(core_sleeping_o)
251                       );
252                     
253                       prim_pulse_sync u_scdc_sync (
254                         .clk_src_i(clk_slow_i),
255                         .rst_src_ni(rst_slow_ni),
256                         .src_pulse_i(slow_cdc_sync),
257                         .clk_dst_i(clk_i),
258                         .rst_dst_ni(rst_ni),
259                         .dst_pulse_o(cdc_sync_done_o)
260                       );
261                     
262                       always_ff @(posedge clk_i or negedge rst_ni) begin
263        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
264        1/1                pwrup_cause_toggle_q2 <= 1'b0;
           Tests:       T1 T2 T3 
265                         end else begin
266        1/1                pwrup_cause_toggle_q2 <= pwrup_cause_toggle_q;
           Tests:       T1 T2 T3 
267                         end
268                       end
269                     
270        1/1            assign pwrup_cause_chg = pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q;
           Tests:       T1 T2 T3 
271                     
272                       always_ff @(posedge clk_i or negedge rst_ni) begin
273        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
274        1/1                pwrup_cause_o <= Por;
           Tests:       T1 T2 T3 
275        1/1              end else if (pwrup_cause_chg) begin
           Tests:       T1 T2 T3 
276        1/1                pwrup_cause_o <= slow_pwrup_cause_i;
           Tests:       T1 T3 T4 
277                         end
                        MISSING_ELSE

---

Cond Coverage for Module : pwrmgr_cdc

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       163
 EXPRESSION (slow_ast_q2 == slow_ast_q)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : pwrmgr_cdc

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
IF	151	2	2	100.00
IF	161	3	3	100.00
IF	173	3	3	100.00
IF	263	2	2	100.00
IF	273	3	3	100.00

151            if (!rst_slow_ni) begin
               -1-  
152              slow_ast_q2 <= PWR_AST_RSP_SYNC_DEFAULT;
                 ==>
153            end else begin
154              slow_ast_q2 <= slow_ast_q;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

161            if (!rst_slow_ni) begin
               -1-  
162              slow_ast_o <= PWR_AST_RSP_SYNC_DEFAULT;
                 ==>
163            end else if (slow_ast_q2 == slow_ast_q) begin
                        -2-  
164              // Output only updates whenever sync and delayed outputs both agree.
165              // If there are delays in sync, this will result in a 1 cycle difference
166              // and the output will hold the previous value
167              slow_ast_o <= slow_ast_q2;
                 ==>
168            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

173            if (!rst_slow_ni) begin
               -1-  
174              slow_wakeup_en_o <= '0;
                 ==>
175              slow_reset_en_o <= '0;
176              slow_main_pd_no <= '1;
177              slow_io_clk_en_o <= '0;
178              slow_core_clk_en_o <= '0;
179              slow_usb_clk_en_lp_o <= '0;
180              slow_usb_clk_en_active_o <= 1'b1;
181            end else if (slow_cdc_sync) begin
                        -2-  
182              slow_wakeup_en_o <= wakeup_en_i;
                 ==>
183              slow_reset_en_o <= reset_en_i;
184              slow_main_pd_no <= main_pd_ni;
185              slow_io_clk_en_o <= io_clk_en_i;
186              slow_core_clk_en_o <= core_clk_en_i;
187              slow_usb_clk_en_lp_o <= usb_clk_en_lp_i;
188              slow_usb_clk_en_active_o <= usb_clk_en_active_i;
189            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

263            if (!rst_ni) begin
               -1-  
264              pwrup_cause_toggle_q2 <= 1'b0;
                 ==>
265            end else begin
266              pwrup_cause_toggle_q2 <= pwrup_cause_toggle_q;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

273            if (!rst_ni) begin
               -1-  
274              pwrup_cause_o <= Por;
                 ==>
275            end else if (pwrup_cause_chg) begin
                        -2-  
276              pwrup_cause_o <= slow_pwrup_cause_i;
                 ==>
277            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3